CN102063146A - Adaptive frequency-compensation linear voltage stabilizer with low voltage difference - Google Patents
Adaptive frequency-compensation linear voltage stabilizer with low voltage difference Download PDFInfo
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Abstract
The invention relates to an adaptive frequency-compensation linear voltage stabilizer with low voltage difference. The voltage stabilizer comprises an error amplifier, a first buffer, a second buffer with adaptive frequency compensation function, a power P-type metal oxide semiconductor tube (PM0), a first feedback resistor (R1), a second feedback resistor (R2), an off-chip capacitor (C0) and a bonding wire resistor (CL). A buffer circuit of a second level can automatically adjust the bias current according to the condition of a drive load so as to adjust the output impedance and realize dynamic frequency compensation on the linear voltage stabilizer with low voltage difference. Compared with the traditional linear voltage stabilizer with low voltage difference, the voltage stabilizer has the characteristics of high loop bandwidth, strong drive adaptability, and stable output waveform during switching among different driving current modes.
Description
Technical field
The present invention relates to a kind of adaptive frequency compensation low pressure difference linear voltage regulator, can be operated under the 2-5V input voltage, 1.8V is provided fixedly output voltage, maximum can drive the 100mA electric current.Have loop bandwidth big, drive adaptability strong, between the different driving current-mode in the handoff procedure, output waveform is characteristics stably.
Background technology
Low pressure difference linear voltage regulator has purposes widely in integrated circuit, generally being used for provides stable core voltage for the chip internal circuit.Low pressure difference linear voltage regulator can be operated in the very wide input voltage range, has very strong power adaptation.In addition, use low pressure difference linear voltage regulator also can eliminate the burr and the interference of external power source to a certain extent.Particularly make battery-powered occasion, at present the core power voltage of a lot of analog-digital chips is at 1.2V-1.8V, and the voltage of battery is normally fixing.Integrated low-voltage difference linear constant voltage regulator in chip, the chip that so has different core voltage just can be operated under the same supply voltage, realizes the practical dirigibility of height.Because low pressure difference linear voltage regulator adopts feedback arrangement usually, the mismatch error amplifier can be realized higher Power Supply Rejection Ratio in certain bandwidth, eliminated the influence of external power source noise and undesired signal.
Low pressure difference linear voltage regulator is used as power supply at chip internal and is used, and its output current has very wide variation range.Corresponding equivalent output load can change to tens Europe from the hundreds of megaohm always, and from the feedback control loop of low pressure difference linear voltage regulator, the position of its output limit can change tens thousand of times.This brings very big challenge can for the stability Design of whole low pressure difference linear voltage regulator feedback control loop.In order to eliminate the influence of this effect, common way is at output terminal very big electric capacity in parallel, moves the output limit to enough low position.Be lower than the position of second limit of loop up to the unit gain frequency of feedback control loop under the minimum load situation.Thereby guaranteed that loop phase nargin is greater than 45 degree under worst condition.But the consequence of doing like this has been an in parallel too big electric capacity (normally tens of to hundreds of μ F) makes that loop bandwidth has seriously been limited, to disturbing and the also decline to some extent of inhibition ability of power-supply fluctuation.Another kind method is to use impact damper (normally source follower) to improve second, the position of the 3rd limit, make these limits away from dominant pole (output limit), even the position of dominant pole (output limit) changes a lot, the position of inferior limit is all the time greater than unit gain frequency.But the major defect of doing like this is to realize higher inferior pole location, needs very big electric current to drive these impact dampers.Such way has directly caused the high power consumption of low pressure difference linear voltage regulator.Do not have the more impact damper of high current efficiency in order when improving time pole location, not increase too much extra power consumption, need to design, promptly under lower bias current, can realize very low output resistance.Can introduce the adaptive frequency compensation technology in addition, promptly time pole location is according to the variation of dominant pole and respective change, when low, only needs lower electric current can realize just guaranteeing that time limit is greater than unit gain frequency in the dominant pole position.And be load when low at the big electric current of output, impact damper is injected extra current, make time limit increase with identical speed with dominant pole, continue the stability of assurance loop.
Summary of the invention
Technical matters:The object of the present invention is to provide a kind of use adaptive frequency compensation technology, comprise the low differential voltage linear voltage stabilizer circuit of two-stage buffer stage.
Technical scheme:For solving the problems of the technologies described above, technical scheme provided by the invention is: a kind of adaptive frequency compensation low pressure difference linear voltage regulator, this voltage stabilizer comprises error amplifier, first impact damper, has second impact damper and the power P type metal oxide semiconductor pipe of adaptive frequency compensation function, first feedback resistance, second feedback resistance, the outer electric capacity of sheet, bonding line resistance; Wherein, reference current is by the input of N type metal oxide semiconductor pipe; Input supply voltage is the power end of error originated from input amplifier respectively, the power end of first impact damper, have the power end of second impact damper of adaptive frequency compensation function and the source electrode of power P type metal oxide semiconductor pipe, the input end of output termination first impact damper of error amplifier, the input end of output termination second impact damper of first impact damper, the grid of the output termination power P type metal oxide semiconductor pipe of second impact damper, the drain electrode of power P type metal oxide semiconductor pipe connects the upper end of first feedback resistance, the upper end of the following termination of first feedback resistance feedback two resistance and the positive input terminal of error amplifier, the lower end ground connection of second feedback resistance, the bottom crown ground connection of the outer electric capacity of sheet, top crown is received output port by bonding line resistance, the negative input end input reference voltage of error amplifier, second impact damper that wherein has the adaptive frequency compensation function is regulated bias current automatically according to the situation that drives load, thereby output impedance is adjusted, to realize dynamic frequency compensation to this low pressure difference linear voltage regulator.
Preferably, described reference voltage is 1.2 volts.
Preferably, described second impact damper that has the adaptive frequency compensation function comprises the 11 NMOS pipe, the 12 NMOS pipe, the 30 NMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 12 NMOS pipe, the 17 NMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe, the tenth transistor; The grid of the 12 NMOS pipe connects the grid of N type metal oxide semiconductor pipe, and drain terminal is connected respectively to the drain terminal of the 16 PMOS pipe and the source end of the 13 NMOS pipe; The 11 NMOS pipe drain-source short circuit, the grid of the 11 NMOS pipe connects the grid of the 12 NMOS pipe; The grid of the 13 NMOS pipe connects the reference voltage of 1.2V, and the drain electrode of the 13 NMOS pipe connects the drain electrode of the 14 PMOS pipe PMOS pipe; The source electrode of the 14 PMOS pipe connects input supply voltage; The tenth NMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe provides image current for the 14 PMOS pipe; The source termination input supply voltage of the 15 PMOS pipe, grid connects the drain electrode of the 14 PMOS pipe; The drain electrode of the 15 PMOS pipe connects the source electrode of the 16 PMOS pipe; The grid short circuit of little breadth length ratio the 17 NMOS pipe is connected to the drain electrode of the 16 PMOS pipe.
Preferably, described second impact damper that has the adaptive frequency compensation function also comprises the adaptive frequency compensation circuit, and this adaptive frequency compensation circuit comprises the 18 NMOS pipe, the 19 NOMS pipe, the 20 PMOS pipe, power tube, the 3rd resistance and first electric capacity; The source electrode of power tube connects input supply voltage, and drain electrode connects the upper end of first feedback resistance, and the source electrode of the 20 PMOS pipe connects input supply voltage, and the grid of the 20 PMOS pipe connects the grid of power tube; The drain electrode of the 20 PMOS pipe connects the drain electrode of the 19 PMOS pipe, and the 19 gate pmos leaks short circuit, source ground; The 18 PMOS manages source ground, and drain electrode connects the drain electrode of the 16 PMOS pipe, and grid connects the grid of the 19 PMOS pipe; The 3rd resistance and first capacitances in series, the grid of the 3rd resistance one termination the 15 PMOS pipe, another termination input supply voltage.
Beneficial effect:Add the two-stage buffer stage, can use the outer electric capacity (1 μ F) of lower sheet, guaranteed the loop bandwidth of this low pressure difference linear voltage regulator.Used second buffer stage of mutual conductance bootstrapping and introduced the motional impedance adjustment technology simultaneously, made second limit change synchronously with the output limit, only injection current in needs has improved the electric current utilization ratio.This circuit have drive adaptability strong, between the different driving current-mode in the handoff procedure, output waveform is characteristics stably.
Description of drawings
Fig. 1 is a low pressure difference linear voltage regulator main body circuit block diagram of the present invention;
Fig. 2 is the circuit theory diagrams of low pressure difference linear voltage regulator of the present invention;
Fig. 3 is the circuit theory diagrams of second buffer stage of the present invention;
Fig. 4 is the loop amplitude-versus-frequency curve of low pressure difference linear voltage regulator of the present invention under maximum and no drive current situation; Wherein solid line is the maximum current drive pattern, and dotted line is the minimum current drive pattern;
Fig. 5 is the loop phase-frequency characteristic curve of low pressure difference linear voltage regulator of the present invention under maximum and no drive current situation; Wherein solid line is the maximum current drive pattern, and dotted line is the minimum current drive pattern;
Fig. 6 is low pressure difference linear voltage regulator of the present invention time domain waveform in the handoff procedure between maximum drive current (100mA) and no drive current pattern.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing.
Referring to Fig. 1-6, a kind of adaptive frequency compensation low pressure difference linear voltage regulator provided by the invention is characterized in that:
This voltage stabilizer comprises error amplifier, first impact damper, has second impact damper and the power P type metal oxide semiconductor pipe PM0 of adaptive frequency compensation function, the first feedback resistance R1, the second feedback resistance R2, sheet outer electric capacity C0, bonding line resistance CL; Wherein, reference current is by N type metal oxide semiconductor pipe M0 input; Input supply voltage is the power end of error originated from input amplifier respectively, the power end of first impact damper, have the power end of second impact damper of adaptive frequency compensation function and the source electrode of power P type metal oxide semiconductor pipe PM0, the input end of output termination first impact damper of error amplifier, the input end of output termination second impact damper of first impact damper, the grid of the output termination power P type metal oxide semiconductor pipe PM0 of second impact damper, the drain electrode of power P type metal oxide semiconductor pipe PM0 connects the upper end of the first feedback resistance R1, the upper end of the following termination of first feedback resistance R1 feedback, two resistance R 2, the lower end ground connection of the second feedback resistance R2, the positive input terminal of the last termination error amplifier of the second feedback resistance R2, the bottom crown ground connection of the outer electric capacity C0 of sheet, top crown is received output port CL by bonding line resistance, the negative input end input reference voltage of error amplifier, second impact damper that wherein has the adaptive frequency compensation function regulated bias current automatically according to the situation that drives load, thereby output impedance is adjusted, to realize dynamic frequency compensation to this low pressure difference linear voltage regulator.
Described reference voltage is 1.2 volts.
Described second impact damper that has the adaptive frequency compensation function comprises that the 11 NMOS pipe M11, the 12 NMOS pipe M12, the 30 NMOS manage M13, the 14 PMOS pipe M14, the 15 PMOS pipe M15, the 16 PMOS manage M16, the 12 NMOS manages M12, the 17 NMOS manages M17, the 8th PMOS manages M8, the 9th PMOS manages M9, the tenth transistor M10; The grid of the 12 NMOS pipe M12 connects the grid current mirror of N type metal oxide semiconductor pipe M0, and drain terminal is connected respectively to the drain terminal of the 16 PMOS pipe M16 and the source end of the 13 NMOS pipe M13; The 11 NMOS pipe M11 drain-source short circuit, the grid of the 11 NMOS pipe M11 connects the grid of the 12 NMOS pipe M12; The grid of the 13 NMOS pipe M13 connects the reference voltage of 1.2V, and the drain electrode of the 13 NMOS pipe M13 connects the drain electrode of the 14 PMOS pipe PMOS pipe M14; The source electrode of the 14 PMOS pipe M14 connects input supply voltage; The tenth NMOS manages M10, and the 8th PMOS manages M8, and the 9th PMOS pipe M9 provides image current for the 14 PMOS pipe M14; The source termination input supply voltage of the 15 PMOS pipe M15, grid connects the drain electrode of the 14 PMOS pipe M14; The drain electrode of the 15 PMOS pipe M15 connects the source electrode of the 16 PMOS pipe M16; The grid short circuit of little breadth length ratio the 17 NMOS pipe M17 is connected to the drain electrode of the 16 PMOS pipe M16.
Described second impact damper that has the adaptive frequency compensation function also comprises the adaptive frequency compensation circuit, and this adaptive frequency compensation circuit comprises the 18 NMOS pipe M18, the 19 NOMS pipe M19, the 20 PMOS pipe M20, power tube M21, the 3rd resistance R 3 and first capacitor C 1; The source electrode of power tube 21 connects input supply voltage, and drain electrode connects the upper end of the first feedback resistance R1, and the source electrode of the 20 PMOS pipe M20 connects input supply voltage, and the grid of the 20 PMOS pipe M20 connects the grid of power tube M21; The drain electrode of the 20 PMOS pipe M20 connects the drain electrode of the 19 PMOS pipe M19, the 19 PMOS pipe M19 grid leak short circuit, source ground; The 18 PMOS pipe M18 source ground, drain electrode connects the drain electrode of the 16 PMOS pipe M16, and grid connects the grid of the 19 PMOS pipe M19; The 3rd resistance R 3 and 1 series connection of first capacitor C, the grid of the 3rd resistance R 3 one terminations the 15 PMOS pipe M15, another termination input supply voltage.
Particularly, this low pressure difference linear voltage regulator comprises error amplifier, buffer stage 1, the buffer stage 2 that has the adaptive frequency compensation function, power P type metal oxide semiconductor pipe (PMOS pipe) PM0, the first feedback resistance R1, the second feedback resistance R2, input supply voltage is an error amplifier, first buffer stage 1, second buffer stage 2, the PM0 power supply, the negative input end of error amplifier connects the 1.2V reference voltage, the output of error amplifier connects the input of first buffer stage, the output of first buffer stage connects the input of second buffer stage, the output of second buffer stage meets PM0, the source termination input power supply of PM0, the drain terminal of PM0 is the upper end that output port connects first resistance R 1, the upper end of following termination second resistance R 2 of R1, the lower end ground connection of R2.The positive input terminal of the last termination error amplifier of R2.The bottom crown ground connection of the outer electric capacity C0 of sheet, top crown is received output port by bonding line resistance.
Reference current provides bias current by current mirror for error amplifier, first buffer stage, second buffer stage by N type metal oxide semiconductor pipe (NMOS pipe) M0 input.Error amplifier is by tail current source M0, differential pair NMOS pipe M1, M2, and load pipe M4, M5 form.First buffer stage is managed M6 by NMOS, and M7 forms.The grid of M6 connect the drain terminal of M5, and the drain terminal of M6 connects the input power supply, the drain terminal of the source termination tail current source M7 of M6, the source end ground connection of M7.PMOS pipe M8, M9, M14, M15, M16, M20 and NMOS pipe M10, M11, M12, M13, M17, M18, M19, M20 form self-regulating second buffer stage of band output impedance.The grid of M16 connect the source end of the first buffer stage M6 as the input end of second buffer stage, and the source end of M16 connects the grid of power tube M21 as the output of second buffer stage.
The second buffer stage circuit has automatic adjusting output impedance function.The main part of this buffer stage is managed M12, M13 by NMOS, and PMOS pipe M14, M15, M16 form.The grid of tail current source M12 connect current mirror, and drain terminal is connected respectively to the drain terminal of M16 and the source end of M13.NMOS pipe M11 drain-source short circuit, the grid of M11 connects the grid of M12.The grid of M13 connects the reference voltage of 1.2V, and the drain electrode of M13 connects the drain electrode of PMOS pipe M14.The source electrode of M14 connects input supply voltage.NMOS manages M10, and the PMOS pipe M8, M9 provide image current for M14.The source termination input supply voltage of M15, grid connects the drain electrode of M14.The drain electrode of M15 connects the source electrode of M16.Little breadth length ratio NMOS manages the grid leak short circuit of M17, is connected to the drain terminal of M16.The adaptive frequency compensation circuit manages M18, M19 by NMOS and PMOS pipe M20 forms.The source electrode of M20 connects input supply voltage, and the grid of M20 connects the grid of power tube M21.The drain electrode of M20 connects the drain electrode of M19, M19 grid leak short circuit, source ground.The M18 source ground, drain electrode connects the drain electrode of M16, and grid connects the grid of M19.Resistance R 3 and capacitor C 1 series connection, the grid of a termination M15, another termination input supply voltage.
Wherein second level buffer circuit can be regulated bias current automatically according to the situation that drives load, thereby output impedance is adjusted, to realize the dynamic frequency compensation to this low pressure difference linear voltage regulator.The present invention with respect to traditional low pressure difference linear voltage regulator have loop bandwidth big, drive adaptability strong, between the different driving current-mode in the handoff procedure, output waveform is characteristics stably.
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.
Fig. 1 is a low pressure difference linear voltage regulator main body circuit block diagram of the present invention; Fig. 2 is the detailed circuit schematic diagram of low pressure difference linear voltage regulator of the present invention.The mutual conductance boostrap circuit as second buffer stage of Fig. 3 also is a part of the present invention.Fig. 4 is the loop amplitude-versus-frequency curve of low pressure difference linear voltage regulator of the present invention under maximum and no drive current situation; Wherein solid line is the maximum current drive pattern, and dotted line is the minimum current drive pattern; Fig. 5 is the loop phase-frequency characteristic curve of low pressure difference linear voltage regulator of the present invention under maximum and no drive current situation; Wherein solid line is the maximum current drive pattern, and dotted line is the minimum current drive pattern; From the content of Fig. 4 and Fig. 5 as can be seen, when output current when 0 changes to 100mA, loop dominant pole position changes to 10KHz from 1Hz.But is also moving toward high frequency treatment the position of inferior limit, guarantees that all the time time pole location is more than unit gain frequency.Guaranteed loop stability.Can learn that in conjunction with amplitude-versus-frequency curve and phase-frequency characteristic curve the phase margin of loop is in more than 60 degree all the time.Fig. 6 is low pressure difference linear voltage regulator of the present invention time domain waveform in the handoff procedure between maximum drive current (100mA) and no drive current pattern; As can be seen, under the worst condition of load changing, output voltage is also corresponding to have produced variation from the figure, but its amplitude of variation can be ignored substantially to the influence that circuit produces in 10mV.And this respective waveforms transition is steady, has shown transient response characteristic preferably.
The above only is a better embodiment of the present invention; protection scope of the present invention is not exceeded with above-mentioned embodiment; as long as the equivalence that those of ordinary skills do according to disclosed content is modified or changed, all should include in the protection domain of putting down in writing in claims.
Claims (4)
1. adaptive frequency compensation low pressure difference linear voltage regulator is characterized in that:
This voltage stabilizer comprises error amplifier, first impact damper, has second impact damper and the power P type metal oxide semiconductor pipe (PM0) of adaptive frequency compensation function, first feedback resistance (R1), second feedback resistance (R2), the outer electric capacity (C0) of sheet, bonding line resistance (CL); Wherein,
Reference current is by N type metal oxide semiconductor pipe (M0) input;
Input supply voltage is the power end of error originated from input amplifier respectively, and the power end of first impact damper has the power end of second impact damper of adaptive frequency compensation function and the source electrode of power P type metal oxide semiconductor pipe (PM0),
The input end of output termination first impact damper of error amplifier, the input end of output termination second impact damper of first impact damper, the grid of the output termination power P type metal oxide semiconductor pipe (PM0) of second impact damper,
The drain electrode of power P type metal oxide semiconductor pipe (PM0) connects the upper end of first feedback resistance (R1), the upper end of the following termination of first feedback resistance (R1) feedback two resistance (R2) and the positive input terminal of error amplifier, the lower end ground connection of second feedback resistance (R2), the bottom crown ground connection of the outer electric capacity (C0) of sheet, top crown is received output port (CL) by bonding line resistance, the negative input end input reference voltage of error amplifier
Second impact damper that wherein has the adaptive frequency compensation function is regulated bias current automatically according to the situation that drives load, thereby output impedance is adjusted, to realize the dynamic frequency compensation to this low pressure difference linear voltage regulator.
2. adaptive frequency compensation low pressure difference linear voltage regulator according to claim 1 is characterized in that: described reference voltage is 1.2 volts.
3. adaptive frequency compensation low pressure difference linear voltage regulator according to claim 1 is characterized in that: described second impact damper that has the adaptive frequency compensation function comprises
The 11 NMOS pipe (M11), the 12 NMOS pipe (M12), the 30 NMOS manage (M13), the 14 PMOS pipe (M14), the 15 PMOS pipe (M15), the 16 PMOS manage (M16), the 12 NMOS manages (M12), the 17 NMOS manages (M17), the 8th PMOS manages (M8), the 9th PMOS manages (M9), the tenth transistor (M10);
The grid of the 12 NMOS pipe (M12) connects the grid of N type metal oxide semiconductor pipe (M0), and drain terminal is connected respectively to the drain terminal of the 16 PMOS pipe (M16) and the source end of the 13 NMOS pipe (M13);
The 11 NMOS pipe (M11) drain-source short circuit, the grid of the 11 NMOS pipe (M11) connects the grid of the 12 NMOS pipe (M12); The grid of the 13 NMOS pipe (M13) connects the reference voltage of 1.2V, and the drain electrode of the 13 NMOS pipe (M13) connects the drain electrode of the 14 PMOS pipe PMOS pipe (M14); The source electrode of the 14 PMOS pipe (M14) connects input supply voltage;
The tenth NMOS manages (M10), and the 8th PMOS manages (M8), and the 9th PMOS pipe (M9) is that the 14 PMOS pipe (M14) provides image current; The source termination input supply voltage of the 15 PMOS pipe (M15), grid connect the drain electrode of the 14 PMOS pipe (M14); The drain electrode of the 15 PMOS pipe (M15) connects the source electrode of the 16 PMOS pipe (M16); The grid short circuit of little breadth length ratio the 17 NMOS pipe (M17) is connected to the drain electrode of the 16 PMOS pipe (M16).
4. adaptive frequency compensation low pressure difference linear voltage regulator according to claim 3, it is characterized in that: described second impact damper that has the adaptive frequency compensation function also comprises the adaptive frequency compensation circuit, and this adaptive frequency compensation circuit comprises that the 18 NMOS pipe (M18), the 19 NOMS pipe (M19), the 20 PMOS manage (M20), power tube (M21), the 3rd resistance (R3) and first electric capacity (C1);
The source electrode of power tube (21) connects input supply voltage, and drain electrode connects the upper end of first feedback resistance (R1), and the source electrode of the 20 PMOS pipe (M20) connects input supply voltage, and the grid of the 20 PMOS pipe (M20) connects the grid of power tube (M21); The drain electrode of the 20 PMOS pipe (M20) connects the drain electrode of the 19 PMOS pipe (M19), the 19 PMOS pipe (M19) grid leak short circuit, source ground; The 18 PMOS manages (M18) source ground, and drain electrode connects the drain electrode of the 16 PMOS pipe (M16), and grid connects the grid of the 19 PMOS pipe (M19); The 3rd resistance (R3) and first electric capacity (C1) series connection, the grid of the 3rd resistance (R3) termination the 15 PMOS pipe (M15), another termination input supply voltage.
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Open date: 20110518 |