CN103107791A - Gain linear variable gain amplifier with constant bandwidth - Google Patents
Gain linear variable gain amplifier with constant bandwidth Download PDFInfo
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- CN103107791A CN103107791A CN2012105908663A CN201210590866A CN103107791A CN 103107791 A CN103107791 A CN 103107791A CN 2012105908663 A CN2012105908663 A CN 2012105908663A CN 201210590866 A CN201210590866 A CN 201210590866A CN 103107791 A CN103107791 A CN 103107791A
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Abstract
The invention discloses a gain linear variable gain amplifier with a constant bandwidth. The gain linear variable gain amplifier with the constant bandwidth comprises a common source class amplifier and a gain regulating network. The common source class amplifier comprises a first N type metallic oxide transistor, a fifth N type metallic oxide transistor, a first P type metallic oxide transistor, a second P type metallic oxide transistor and a first current source. The gain regulating network comprises N type metallic oxide transistors ranging from a second N type metallic oxide transistor to an eighth N type metallic oxide transistor, current sources ranging from a second current source to a tenth current source and switches ranging from a first switch to a fifteenth switch. The gain linear variable gain amplifier with the constant bandwidth has the advantage of being stable in bandwidth and meanwhile is capable of enabling the gain to achieve accurate linear effect through different control words.
Description
Technical field
The present invention relates to a kind of amplifier, specifically, relate to the constant gain linearity variable gain amplifier of a kind of bandwidth.
Background technology
In the radiofrequency signal receiver, the effect of variable gain amplifier is to guarantee the constant of output signal in the scope that input signal changes.Consider from whole receiver, amplifier should have the higher linearity.In addition, variable gain amplifier should have as one of major part of ifd module stable transfer and the non-band signal of more effective inhibition that good bandwidth guarantees signal.
Variable gain amplifier can be divided into analog signal control variable gain amplifier and Digital Signals variable gain amplifier according to the difference of control signal.Variable gain amplifier is controlled in simulation needs independent structural index voltage generation circuit, comparatively difficult under CMOS realizes.The digital control variable gain amplifier realizes that by the control figure coded system dB of gain is linear.Control variable gain amplifier than analog signal, the Digital Signals variable gain amplifier does not need independent structural index voltage generation circuit, and can improve gain accuracy in discrete point optimized gain value, is conducive to low-power consumption simultaneously yet.Therefore, digital variable gain amplifier more and more becomes the main way in the radio frequency reception link.
Digital variable gain amplifier mainly is divided into open loop structure and closed-loop structure.The two is all to realize the dB linear relationship of gain and digital signal by the Digital Signals switch.Thereby closed-loop structure realizes gain-variable by changing feedback network change feedback factor, and its gain accuracy is high, but has the shortcomings such as bandwidth is less, power consumption is larger; Open loop structure is mainly realized gain-variable by changing equivalent transconductance or output impedance, and generally its gain control range is larger, broader bandwidth, and power consumption is lower, but gain accuracy is relatively poor.Common open loop structure has a lot, and based on the variable gain amplifier of programmable load, although can realize the dB linear change that gains, the bandwidth of amplifier can reduce along with the increase of gain.Based on the variable gain amplifier of diode load differential pair, change the gain of amplifier by the mutual conductance that changes input pipe and load pipe, be faced with equally the problem that bandwidth changes.
Simultaneously, general variable gain amplifier based on programmable trans-conductance by simple change input pipe size or change the mutual conductance that bias current changes input pipe, when single varying sized or electric current, the overdrive voltage of input pipe changes, make the transistor drain-source voltage as bias current sources change, thereby make the current source error change that produces in the current mirror mode larger.
Summary of the invention
Goal of the invention: for the problem and shortage of above-mentioned prior art existence, the purpose of this invention is to provide the constant gain linearity variable gain amplifier of a kind of bandwidth, the amplifier of this structure has the constant characteristics of bandwidth, by conducting and the disconnection of control word control switch, can make gain reach accurate linear relationship simultaneously.
Technical scheme: for achieving the above object, the technical solution used in the present invention is the constant gain linearity variable gain amplifier of a kind of bandwidth, and this variable gain amplifier comprises common-source stage amplifier and gain-adjusted network; Wherein:
The common-source stage amplifier comprises the first N-type MOS transistor, the 5th N-type MOS transistor, a P type MOS transistor, the 2nd P type MOS transistor and the first current source;
the gain-adjusted network comprises the second N-type MOS transistor, the 3rd N-type MOS transistor, the 4th N-type MOS transistor, the 6th N-type MOS transistor, the 7th N-type MOS transistor, the 8th N-type MOS transistor, the second current source, the 3rd current source, the 4th current source, the 5th current source, the 6th current source, the 7th current source, the 8th current source, the 9th current source, the tenth current source, the first switch, second switch, the 3rd switch, the 4th switch, the 5th switch, the 6th switch, minion is closed, the 8th switch, the 9th switch, the tenth switch, the 11 switch, twelvemo is closed, the 13 switch, the 14 switch and the 15 switch,
The input signal anode is connected with the grid of the first N-type MOS transistor, the second N-type MOS transistor, the 3rd N-type MOS transistor and the 4th N-type MOS transistor; The drain electrode of the drain electrode of the first N-type MOS transistor and a P type MOS transistor connects, and the drain electrode of a P type MOS transistor is connected with grid, and the source electrode of a P type MOS transistor connects supply voltage; The source electrode of the first N-type MOS transistor is connected with the source electrode of the second N-type MOS transistor, the source electrode of the 3rd N-type MOS transistor, the source electrode of the 4th N-type MOS transistor, the source electrode of the 5th N-type MOS transistor, the source electrode of the 6th N-type MOS transistor, the source electrode of the 7th N-type MOS transistor and the source electrode of the 8th N-type MOS transistor, is connected with an end of the first current source, the first switch, second switch and the 3rd switch simultaneously; The other end of the first switch is connected with an end of the second current source, and the other end of second switch is connected with an end of the 3rd current source, and the other end of the 3rd switch is connected with an end of the 4th current source; The other end ground connection of the first current source, the second current source, the 3rd current source and the 4th current source; One end of the 4th switch is connected with the drain electrode of the second N-type MOS transistor, and an end of the 5th switch is connected with the drain electrode of the 3rd N-type MOS transistor, and an end of the 6th switch is connected with the drain electrode of the 4th N-type MOS transistor; The other end of the 4th switch, the 5th switch and the 6th switch is connected with the drain electrode of the first N-type MOS transistor, is connected with the end that the tenth switch, the 11 switch and twelvemo are closed simultaneously, as the anode of amplifier output signal; The other end of the tenth switch is connected with an end of the 7th current source, and the other end of the 11 switch is connected with an end of the 6th current source, and the other end that twelvemo is closed is connected with an end of the 5th current source; Another termination supply voltage of the 5th current source, the 6th current source and the 7th current source; The input signal negative terminal is connected with the grid of the 5th N-type MOS transistor, the 6th N-type MOS transistor, the 7th N-type MOS transistor and the 8th N-type MOS transistor; The drain electrode of the drain electrode of the 5th N-type MOS transistor and the 2nd P type MOS transistor connects, and the drain electrode of the 2nd P type MOS transistor is connected with grid, and the source electrode of the 2nd P type MOS transistor connects supply voltage; The end that minion is closed is connected with the drain electrode of the 6th N-type MOS transistor, and an end of the 8th switch is connected with the drain electrode of the 7th N-type MOS transistor, and an end of the 9th switch is connected with the drain electrode of the 8th N-type MOS transistor; The other end of minion pass, the 8th switch and the 9th switch is connected with the drain electrode of the 5th N-type MOS transistor, is connected with an end of the 13 switch, the 14 switch and the 15 switch simultaneously, as the negative terminal of amplifier output signal; The other end of the 13 switch is connected with an end of the 8th current source, and the other end of the 14 switch is connected with an end of the 9th current source, and the other end of the 15 switch is connected with an end of the tenth current source; Another termination supply voltage of the 8th current source, the 9th current source and the tenth current source.
Beneficial effect: compared with prior art, the present invention has following beneficial effect:
1. bandwidth is constant.Variable gain amplifier of the present invention is in the afterbody of receiver system analog signal link, and the input signal of amplifier is operated in the low frequency state.It is very little that variable gain amplifier of the present invention, bandwidth are subject to the impact of change in gain, basically remains unchanged, the signal beyond like this can better filtering bandwidth.The variable gain amplifier that bandwidth of the present invention is constant makes a P type MOS transistor connect in the diode mode with the 2nd P type MOS transistor and as the load of two differential circuits, controls current source in parallel by the switch control word and make the electric current that flows through a P type MOS transistor and the 2nd P type MOS transistor not guarantee that its impedance is constant.If this transistor impedance is less, the output impedance of amplifier is mainly determined by this transistor impedance, this transistor output grid source electric capacity is larger simultaneously, and on output node, other transistorized gate leakage capacitances are very little, the output capacitance size is mainly also determined by this transistor, thereby it is very little to guarantee that bandwidth changes, and basically keeps constant.
2. the gain linearity relation is accurate.In whole receiver system, variable gain amplifier is in back segment, and therefore, the linearity of amplifier height directly has influence on the performance of whole receiver.Variable gain amplifier of the present invention has been realized digital control word and the accurate linear relationship of gain.In the breadth length ratio of variable gain amplifier of the present invention by switch control word the first N-type MOS transistor and the 5th N-type MOS transistor in controlling common-source amplifier, change corresponding bias current size, make the mutual conductance of amplifier input pipe and control word linear.The overdrive voltage that guarantees simultaneously input pipe is constant, and the current source transistor drain-source voltage that makes current mirror produce is constant, thereby makes the error of current source less.Because output impedance remains unchanged basically, by different control word sizes is set, make the size of gain and control word linear, the step-length of gain is fixed simultaneously, has improved gain accuracy and the linearity.
Description of drawings
Fig. 1 is circuit diagram of the present invention;
Fig. 2 is amplitude-frequency characteristic oscillogram of the present invention;
Fig. 3 is the gain contrast figure of the present invention and traditional structure.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
as shown in Figure 1, the gain linearity variable gain amplifier that a kind of bandwidth of the present invention is constant comprises common-source stage amplifier and gain-adjusted network, wherein, the common-source stage amplifier comprises the first N-type MOS transistor N1, the 5th N-type MOS transistor N5, a P type MOS transistor P1, the 2nd P type MOS transistor P2 and the first current source I1, the gain-adjusted network comprises the second N-type MOS transistor N2, the 3rd N-type MOS transistor N3, the 4th N-type MOS transistor N4, the 6th N-type MOS transistor N6, the 7th N-type MOS transistor N7, the 8th N-type MOS transistor N8, the second current source I2, the 3rd current source I3, the 4th current source I4, the 5th current source I5, the 6th current source I6, the 7th current source I7, the 8th current source I8, the 9th current source I9, the tenth current source I10, the first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4, the 5th switch S 5, the 6th switch S 6, minion is closed S7, the 8th switch S8, the 9th switch S 9, the tenth switch S 10, the 11 switch S 11, twelvemo is closed S12, the 13 switch S 13, the 14 switch S 14 and the 15 switch S 15.
Input signal anode VIN+ is connected with the grid of the first N-type MOS transistor N1, the second N-type MOS transistor N2, the 3rd N-type MOS transistor N3 and the 4th N-type MOS transistor N4; The drain electrode of the drain electrode of the first N-type MOS transistor N1 and a P type MOS transistor P1 connects, and the drain electrode of a P type MOS transistor P1 is connected with grid, and the source electrode of a P type MOS transistor P1 connects supply voltage; The source electrode of the first N-type MOS transistor N1 is connected with the source electrode of the second N-type MOS transistor N2, the source electrode of the 3rd N-type MOS transistor N3, the source electrode of the 4th N-type MOS transistor N4, the source electrode of the 5th N-type MOS transistor N5, the source electrode of the 6th N-type MOS transistor N6, the source electrode of the 7th N-type MOS transistor N7 and the source electrode of the 8th N-type MOS transistor N8, is connected with the first current source I1, the first switch S 1, second switch S2 and an end of the 3rd switch S 3 simultaneously; The other end of the first switch S 1 is connected with the end of the second current source I2, and the other end of second switch S2 is connected with the end of the 3rd current source I3, and the other end of the 3rd switch S 3 is connected with the end of the 4th current source I4; The other end ground connection of the first current source I1, the second current source I2, the 3rd current source I3 and the 4th current source I4; One end of the 4th switch S 4 is connected with the drain electrode of the second N-type MOS transistor N2, one end of the 5th switch S 5 is connected with the drain electrode of the 3rd N-type MOS transistor N3, and an end of the 6th switch S 6 is connected with the drain electrode of the 4th N-type MOS transistor N4; The other end of the 4th switch S 4, the 5th switch S 5 and the 6th switch S 6 is connected with the drain electrode of the first N-type MOS transistor N1, an end with the tenth switch S 10, the 11 switch S 11 and twelvemo pass S12 is connected simultaneously, as the anode VOUT+ of amplifier output signal; The other end of the tenth switch S 10 is connected with the end of the 7th current source I7, and the other end of the 11 switch S 11 is connected with the end of the 6th current source I6, and the other end that twelvemo is closed S12 is connected with the end of the 5th current source I5; Another termination supply voltage of the 5th current source I5, the 6th current source I6 and the 7th current source I7; Input signal negative terminal VIN-is connected with the grid of the 5th N-type MOS transistor N5, the 6th N-type MOS transistor N6, the 7th N-type MOS transistor N7 and the 8th N-type MOS transistor N8; The drain electrode of the drain electrode of the 5th N-type MOS transistor N5 and the 2nd P type MOS transistor P2 connects, and the drain electrode of the 2nd P type MOS transistor P2 is connected with grid, and the source electrode of the 2nd P type MOS transistor P2 connects supply voltage; The end that minion is closed S7 is connected with the drain electrode of the 6th N-type MOS transistor N6, the end of the 8th switch S8 is connected with the drain electrode of the 7th N-type MOS transistor N7, and an end of the 9th switch S 9 is connected with the drain electrode of the 8th N-type MOS transistor N8; The other end that minion is closed S7, the 8th switch S8 and the 9th switch S 9 is connected with the drain electrode of the 5th N-type MOS transistor N5, be connected with an end of the 13 switch S 13, the 14 switch S 14 and the 15 switch S 15 simultaneously, as the negative terminal VOUT-of amplifier output signal; The other end of the 13 switch S 13 is connected with the end of the 8th current source I8, and the other end of the 14 switch S 14 is connected with the end of the 9th current source I9, and the other end of the 15 switch S 15 is connected with the end of the tenth current source I10; Another termination supply voltage of the 8th current source I8, the 9th current source I9 and the tenth current source I10.
The gain linearity variable gain amplifier that above-mentioned bandwidth is constant is controlled current source in parallel by switch and is made that the electric current that flows through a P type MOS transistor P1 and the 2nd P type MOS transistor P2 is constant guarantees that its impedance is constant.When this transistor impedance less, the output impedance of amplifier is mainly determined by this transistor impedance, this transistor output grid source electric capacity is larger simultaneously, and on output node, other transistorized gate leakage capacitances are very little, the output capacitance size is mainly also determined by this transistor, thereby it is very little to guarantee that bandwidth changes, and basically keeps constant.When the breadth length ratio of network by switch control word the first N-type MOS transistor and the 5th N-type MOS transistor in controlling common-source amplifier controlled in gain of the present invention, change corresponding bias current size, make the mutual conductance of amplifier input pipe and control word linear.Because output impedance remains unchanged basically, by different control word sizes is set, make the size of gain and control word linear, the step-length of gain is fixed simultaneously.
The first switch S 1, the 4th switch S 4, minion pass S7, the tenth switch S 10 and the 13 switch S 13 are controlled by a control word A1, second switch S2, the 5th switch S 5, the 8th switch S8, the 11 switch S 11 and the 14 switch S 14 are controlled by a control word A2, the 3rd switch S 3, the 6th switch S 6, the 9th switch S 9, twelvemo close S12 and the 15 switch S 15 is controlled by a control word A3, and control word signal A3A2A1 is provided by the digital module in whole automatic gain control loop.The first current source I1, the second current source I2, the 6th current source I6 and the 9th current source I9 electric current equate, the 7th current source I7 and the 8th current source I8 size of current equate and equal half of the first current source I1 electric current, the 3rd current source I3, the 5th current source I5 and the tenth current source I10 size of current equate and equal the twice of the first current source I1 electric current, and the 4th current source I4 size of current equals four times of the first current source I1 electric current.the breadth length ratio of the first N-type MOS transistor N1 and the 5th N-type MOS transistor N5 equates, the breadth length ratio of the second N-type MOS transistor N2 and the 6th N-type MOS transistor N6 equates and equals the breadth length ratio of the first N-type MOS transistor N1, the breadth length ratio of the 3rd N-type MOS transistor N3 and the 7th N-type MOS transistor N7 equates and equals the twice of the first N-type MOS transistor N1 breadth length ratio, the breadth length ratio of the 4th N-type MOS transistor N4 and the 8th N-type MOS transistor N8 equates and equals four times of the first N-type MOS transistor N1 breadth length ratio.Low frequency difference signal is added in respectively anode VIN+ and negative terminal VIN-, when the first to the 15 switch S 1-S15 all disconnects, the voltage small-signal converts Small Current Signal to by the first N-type MOS transistor N1 and the 5th N-type MOS transistor N5 respectively, the first current source I1 provides current offset for common-source amplifier, the one P type MOS transistor P1 connects in the diode mode respectively with the 2nd P type MOS transistor P2, as the load of difference branch road.The drain electrode of the first N-type MOS transistor N1 and the 5th N-type MOS transistor N5 is respectively as positive output end VOUT+ and the negative output terminal VOUT-of amplifier.When control word A3A2A1 is 01, namely the first switch S 1, the 4th switch S 4, minion are closed S7, the tenth switch S 10 and the 13 switch S 13 closures, the electric current of the second current source I2 is by the 7th current source I7 and the 8th current source I8 shunting, the electric current that flows through a P type MOS transistor P1 and the 2nd P type MOS transistor P2 remains unchanged, these two transistor equivalent impedances are in the inverse of mutual conductance, therefore impedance is constant and less.Simultaneously, the electric current of the 7th current source I7 flows through the second N-type MOS transistor N2 entirely, and the electric current of the 8th current source I8 flows through the 6th N-type MOS transistor N6 entirely.The impedance of seeing into from output mainly determines by the equiva lent impedance of a P type MOS transistor P1 and the 2nd P type MOS transistor P2, i.e. output impedance remains unchanged basically.The output node place, the parasitic capacitance of the one P type MOS transistor P1 and the 2nd P type MOS transistor P2 is mainly grid source electric capacity and larger, gate leakage capacitance and other transistors of introducing work, the transistor gate drain capacitance that is operated in the saturation region is very little, almost do not have, therefore output node place equivalent capacity is determined by a P type MOS transistor P1 and the 2nd P type MOS transistor P2 and is constant, therefore bandwidth does not change, keeps constant.The second current source I2 electric current only flows through the second N-type MOS transistor N2 and the 6th N-type MOS transistor N6, for it provides current offset, the first switch S 1, the 4th switch S 4 and minion are closed S7 closure simultaneously, make the breadth length ratio first N-type MOS transistor N1 relative to bias current of the second N-type MOS transistor N2 change respectively identical multiple, the mutual conductance of the second N-type MOS transistor N2 is the identical multiple of the first N-type MOS transistor N1 mutual conductance.Simultaneously, the breadth length ratio of the 6th N-type MOS transistor N6 five N-type MOS transistor N5 relative to bias current changes respectively identical multiple, and the mutual conductance of the 6th N-type MOS transistor N6 is the identical multiple of the 5th N-type MOS transistor N5 mutual conductance.Guaranteeing that the first N-type MOS transistor N1 is identical with the mutual conductance of the 5th N-type MOS transistor N5 and when constant, the size of multiple is depended in whole common-source amplifier equivalence input mutual conductance, because the output impedance size is constant, the size of multiple is depended in amplifier gain.
When control word A3A2A1 is 011, namely the first switch S 1, the 4th switch S 4, minion are closed outside S7, the tenth switch S 10 and the 13 switch S 13 closures, second switch S2, the 5th switch S 5, the 8th switch S8, the 11 switch S 11 and the 14 switch S 14 are also closed simultaneously, the transistor gate drain capacitance of introducing this moment is very little to the grid sources capacitive effect of an original P type MOS transistor P1 and the 2nd P type MOS transistor P2, and output capacitance remains unchanged; The electric current of the 3rd current source I3 guarantees that by the 6th current source I6 and the 9th current source I9 shunting a P type MOS transistor P1 and the 2nd P type MOS transistor P2 electric current are constant, and its corresponding equiva lent impedance is also constant.Because other transistor drain-source resistances of introducing are very large, mainly by a P type MOS transistor P1 and the 2nd P type MOS transistor P2 decision, therefore output impedance remains unchanged, bandwidth also remains unchanged in output loading.Under this control word, the electric current of the 6th current source I6 flows through the 3rd N-type MOS transistor N3 entirely, and the electric current of the 9th current source I9 flows through the 7th N-type MOS transistor N7 entirely.The 3rd current source I3 electric current only flows through the 3rd N-type MOS transistor N3 and the 7th N-type MOS transistor N7, for it provides current offset, second switch S2, the 5th switch S 5 and the 8th switch S8 are closed simultaneously, make the breadth length ratio first N-type MOS transistor N1 relative to bias current of the 3rd N-type MOS transistor N3 change respectively identical multiple, the mutual conductance of the 3rd N-type MOS transistor N3 is the identical multiple of the first N-type MOS transistor N1 mutual conductance.Simultaneously, the breadth length ratio of the 7th N-type MOS transistor N7 five N-type MOS transistor N5 relative to bias current changes respectively identical multiple, and the mutual conductance of the 7th N-type MOS transistor N7 is the identical multiple of the 5th N-type MOS transistor N5 mutual conductance.Guaranteeing that the first N-type MOS transistor N1 is identical with the mutual conductance of the 5th N-type MOS transistor N5 and when constant, total multiple and size are depended in whole common-source amplifier equivalence input mutual conductance.
When control word A3A2A1 was 111, namely all switches were closed simultaneously, this moment the one P type MOS transistor P1 and the 2nd P type MOS transistor P2 grid sources electric capacity in the highest flight, output capacitance remains unchanged basically; The electric current of the 4th current source I4 guarantees that by the 5th current source I5 and the tenth current source I10 shunting a P type MOS transistor P1 and the 2nd P type MOS transistor P2 electric current are constant, and its corresponding equiva lent impedance is also constant.Because other transistor drain-source resistances of introducing are very large, mainly by a P type MOS transistor P1 and the 2nd P type MOS transistor P2 decision, therefore output impedance remains unchanged, bandwidth also remains unchanged in output loading.Under this control word, the electric current of the 5th current source I5 flows through the 4th N-type MOS transistor N4 entirely, and the electric current of the tenth current source I10 flows through the 8th N-type MOS transistor N8 entirely.The 4th current source I4 electric current only flows through the 4th N-type MOS transistor N4 and the 8th N-type MOS transistor N8, for it provides current offset, the 3rd switch S 3, the 6th switch S 6 and the 9th switch S 9 are closed simultaneously, make the breadth length ratio first N-type MOS transistor N1 relative to bias current of the 4th N-type MOS transistor N4 change respectively identical multiple, the mutual conductance of the 4th N-type MOS transistor N4 is the identical multiple of the first N-type MOS transistor N1 mutual conductance.Simultaneously, the breadth length ratio of the 8th N-type MOS transistor N8 five N-type MOS transistor N5 relative to bias current changes respectively identical multiple, and the mutual conductance of the 8th N-type MOS transistor N8 is the identical multiple of the 5th N-type MOS transistor N5 mutual conductance.Guaranteeing that the first N-type MOS transistor N1 is identical with the mutual conductance of the 5th N-type MOS transistor N5 and when constant, total multiple and size are depended in whole common-source amplifier input mutual conductance.The variation of control word directly makes whole amplifier input pipe equivalent transconductance change at double.By fixing electric current multiple and input pipe size multiple are set, can be so that amplifier gain become accurate linear relationship with control word, gain step size is fixed.
Illustrate that below by simulation comparison the present invention has advantages of the constant and gain linearity of bandwidth.
Adopt
The Virtuoso simulation software carries out the amplitude-frequency characteristic emulation of variable gain amplifier.Use simultaneously traditional the passing through of this technology contrast to change the technology that mutual conductance reaches gain-variable.
The amplitude-frequency characteristic result as shown in Figure 2, abscissa represents the frequency of input signal, the Hz of unit, ordinate represent the gain, the dB of unit.As can be seen from Figure 2, bandwidth of the present invention is substantially constant near 170MHz.This technology and traditional pass through to change technology comparing result that mutual conductance reaches gain-variable as shown in Figure 3, the variable gain amplifier that the present invention proposes has accurate gain linearity relation, and gain step size is 6dB.
To sum up, in the present invention, as load, the break-make that makes switch changes very little to the equiva lent impedance of output node and capacitive reactance, thereby guarantees that bandwidth is constant with the transistor of diode connected mode.The present invention adopts and changes simultaneously input pipe size and bias current, make the overdrive voltage of input pipe constant, guarantee that the current source drain-source voltage that current mirror produces is constant, therefore further improved gain accuracy on common Digital Signals switch is realized the dB linear relationship basis of gain.
Claims (1)
1. gain linearity variable gain amplifier that bandwidth is constant, it is characterized in that: this variable gain amplifier comprises common-source stage amplifier and gain-adjusted network; Wherein:
The common-source stage amplifier comprises the first N-type MOS transistor (N1), the 5th N-type MOS transistor (N5), a P type MOS transistor (P1), the 2nd P type MOS transistor (P2) and the first current source (I1);
the gain-adjusted network comprises the second N-type MOS transistor (N2), the 3rd N-type MOS transistor (N3), the 4th N-type MOS transistor (N4), the 6th N-type MOS transistor (N6), the 7th N-type MOS transistor (N7), the 8th N-type MOS transistor (N8), the second current source (I2), the 3rd current source (I3), the 4th current source (I4), the 5th current source (I5), the 6th current source (I6), the 7th current source (I7), the 8th current source (I8), the 9th current source (I9), the tenth current source (I10), the first switch (S1), second switch (S2), the 3rd switch (S3), the 4th switch (S4), the 5th switch (S5), the 6th switch (S6), minion is closed (S7), the 8th switch (S8), the 9th switch (S9), the tenth switch (S10), the 11 switch (S11), twelvemo is closed (S12), the 13 switch (S13), the 14 switch (S14) and the 15 switch (S15),
input signal anode (VIN+) is connected with the grid of the first N-type MOS transistor (N1), the second N-type MOS transistor (N2), the 3rd N-type MOS transistor (N3) and the 4th N-type MOS transistor (N4), the drain electrode of the drain electrode of the first N-type MOS transistor (N1) and a P type MOS transistor (P1) connects, the drain electrode of the one P type MOS transistor (P1) is connected with grid, and the source electrode of a P type MOS transistor (P1) connects supply voltage, the source electrode of the source electrode of the first N-type MOS transistor (N1) and the second N-type MOS transistor (N2), the source electrode of the 3rd N-type MOS transistor (N3), the source electrode of the 4th N-type MOS transistor (N4), the source electrode of the 5th N-type MOS transistor (N5), the source electrode of the 6th N-type MOS transistor (N6), the source electrode of the source electrode of the 7th N-type MOS transistor (N7) and the 8th N-type MOS transistor (N8) connects, simultaneously with the first current source (I1), the first switch (S1), one end of second switch (S2) and the 3rd switch (S3) connects, the other end of the first switch (S1) is connected with an end of the second current source (I2), the other end of second switch (S2) is connected with an end of the 3rd current source (I3), and the other end of the 3rd switch (S3) is connected with an end of the 4th current source (I4), the other end ground connection of the first current source (I1), the second current source (I2), the 3rd current source (I3) and the 4th current source (I4), one end of the 4th switch (S4) is connected with the drain electrode of the second N-type MOS transistor (N2), one end of the 5th switch (S5) is connected with the drain electrode of the 3rd N-type MOS transistor (N3), and an end of the 6th switch (S6) is connected with the drain electrode of the 4th N-type MOS transistor (N4), the other end of the 4th switch (S4), the 5th switch (S5) and the 6th switch (S6) is connected with the drain electrode of the first N-type MOS transistor (N1), an end with the tenth switch (S10), the 11 switch (S11) and twelvemo pass (S12) is connected simultaneously, as the anode (VOUT+) of amplifier output signal, the other end of the tenth switch (S10) is connected with an end of the 7th current source (I7), the other end of the 11 switch (S11) is connected with an end of the 6th current source (I6), and the other end that twelvemo is closed (S12) is connected with an end of the 5th current source (I5), another termination supply voltage of the 5th current source (I5), the 6th current source (I6) and the 7th current source (I7), input signal negative terminal (VIN-) is connected with the grid of the 5th N-type MOS transistor (N5), the 6th N-type MOS transistor (N6), the 7th N-type MOS transistor (N7) and the 8th N-type MOS transistor (N8), the drain electrode of the drain electrode of the 5th N-type MOS transistor (N5) and the 2nd P type MOS transistor (P2) connects, the drain electrode of the 2nd P type MOS transistor (P2) is connected with grid, and the source electrode of the 2nd P type MOS transistor (P2) connects supply voltage, the end that minion is closed (S7) is connected with the drain electrode of the 6th N-type MOS transistor (N6), one end of the 8th switch (S8) is connected with the drain electrode of the 7th N-type MOS transistor (N7), and an end of the 9th switch (S9) is connected with the drain electrode of the 8th N-type MOS transistor (N8), the other end that minion is closed (S7), the 8th switch (S8) and the 9th switch (S9) is connected with the drain electrode of the 5th N-type MOS transistor (N5), be connected with an end of the 13 switch (S13), the 14 switch (S14) and the 15 switch (S15) simultaneously, as the negative terminal (VOUT-) of amplifier output signal, the other end of the 13 switch (S13) is connected with an end of the 8th current source (I8), the other end of the 14 switch (S14) is connected with an end of the 9th current source (I9), and the other end of the 15 switch (S15) is connected with an end of the tenth current source (I10), another termination supply voltage of the 8th current source (I8), the 9th current source (I9) and the tenth current source (I10).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106961255A (en) * | 2017-03-16 | 2017-07-18 | 天津大学 | The operational amplifier of programmable output Slew Rate |
| TWI672903B (en) * | 2018-10-03 | 2019-09-21 | 立積電子股份有限公司 | Amplifier circuit |
| CN110971205A (en) * | 2018-09-30 | 2020-04-07 | 华为技术有限公司 | High-linearity variable gain amplifier and electronic device |
| WO2022141198A1 (en) * | 2020-12-30 | 2022-07-07 | 华为技术有限公司 | Operational amplifier, drive circuit, interface chip, and electronic device |
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| US6331803B1 (en) * | 2000-05-08 | 2001-12-18 | Marvell International Ltd | Constant bandwidth, variable gain amplifier, and method |
| CN101951236A (en) * | 2010-09-20 | 2011-01-19 | 东南大学 | Digital variable gain amplifier |
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| US6331803B1 (en) * | 2000-05-08 | 2001-12-18 | Marvell International Ltd | Constant bandwidth, variable gain amplifier, and method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106961255A (en) * | 2017-03-16 | 2017-07-18 | 天津大学 | The operational amplifier of programmable output Slew Rate |
| CN110971205A (en) * | 2018-09-30 | 2020-04-07 | 华为技术有限公司 | High-linearity variable gain amplifier and electronic device |
| CN110971205B (en) * | 2018-09-30 | 2022-08-09 | 华为技术有限公司 | High-linearity variable gain amplifier and electronic device |
| US11431311B2 (en) | 2018-09-30 | 2022-08-30 | Huawei Technologies Co., Ltd. | High-linearity variable gain amplifier and electronic apparatus |
| TWI672903B (en) * | 2018-10-03 | 2019-09-21 | 立積電子股份有限公司 | Amplifier circuit |
| US11108366B2 (en) | 2018-10-03 | 2021-08-31 | Richwave Technology Corp. | Amplifier circuit |
| WO2022141198A1 (en) * | 2020-12-30 | 2022-07-07 | 华为技术有限公司 | Operational amplifier, drive circuit, interface chip, and electronic device |
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| Publication number | Publication date |
|---|---|
| CN103107791B (en) | 2015-03-04 |
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