CN103916098A - Programmable gain amplifier with high gain precision - Google Patents

Abstract

The invention discloses a programmable gain amplifier with high gain precision. The programmable gain amplifier is mainly used for meeting the requirement of a communication system for high gain precision and low power consumption of the programmable gain amplifier. The amplifier is formed through cascade connection of a gain fine adjusting stage and a gain rough adjusting stage, wherein the closed loop resistance negative feedback technology is adopted in the gain fine adjusting stage, and the open loop negative load variable common source stage amplifier technology is adopted in the gain rough adjusting stage. An input signal first controls a gain rough adjusting stage to determine an appropriate gain through a switch, and then the gain rough adjusting stage conducts precise gain adjustment on the basis, so that a gain with high precision is obtained. The gain rough adjusting stage selects different load resistances through the switch to conduct rough adjustment. Compared with a traditional fixed gain stage chip, the area is smaller, and power is lower. The cascade connection of the open loop structure and the closed-loop structure achieves compatibility of the open loop structure and the closed-loop structure. The programmable gain amplifier with high gain precision has the advantages of being high in gain precision, good in linearity, low in power consumption and the like.

Description

A kind of high-gain precision programmable gain amplifier

Technical field

The invention belongs to semiconductor integrated circuit design field, be specifically related to a kind of programmable gain amplifier of low power consumption high-precision.

Background technology

In wireless communication system, acknowledge(ment) signal often has larger dynamic range after propagation ducts, for example, just needs the change in gain of about 80dB in gsm wireless receiver.In order to obtain a relatively constant signal, need an AGC (automatic gain control) system to regulate the amplitude that receives signal.Wherein, programmable gain amplifier (Programmable Gain Amplifier, PGA) is as the nucleus module of AGC (automatic gain control) system, and its performance quality is most important to wireless communication system.Along with the high speed development of wireless communication system, the requirement of the power consumption of system to PGA and gain accuracy is more and more higher, and therefore, the PGA of low power consumption high-precision becomes study hotspot gradually.

Conventionally have two kinds of modes to realize the gain-adjusted of PGA, one is operate in open loop state mode, and its gain generally can be expressed as the product of the equivalence input mutual conductance of amplifier tube and the equivalent output impedance of load pipe, regulates gain by changing mutual conductance or output impedance.This mode is simple in structure, and power consumption is lower, but gain accuracy is poor; Another kind is closed loop working method, and its gain is generally determined by the ratio of feedback factor and input impedance, regulates gain by changing feedback factor.This mode stable performance, gain accuracy is high, but power consumption is bigger than normal.

Figure 1 shows that a kind of programmable gain amplifier based on the variable common-source stage amplifier of open loop load pull arrangement.This programmable gain amplifier select metal-oxide-semiconductor be basic switch resistance array as its variable load, have advantages of that area occupied is little, pressure drop is little, but metal-oxide-semiconductor resistance is subject to technogenic influence larger.The gain of amplifier equals to input the ratio of mutual conductance and load mutual conductance, in the time that input mutual conductance remains unchanged, changes load mutual conductance and can realize gain-adjusted.The change of load mutual conductance is opened corresponding load metal-oxide-semiconductor by single-pole double-throw switch (SPDT) and is realized, in the time selecting corresponding metal-oxide-semiconductor work, adjustment by switch is connected the grid of this metal-oxide-semiconductor with drain electrode, the grid of other load metal-oxide-semiconductors is connected with power supply and makes its shutoff simultaneously.

The programmable gain amplifier of this structure is realized gain-adjusted by changing load mutual conductance, and simple in structure, power consumption is lower, but is difficult to accurate ride gain, and the dynamic range of output signal is limited too.

Summary of the invention

Goal of the invention: the object of the invention is to propose a kind of programmable gain amplifier of low power consumption high-precision, to meet the requirement of the low-power consumption high-gain precision of communication system to programmable gain amplifier.

Technical scheme: in order to realize foregoing invention object, the programmable gain amplifier of the low power consumption high-precision that the present invention adopts carries out cascade by the gain fine tuning level of a closed loop resistance negative feedback structure and the gain coarse adjustment level of a variable common-source stage amplifier architecture of open loop load pull arrangement and forms; This amplifier circuit has positive and negative two-way input, output, this two-way circuit full symmetric design, and wherein negative input, output signal processing circuit are:

In the gain fine tuning level of described closed loop resistance negative feedback structure, the two ends of the 11 switch are connected on respectively between signal negative input end and the first resistance, the reverse input end of another termination the first operational amplifier of the first resistance, the positive output termination twelvemo of the first operational amplifier is closed, and the other end that twelvemo is closed is output at the corresponding levels; Wherein, the negative feedback switched resistor network that is connected in parallel 6 groups and is composed in series by switch and resistance between the input of the first operational amplifier and output, first group is composed in series by the 21 switch, the second resistance, the two or two switch; Second group is composed in series by the 31 switch, the 3rd resistance, the three or two switch; The 3rd group is composed in series by the 41 switch, the 4th resistance, the four or two switch; The 4th group by May Day switch, the 5th resistance, the five or two switch be composed in series; The 5th group is composed in series by the 61 switch, the 6th resistance, the six or two switch; The 6th group by the July 1st switch, the 7th resistance, the seven or two switch be composed in series; One end of reverse the first switch is connected between the 11 switch and signal negative input end, and the other end is connected on twelvemo and closes between the 81 switch;

In the gain coarse adjustment level of the variable common-source stage amplifier architecture of described open loop load pull arrangement, the two ends of the 81 switch are connected on respectively between twelvemo pass and the reverse input end of the second operational amplifier, the second operational amplifier positive output termination the eight or two switch, the other end of the eight or two switch is the signal negative output terminal of amplifier at the corresponding levels; One end of reverse second switch is connected on twelvemo and closes between the 81 switch, and the other end is connected between the eight or two switch and signal negative output terminal.

In the gain coarse adjustment level of the variable common-source stage amplifier architecture of described open loop load pull arrangement, the grid of positive input termination the one NMOS pipe of the second operational amplifier, the grid of negative input termination the 2nd NMOS pipe; The source electrode of the one NMOS pipe connects the drain electrode of the 3rd NMOS pipe, and drain electrode connects the negative output terminal of the second operational amplifier; The source electrode of the 2nd NMOS pipe connects the drain electrode of the 4th NMOS pipe, and drain electrode connects the positive output end of the second operational amplifier; The grid of the 3rd NMOS pipe is connected with the grid of the 4th NMOS pipe, the source electrode ground connection that is connected with the source electrode of the 4th NMOS pipe; The grid of the one PMOS pipe is connected with the grid of the 2nd PMOS pipe, the source electrode power supply that is connected with the source electrode of the 2nd PMOS pipe, and drain electrode is connected with the drain electrode of a NMOS pipe; The drain electrode of the 2nd PMOS pipe is connected with the drain electrode of the 2nd NMOS pipe; The source electrode of one termination the one NMOS pipe of the 8th resistance, the source electrode of another termination the 2nd NMOS pipe; Between the grid of a PMOS pipe and drain electrode, be connected in series the 91 switch and the 11 resistance; Between the two ends of the 91 switch, be connected in series the one zero one switch and the 21 resistance; Between the two ends of the one zero one switch, be connected in series the 201 switch and the 31 resistance; Between the two ends of the 201 switch, be connected in series the 301 switch and the 41 resistance; Between the two ends of the 301 switch, be connected in series the 401 switch and May Day resistance; Between the grid of the 2nd PMOS pipe and drain electrode, be connected in series the 92 switch and the 12 resistance; Between the two ends of the 92 switch, be connected in series the one zero two switch and the two or two resistance; Between the two ends of the one zero two switch, be connected in series the 202 switch and the three or two resistance; Between the two ends of the 202 switch, be connected in series the 302 switch and the four or two resistance; Between the two ends of the 302 switch, be connected in series the 402 switch and the five or two resistance.

The 11 described switch to the 402 switches all adopt cmos transmission gate circuit, low level conducting; Described reverse the first switch and oppositely second switch all adopt cmos transmission gate circuit, high level conducting.

In the gain fine tuning level of described closed loop resistance negative feedback structure, the first operational amplifier adopts two-stage Full differential operational amplifier to add common-mode feedback structure.

Beneficial effect: PGA of the present invention realizes by the mode that adopts the gain fine tuning level of closed loop resistance negative feedback structure and the gain coarse adjustment level phase cascade of the variable common-source stage amplifier architecture of open loop load pull arrangement, realize the compatibility of closed loop and open loop advantage, gain coarse adjustment level is compared traditional fixed gain level and has been saved chip area, has reduced power consumption.This PGA has the advantages such as gain accuracy is high, low in energy consumption, the linearity is good.

Accompanying drawing explanation

Fig. 1 is a kind of based on the variable open loop programmable gain amplifier structure of load;

Fig. 2 is the programmable gain amplifier structure of a kind of low power consumption high-precision provided by the invention;

Fig. 3 is the structure chart of OP2 in Fig. 2;

Fig. 4 is the gain characteristic curve of programmable gain amplifier of the present invention;

Fig. 5 is the gain error curve of programmable gain amplifier of the present invention under different gains.

Embodiment

For the technological means that further illustrates advantage of the present invention place and specifically take, below constipation close diagram and describe the specific embodiment of the present invention and circuit structure in detail.

With reference to Fig. 2, the programmable gain amplifier of a kind of low power consumption high-precision provided by the present invention carries out cascade by the gain fine tuning level of a closed loop resistance negative feedback structure and the gain coarse adjustment level of a variable common-source stage amplifier architecture of open loop load pull arrangement and forms.This amplifier circuit has positive and negative two-way input, output, this two-way circuit full symmetric design, and wherein negative input, output signal processing circuit are:

In the gain fine tuning level of closed loop resistance negative feedback structure, the 11 switch S 11 is connected on respectively between signal negative input end Vin and the first resistance R 1, the reverse input end of another termination first operational amplifier OP1 of the first resistance R 1, the positive output termination twelvemo of the first operational amplifier OP1 is closed S12, and the other end that twelvemo is closed S12 is output at the corresponding levels.

Wherein, the feedback switch resistor network that is connected in parallel 6 groups and is composed in series by switch and resistance between the input of the first operational amplifier OP1 and output, first group is composed in series by the 21 switch S 21, the second resistance R the 2, the 22 switch S 22; Second group is composed in series by the 31 switch S 31, the 3rd resistance R the 3, the 32 switch S 32; The 3rd group is composed in series by the 41 switch S 41, the 4th resistance R the 4, the 42 switch S 42; The 4th group by May Day switch S 51, the 5th resistance R the 5, the 52 switch S 52 be composed in series; The 5th group is composed in series by the 61 switch S 61, the 6th resistance R the 6, the 62 switch S 62; The 6th group by the July 1st switch S 71, the 7th resistance R the 7, the 72 switch S 72 be composed in series; Reverse the first switch an end be connected between the 11 switch S 11 and signal negative input end Vin, the other end is connected on twelvemo and closes between S12 and the 81 switch S 81.

The first resistance R 1, the first operational amplifier OP1 and feedback switch resistor network form resistive degeneration formula gain fine tuning level, and the 11 switch S 11, twelvemo are closed S12 and reverse the first switch the break-make of ride gain fine tuning level; In the time that the 11 switch S 11, twelvemo are closed S12 conducting, the gain expressions of gain fine tuning level is as follows:

$A_v=-\frac{R_f}{R_1}$

Here A _vthe voltage amplification factor of gain fine tuning level, R _fthe resistance of feedback switch resistor network, R ₁it is the resistance of the first resistance R 1.From above formula, work as R ₁while remaining unchanged, just can change gain as long as change the resistance of feedback switch resistor network, and the resistance of feedback switch resistor network can by the 21 switch S the 21, the 22 switch S the 22, the 31 switch S the 31, the 32 switch S the 32, the 41 switch S the 41, the 42 switch S 42, May Day switch S the 51, the 52 switch S the 52, the 61 switch S the 61, the 62 switch S 62, the July 1st switch S the 71, the 72 switch S 72 its corresponding resistance of control break-make change.

In the gain coarse adjustment level of the variable common-source stage amplifier architecture of open loop load pull arrangement, the 81 switch S 81 is connected on respectively twelvemo and closes between S12 and the reverse input end of the second operational amplifier OP2, the second operational amplifier OP2 positive output termination the eight or two switch S 82, the other end of the eight or two switch S 82 is outputs of this amplifier, meets signal negative output terminal Von; Reverse the 8th switch an end be connected on twelvemo and close between S12 and the 81 switch S 81, the other end is connected between the eight or two switch S 82 and signal negative output terminal Von; The 81 switch S the 81, the 82 switch S 82 and reverse the 8th switch control the break-make of the second operational amplifier OP2.

Wherein as shown in Figure 3, the positive input terminal Vi+ of the second operational amplifier OP2 connects the grid of a NMOS pipe NM1, and negative input end Vi-connects the grid of the 2nd NMOS pipe NM2; The source electrode of the one NMOS pipe NM1 connects the drain electrode of the 3rd NMOS pipe NM3, and drain electrode meets the negative output terminal Vo-of the second operational amplifier OP2; The source electrode of the 2nd NMOS pipe NM2 connects the drain electrode of the 4th NMOS pipe NM4, and drain electrode meets the positive output end Vo+ of the second operational amplifier OP2; The grid of the 3rd NMOS pipe NM3 is connected with the grid of the 4th NMOS pipe NM4, the source electrode that source electrode and the 4th NMOS the manage NM4 ground connection that is connected; The grid of the one PMOS pipe PM1 is connected with the grid of the 2nd PMOS pipe PM2, the source electrode power supply that is connected with the source electrode of the 2nd PMOS pipe PM2, and the drain electrode of managing NM1 with a NMOS that drains is connected; The drain electrode of the 2nd PMOS pipe PM2 is connected with the drain electrode of the 2nd NMOS pipe NM2; The source electrode of one termination the one NMOS pipe NM1 of the 8th resistance R 8, the source electrode of another termination the 2nd NMOS pipe NM2; Between managing the grid of PM1 and drain, a PMOS is connected in series the 91 switch S the 91 and the 11 resistance R 11; Between the two ends of the 91 switch S 91, be connected in series the one zero one switch S the 101 and the 21 resistance R 21; Between the two ends of the one zero one switch S 101, be connected in series the 201 switch S the 201 and the 31 resistance R 31; Between the two ends of the 201 switch S 201, be connected in series the 301 switch S the 301 and the 41 resistance R 41; Between the two ends of the 301 switch S 301, be connected in series the 401 switch S 401 and May Day resistance R 51; Between managing the grid of PM2 and drain, the 2nd PMOS is connected in series the 92 switch S the 92 and the 12 resistance R 12; Between the two ends of the 92 switch S 92, be connected in series the one zero two switch S the 102 and the 22 resistance R 22; Between the two ends of the one zero two switch S 102, be connected in series the 202 switch S the 202 and the 32 resistance R 32; Between the two ends of the 202 switch S 202, be connected in series the 302 switch S the 302 and the 42 resistance R 42; Between the two ends of the 302 switch S 302, be connected in series the 402 switch S the 402 and the 52 resistance R 52.Its gain expressions is as follows:

$A\≈\frac{r_{o5}\left|\right|R_{\mathrm{of}}}{1/g_{m1}+R_8/2}$

Wherein, A is the gain of the second operational amplifier OP2, g _m1the mutual conductance of NM1 pipe, r _o5the output resistance of PM1 pipe, R ₈it is source negative feedback resistance R ₈resistance, R _ofrepresent to manage with PM1 the resistance of resistance in parallel, by its size of switch control.Can be drawn by above formula, when source negative feedback resistance R ₈much larger than the mutual conductance g of M1 pipe _m1time, the gain of amplifier becomes g _m1minorant, be approximately the ratio of equivalent load resistance and source negative feedback resistance, therefore the linearity of this structure is better.

Figure 4 shows that the gain characteristic curve of the programmable gain amplifier of low power consumption high-precision in Fig. 2.Can find out, the gain-adjusted scope of can realize-12～24dB of programmable gain amplifier of the present invention, gain step size is 1dB.

The gain error curve of the programmable gain amplifier that Figure 5 shows that low power consumption high-precision in Fig. 2 under different gains.Can find out, the gain error of the programmable gain amplifier shown in Fig. 2 under different gains is less than 0.02dB, and gain accuracy is very high.

In sum, the programmable gain amplifier of the low power consumption high-precision that the present invention proposes has advantages of that gain accuracy is high, low in energy consumption, the linearity is good, in wireless communication system, has broad application prospects.

Below be only example of the present invention, do not form any limitation of the invention, obviously, under thought of the present invention, any those skilled in the art, are not departing within the scope of technical solution of the present invention, can utilize the technology contents of above-mentioned announcement that circuit structure and components and parts size are suitably adjusted or optimized, refer to according to technology of the present invention any simple modification, equivalents and modification that above embodiment is done, all belong to the scope of technical solution of the present invention.

Claims (4)

1. a programmable gain amplifier for low power consumption high-precision, is characterized in that this amplifier is formed by the gain fine tuning level of a closed loop resistance negative feedback structure and the gain coarse adjustment level cascade of a variable common-source stage amplifier architecture of open loop load pull arrangement; This amplifier circuit has positive and negative two-way input, output, this two-way circuit full symmetric design; Wherein negative input, output signal processing circuit are:

In the gain fine tuning level of described closed loop resistance negative feedback structure, the two ends of the 11 switch (S11) are connected on respectively between signal negative input end (Vin) and the first resistance (R1), the reverse input end of another termination the first operational amplifier (OP1) of the first resistance (R1), the positive output termination twelvemo of the first operational amplifier (OP1) is closed (S12), and the other end that twelvemo is closed (S12) is output at the corresponding levels; Wherein, the negative feedback switched resistor network that is connected in parallel 6 groups and is composed in series by switch and resistance between the input of the first operational amplifier (OP1) and output, first group is composed in series by the 21 switch (S21), the second resistance (R2), the two or two switch (S22); Second group is composed in series by the 31 switch (S31), the 3rd resistance (R3), the three or two switch (S32); The 3rd group is composed in series by the 41 switch (S41), the 4th resistance (R4), the four or two switch (S42); The 4th group is composed in series by switch on May Day (S51), the 5th resistance (R5), the five or two switch (S52); The 5th group is composed in series by the 61 switch (S61), the 6th resistance (R6), the six or two switch (S62); The 6th group is composed in series by the switch July 1st (S71), the 7th resistance (R7), the seven or two switch (S72); Reverse the first switch an end be connected between the 11 switch (S11) and signal negative input end (Vin), the other end is connected on twelvemo and closes between (S12) and the 81 switch (S81);

In the gain coarse adjustment level of the variable common-source stage amplifier architecture of described open loop load pull arrangement, the two ends of the 81 switch (S81) are connected on respectively twelvemo and close between (S12) and the reverse input end of the second operational amplifier (OP2), the second operational amplifier (OP2) positive output termination the eight or two switch (S82), the other end of the eight or two switch (S82) is the signal negative output terminal (Von) of amplifier at the corresponding levels; Oppositely second switch an end be connected on twelvemo and close between (S12) and the 81 switch (S81), the other end is connected between the eight or two switch (S82) and signal negative output terminal (Von).

2. according to the programmable gain amplifier of a kind of low power consumption high-precision claimed in claim 1, it is characterized in that in the gain coarse adjustment level of the described variable common-source stage amplifier architecture of open loop load pull arrangement, the positive input terminal (Vi+) of the second operational amplifier (OP2) connects the grid of a NMOS pipe (NM1), and negative input end (Vi-) connects the grid of the 2nd NMOS pipe (NM2); The source electrode of the one NMOS pipe (NM1) connects the drain electrode of the 3rd NMOS pipe (NM3), and drain electrode connects the negative output terminal (Vo-) of the second operational amplifier (OP2); The source electrode of the 2nd NMOS pipe (NM2) connects the drain electrode of the 4th NMOS pipe (NM4), and drain electrode connects the positive output end (Vo+) of the second operational amplifier (OP2); The grid of the 3rd NMOS pipe (NM3) is connected with the grid that the 4th NMOS manages (NM4), the source electrode that source electrode and the 4th NMOS manage (NM4) ground connection that is connected; The grid of the one PMOS pipe (PM1) is connected with the grid that the 2nd PMOS manage (PM2), the source electrode that source electrode and the 2nd PMOS manage (PM2) power supply that is connected, and the drain electrode of managing (NM1) with a NMOS that drains is connected; The drain electrode of the 2nd PMOS pipe (PM2) is connected with the drain electrode that the 2nd NMOS manages (NM2); The source electrode of one termination the one NMOS pipe (NM1) of the 8th resistance (R8), the source electrode of another termination the 2nd NMOS pipe (NM2); Between managing the grid of (PM1) and drain, a PMOS is connected in series the 91 switch (S91) and the 11 resistance (R11); Between the two ends of the 91 switch (S91), be connected in series the one zero one switch (S101) and the 21 resistance (R21); Between the two ends of the one zero one switch (S101), be connected in series the 201 switch (S201) and the 31 resistance (R31); Between the two ends of the 201 switch (S201), be connected in series the 301 switch (S301) and the 41 resistance (R41); Between the two ends of the 301 switch (S301), be connected in series the 401 switch (S401) and resistance on May Day (R51); Between managing the grid of (PM2) and drain, the 2nd PMOS is connected in series the 92 switch (S92) and the 12 resistance (R12); Between the two ends of the 92 switch (S92), be connected in series the one zero two switch (S102) and the two or two resistance (R22); Between the two ends of the one zero two switch (S102), be connected in series the 202 switch (S202) and the three or two resistance (R32); Between the two ends of the 202 switch (S202), be connected in series the 302 switch (S302) and the four or two resistance (R42); Between the two ends of the 302 switch (S302), be connected in series the 402 switch (S402) and the five or two resistance (R52).

3. according to the programmable gain amplifier of a kind of low power consumption high-precision claimed in claim 1, it is characterized in that the 11 described switch (S11) all adopts cmos transmission gate circuit to the 402 switch (S402), low level conducting; Described reverse the first switch with reverse second switch all adopt cmos transmission gate circuit, high level conducting.

4. according to the programmable gain amplifier of a kind of low power consumption high-precision claimed in claim 1, it is characterized in that in the gain fine tuning level of described closed loop resistance negative feedback structure, the first operational amplifier (OP1) adopts two-stage Full differential operational amplifier to add common-mode feedback structure.