CN102945059A - Low dropout linear regulator and pole adjustment method thereof - Google Patents
Low dropout linear regulator and pole adjustment method thereof Download PDFInfo
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Abstract
Disclosed are a low dropout linear regulator and a pole adjustment method thereof. A source electrode of a p-channel metal oxide semiconductor (PMOS) adjustment transistor of the low dropout linear regulator is connected with a first voltage end, a drain electrode of the PMOS adjustment transistor is connected with a first end of a first resistor, a grid electrode of the PMOS adjustment transistor is connected with an output end of an error amplifier, a first electric current supply unit is suitable for generating reference current, a second electric current supply unit is suitable for generating regulating current, the regulating current is relevant to the electric current of an output end of the low dropout linear regulator, a first input end of the error amplifier inputs reference voltage, a second input end of the error amplifier is connected with a second end of the first resistor and a first end of a second resistor, a bias current input end inputs bias current generated by superposition of the reference current and the regulating current, the first end of the first resistor serves as the output end of the low dropout linear regulator, a second end of the second resistor is connected with a second voltage end, and the voltage value of the first voltage end is larger than that of the second voltage end.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of low pressure difference linear voltage regulator and limit method of adjustment thereof.
Background technology
The linear mu balanced circuit of low voltage difference (Low Dropout Regulator, LDO) is the step-down type dc linear voltage regulator, and along with the development of SOC technology, it is ubiquitous in sector applications such as computing machine, communication, instrument and meter, consumer electronics, monitoring camera-shootings.Although compare with the DC-DC switching voltage converter, the efficient of LDO is low, but it has the advantages such as peripheral cell is few, ripple is little, noise is low, chip area is little, circuit structure is simple, so LDO occupies very large proportion in power management class chip always.
Raising along with integrated level, increasing LDO is as SOC(System on Chip, SOC (system on a chip)) submodule of chip is given certain crucial module for power supply and is integrated in this SOC chip, and integrated a plurality of LDO modules give different module for power supply very general in the powerful SOC chip.Frequency of operation along with the SOC system improves constantly simultaneously, and it is also more and more serious that digital circuit wherein brings power supply to disturb, and this just needs LDO that the performance requirements such as High-speed transient response speed, high output voltage control accuracy, high PSRR, low noise are arranged.
As shown in Figure 1, existing LDO comprises that error amplifier OP, current source IL1, PMOS adjust the degeneration factor that transistor MP and dividing potential drop feedback network etc. consist of.Described dividing potential drop feedback network comprises the first resistance R 1, the second resistance R 2.Described the first resistance R 1 and the second resistance R 2 form partial pressure unit, and branch pressure voltage is fed back to the normal phase input end of error amplifier OP.The negative-phase input of described error amplifier OP receives reference voltage vref.Described current source IL1 provides the bias current of error amplifier OP.
LDO shown in Figure 1 generally has two limits: one is the P1 limit of adjusting transistor MP gate terminal at PMOS, and another is the P2 limit at LDO output terminal OUT.Be the frequency stability of assurance LDO and enough phase margins, the spacing of P1 limit and P2 limit should be enough large.The demander of LDO wishes that all the power consumption of LDO under ideal case is enough low at present, the circuit power consumption of electric resistance partial pressure sampling is very little, this is so that the frequency of P2 limit is very little, the P1 limit can't be accomplished the little phase stability that much satisfies loop of frequency than P2 limit, and the electric capacity of the P2 electric capacity of ordering much larger than P1.So in the situation that low-power consumption during the LDO standby, dominant pole can only be P2 limit (two limit medium frequency low be dominant pole).When the LDO output end current increased, the frequency of P1 limit remained unchanged substantially, and the frequency of P2 limit becomes greatly gradually, and the difference on the frequency between P1 limit and the P2 limit dwindles, and causes the frequency stability variation.
Miller-compensated mode becomes under the demand of LDO standby low-power consumption and is difficult to effectively, and the mode of the external large electric capacity of output terminal can obtain preferably effect.At the external large electric capacity of LDO output terminal OUT, reduced the increase amplitude of P1 limit when the LDO output end current increases, guarantee that the difference on the frequency of P1 limit and P2 limit is enough large, guarantee the stability of LDO.
But the development trend of LDO more and more tends to cancel the pin of LDO output terminal, if without the pin of LDO output terminal, then the large electric capacity in the said method can't be connected outside sheet with the LDO output terminal, LDO frequency stability problem then can still exist.
Summary of the invention
The problem that the present invention solves is the frequency stability problem that how to solve low pressure difference linear voltage regulator.
For addressing the above problem, the invention provides a kind of low-dropout linear voltage-regulating circuit, comprising: error amplifier, the first electric current provide unit, the second electric current to provide unit, PMOS to adjust transistor, the first resistance and the second resistance;
Described PMOS adjusts transistorized source electrode and connects the first voltage end, and drain electrode connects the first end of described the first resistance, and grid connects the output terminal of described error amplifier;
Described the first electric current provides the unit to be suitable for producing reference current;
Described the second electric current provides the unit to be suitable for producing and regulates electric current, and described adjusting electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
The first input end input reference voltage of described error amplifier, the second input end connect the second end of described the first resistance and the first end of the second resistance, and the bias current input end is inputted described reference current and regulated the bias current that the electric current stack produces;
The first end of described the first resistance is the output terminal of described low pressure difference linear voltage regulator;
The second end of described the second resistance connects the second voltage end;
The magnitude of voltage of described the first voltage end is greater than the magnitude of voltage of second voltage end.
The present invention also provides a kind of limit method of adjustment of low pressure difference linear voltage regulator, comprising:
Reference current is provided and regulates electric current, described adjusting electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
Superpose described reference current and regulate electric current is to obtain bias current;
The bias current input end of the error amplifier of described bias current to the described low pressure difference linear voltage regulator is provided.
Compared with prior art, technical solution of the present invention has the following advantages at least:
When load becomes large, it is large that the output end current of low pressure difference linear voltage regulator becomes, and it is large that the P2 pole frequency of low pressure difference linear voltage regulator output terminal becomes, and also the phase strain is large to regulate electric current, so that the output impedance of error amplifier diminishes, the P1 pole frequency that PMOS adjusts transistor gate becomes large like this.Because the frequency of P1 limit and P2 limit all increases to some extent, so both frequency-splittings can remain on enough large distance substantially, has guaranteed the stability of low pressure difference linear voltage regulator.
Regulate electric current also very little when load current is very little, the power consumption of low pressure difference linear voltage regulator integral body is very low.
Description of drawings
Fig. 1 is the circuit diagram of prior art mesolow difference linear voltage-stabilizing circuit;
Fig. 2 is the low pressure difference linear voltage regulator schematic diagram of the embodiment of the invention one;
Fig. 3 is a kind of specific embodiment schematic diagram of the low-dropout linear voltage-regulating circuit of the embodiment of the invention one;
Fig. 4 is the low pressure difference linear voltage regulator schematic diagram of the embodiment of the invention two of the present invention;
Fig. 5 is a kind of specific embodiment schematic diagram of the low-dropout linear voltage-regulating circuit of the embodiment of the invention two.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to following explanation, advantages and features of the invention will be clearer.
As shown in Figure 2, the embodiment of the invention one provides a kind of low pressure difference linear voltage regulator, comprising: error amplifier OP, the first electric current provide unit 11, the second electric current to provide unit 12, PMOS to adjust transistor MP1, the first resistance R 1 and the second resistance R 2.
The source electrode that described PMOS adjusts transistor MP1 connects the first voltage end VDD, and drain electrode connects the first end of described the first resistance R 1, and grid connects the output terminal OUT1 of described error amplifier OP;
Described the first electric current provides unit 11 to be suitable for producing reference current;
Described the second electric current provides unit 12 to be suitable for producing and regulates electric current, and described adjusting electric current is associated with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator;
The first input end IN1 input reference voltage of described error amplifier OP1, the second input end IN2 connects the second end of described the first resistance R 1 and the first end of the second resistance R 2, and bias current input end BIAS inputs described reference current and regulates the bias current that the electric current stack produces;
The first end of described the first resistance R 1 is the output terminal OUT2 of described low pressure difference linear voltage regulator;
The second end of described the second resistance R 2 connects second voltage end GND;
The magnitude of voltage of described the first voltage end VDD is greater than the magnitude of voltage of second voltage end GND.
Described the first voltage end VDD can provide supply voltage, and described second voltage end GND can be for providing ground voltage.
Described the second electric current provides adjusting electric current that unit 12 provides to increase with the electric current of the output terminal of described low pressure linear voltage regulator.
In embodiment one, the second electric current provides unit 12 to be connected with the bias current input end BIAS of described error amplifier OP1 and the output terminal OUT1 of error amplifier OP1 respectively, be suitable for gathering by the voltage on the described error amplifier OP1 output terminal OUT1 electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator, thus the adjusting electric current that generation is associated with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator.Described adjusting electric current can increase with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator.
Fig. 3 is a kind of specific embodiment of the embodiment of the invention one.As shown in Figure 3, described the second electric current provides unit 12 to comprise: the 2nd PMOS transistor MP2 and the first current lens unit IL1.The source electrode of described the 2nd PMOS transistor MP2 connects described the first voltage end VDD, and drain electrode connects the input end of described the second current lens unit, and grid connects the grid that described PMOS adjusts transistor MP1; The first output terminal of described the second current lens unit IL1 connects the bias current input end BIAS of described error amplifier OP, and the second output terminal connects described second voltage end GND.
The electric current that flows through on the first resistance R 1 and the second resistance R 2 is very little, so the electric current of the output terminal OUT2 of the drain current of the first transistor MP1 and low pressure difference linear voltage regulator about equally.Transistor all is in the saturation region when considering the low pressure difference linear voltage regulator normal operation, the poor transistor drain electric current equal and that underlayer voltage is the same of gate source voltage equates (ignoring channel-length modulation), so the drain current of the drain current of the 2nd PMOS transistor MP2 and PMOS adjustment transistor MP1 about equally.Therefore, in the situation that low-power consumption, the output terminal OUT2 approximately equal of the drain current of the 2nd PMOS transistor MP2 and low pressure difference linear voltage regulator.
Described the first current lens unit IL1 can comprise: the first nmos pass transistor MN1 and the second nmos pass transistor MN2.The drain electrode of described the first nmos pass transistor MN1 connects the grid of the grid of the first nmos pass transistor MN1 and the second nmos pass transistor MN2 and as the input end of described the first current lens unit IL1, source electrode connects described second voltage end GND; The drain electrode of described the second nmos pass transistor is as the first output terminal of described the first current lens unit IL1, and source electrode is as the second output terminal of described the first current lens unit IL1.
Described the first electric current provides the unit to comprise the 5th nmos pass transistor MN5, and the drain electrode of described the 5th nmos pass transistor MN5 connects the bias current input end BIAS of described error amplifier OP, and source electrode connects described second voltage end GND, grid input offset voltage.
Described error amplifier OP can comprise: the 5th PMOS transistor, the 6th PMOS transistor, the 6th nmos pass transistor and the 7th nmos pass transistor.The transistorized source electrode of described the 5th PMOS connects described the first voltage end VDD, and drain electrode connects the drain electrode of the transistorized grid of described the 5th PMOS, the transistorized grid of the 6th PMOS and the 6th nmos pass transistor.The transistorized source electrode of described the 6th PMOS connects described the first voltage end VDD, and drain electrode connects the drain electrode of described the 7th nmos pass transistor and as the output terminal OUT1 of described error amplifier OP.The source electrode of described the 6th nmos pass transistor connects the source electrode of described the 7th nmos pass transistor and as the bias current input end BIAS of described error amplifier OP, grid is as the second input end IN2 of described error amplifier OP.The grid of described the 7th nmos pass transistor is as the first input end IN1 of described error amplifier OP.
In the present embodiment one, the drain current of the drain current of the 2nd PMOS transistor MP2 and PMOS adjustment transistor MP1 has realized that the second electric current provides unit 12 to gather the electric current of the output terminal OUT2 of low pressure difference linear voltage regulator by the voltage on the error amplifier OP1 output terminal OUT1 about equally.
The electric current that the 2nd PMOS transistor MP2 source electrode collects can be mirrored to by the first current lens unit the bias current input end BIAS of error amplifier OP.
The electric current that the second electric current that the embodiment of the invention one provides provides unit 12 to gather the output terminal OUT2 of described low pressure difference linear voltage regulator by the voltage on the error amplifier OP1 output terminal OUT1, thereby the adjusting electric current that generation is associated with the electric current of the output terminal OUT2 of low pressure difference linear voltage regulator.
When load became large, it is large that the output terminal OUT2 electric current of low pressure difference linear voltage regulator becomes, and it is large that P2 limit (the output terminal OUT2 of low pressure difference linear voltage regulator) frequency becomes.The output terminal OUT2 electric current change of low pressure difference linear voltage regulator causes greatly the second electric current to provide the adjusting electric current of unit 12 also to become greatly, so that the output impedance of error amplifier OP diminishes, P1 limit (PMOS adjusts the grid of transistor MP1) frequency becomes large like this.Because the frequency of P1 limit and P2 limit all increases to some extent, so just can guarantee that limit moves to identical direction, the sampling feedback coefficient just can not reduce more than or equal to the relative position of 1 o'clock P1 limit and P2 limit, both frequency-splittings can remain on enough large distance substantially like this, have guaranteed the stability of low pressure difference linear voltage regulator.
As shown in Figure 4, the low pressure difference linear voltage regulator that embodiment two provides is with the difference of embodiment one: the second electric current provides unit 12 to be connected with the bias current input end BIAS of described error amplifier OP1 and the output terminal OUT2 of low pressure difference linear voltage regulator respectively, be suitable for directly gathering the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator, thus the adjusting electric current that generation is associated with the electric current of the output terminal OUT2 of described low pressure difference linear voltage regulator.
Fig. 5 is a kind of specific embodiment of the embodiment of the invention two.As shown in Figure 5, described the second electric current provides unit 12 to comprise: the second current lens unit IL2 and the 3rd current lens unit IL3.The drain electrode of described PMOS adjustment transistor MP1 connects the first end of described the first resistance R 1 by described the second current lens unit IL2; The input end of described the second current lens unit IL2 connects the drain electrode that described PMOS adjusts transistor MP1, and the first output terminal connects the first end of described the first resistance R 1, and the second output terminal connects the input end of described the 3rd current lens unit IL3; The first output terminal of described the 3rd current lens unit IL3 connects the bias current input end of described error amplifier, and the second output terminal connects described second voltage end GND.
Described the second current lens unit IL2 can comprise: the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4.The source electrode of described the 3rd PMOS transistor MP3 connects the source electrode of described the 4th PMOS transistor MP4 and as the input end of described the second current lens unit, and grid connects the grid of the drain electrode of described the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4 and as the first output terminal of described the second current lens unit IL2; The drain electrode of described the 4th PMOS transistor MP4 is as the second output terminal of described the second current lens unit IL2.
Described the 3rd current lens unit IL3 can comprise: the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4.The drain electrode of described the 3rd nmos pass transistor MN3 connects the grid of the grid of the 3rd nmos pass transistor MN3 and the 4th nmos pass transistor MN4 and as the input end of described the 3rd current lens unit IL3, source electrode connects described second voltage end GND; The drain electrode of described the 4th nmos pass transistor MN4 is as the first output terminal of described the 3rd current lens unit IL3, and source electrode is as the second output terminal of described the 3rd current lens unit IL3.
In the present embodiment two, the drain current that the second current lens unit can be adjusted PMOS transistor MP1 is mirrored to the input end of the 3rd current lens unit, thereby realizes the collection of electric current of the output terminal OUT2 of low pressure difference linear voltage regulator.
The electric current that the second electric current that the embodiment of the invention two provides provides unit 12 directly to gather the output terminal OUT2 of described low pressure difference linear voltage regulator, thereby the adjusting electric current that generation is associated with the electric current of the output terminal OUT2 of low pressure difference linear voltage regulator.When load becomes large, it is large that the frequency of P2 limit becomes, the adjusting electric current that the second electric current provides unit 12 to produce increases, so that the output impedance of error amplifier OP diminishes, the P1 pole frequency becomes large, the frequency-splitting of P1 limit and P2 limit can remain on enough large distance substantially, has guaranteed the stability of low pressure difference linear voltage regulator.
In other embodiments, described the first electric current provides the unit to realize by other bias current generating circuits in the prior art.
In other embodiments, described the second electric current provides the unit can adopt CCCS or Voltage-controlled Current Source to realize.When described the second electric current provided the unit to be CCCS, the control end of described CCCS was connected with the output terminal OUT2 of described low pressure difference linear voltage regulator.When described the second electric current provided the unit to be Voltage-controlled Current Source, the control end of described Voltage-controlled Current Source was adjusted transistorized grid with described PMOS and is connected.
In other embodiments, described the first current lens unit, the second current lens unit and the 3rd current lens unit also can adopt in the prior art current mirroring circuit of other types to realize.
The present invention also provides a kind of limit method of adjustment of low pressure difference linear voltage regulator, comprising:
Step S1 provides reference current and regulates electric current, and described adjusting electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
Step S2, superpose described reference current and adjusting electric current are to obtain bias current;
Step S3 provides the bias current input end of the error amplifier of described bias current to the described low pressure difference linear voltage regulator.
Optionally, the providing adjusting electric current among the step S1 can comprise: gather the output end current of described low pressure difference linear voltage regulator to produce described adjusting electric current.
Optionally, the providing adjusting electric current among the step S1 also can comprise: the PMOS that gathers in the described low pressure difference linear voltage regulator adjusts transistorized gate terminal voltage to produce described adjusting electric current.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. a low pressure difference linear voltage regulator is characterized in that, comprising: error amplifier, the first electric current provide unit, the second electric current to provide unit, PMOS to adjust transistor, the first resistance and the second resistance;
Described PMOS adjusts transistorized source electrode and connects the first voltage end, and drain electrode connects the first end of described the first resistance, and grid connects the output terminal of described error amplifier;
Described the first electric current provides the unit to be suitable for producing reference current;
Described the second electric current provides the unit to be suitable for producing and regulates electric current, and described adjusting electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
The first input end input reference voltage of described error amplifier, the second input end connect the second end of described the first resistance and the first end of the second resistance, and the bias current input end is inputted described reference current and regulated the bias current that the electric current stack produces;
The first end of described the first resistance is the output terminal of described low pressure difference linear voltage regulator;
The second end of described the second resistance connects the second voltage end;
The magnitude of voltage of described the first voltage end is greater than the magnitude of voltage of second voltage end.
2. low pressure difference linear voltage regulator as claimed in claim 1 is characterized in that, described the second electric current provides the unit to comprise: the 2nd PMOS transistor and the first current lens unit;
The transistorized source electrode of described the 2nd PMOS connects described the first voltage end, and drain electrode connects the input end of described the first current lens unit, and grid connects described PMOS and adjusts transistorized grid;
The first output terminal of described the first current lens unit connects the bias current input end of described error amplifier, and the second output terminal connects described second voltage end.
3. low pressure difference linear voltage regulator as claimed in claim 2 is characterized in that, described the first current lens unit comprises: the first nmos pass transistor and the second nmos pass transistor;
The drain electrode of described the first nmos pass transistor connects the grid of the grid of the first nmos pass transistor and the second nmos pass transistor and as the input end of described the first current lens unit, source electrode connects described second voltage end;
The drain electrode of described the second nmos pass transistor is as the first output terminal of described the first current lens unit, and source electrode is as the second output terminal of described the first current lens unit.
4. low pressure difference linear voltage regulator as claimed in claim 1 is characterized in that, described the second electric current provides the unit to comprise: the second current lens unit and the 3rd current lens unit;
Described PMOS adjusts transistorized drain electrode connects described the first resistance by described the second current lens unit first end;
The input end of described the second current lens unit connects described PMOS and adjusts transistorized drain electrode, and the first output terminal connects the first end of described the first resistance, and the second output terminal connects the input end of described the 3rd current lens unit;
The first output terminal of described the 3rd current lens unit connects the bias current input end of described error amplifier, and the second output terminal connects described second voltage end.
5. low pressure difference linear voltage regulator as claimed in claim 4 is characterized in that, described the second current lens unit comprises: the 3rd PMOS transistor and the 4th PMOS transistor;
The transistorized source electrode of described the 3rd PMOS connects the transistorized source electrode of described the 4th PMOS and as the input end of described the second current lens unit, and grid connects the transistorized drain electrode of described the 3rd PMOS and the transistorized grid of the 4th PMOS and as the first output terminal of described the second current lens unit;
The transistorized drain electrode of described the 4th PMOS is as the second output terminal of described the second current lens unit.
6. low pressure difference linear voltage regulator as claimed in claim 4 is characterized in that, described the 3rd current lens unit comprises: the 3rd nmos pass transistor and the 4th nmos pass transistor;
The drain electrode of described the 3rd nmos pass transistor connects the grid of the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor and as the input end of described the 3rd current lens unit, source electrode connects described second voltage end;
The drain electrode of described the 4th nmos pass transistor is as the first output terminal of described the 3rd current lens unit, and source electrode is as the second output terminal of described the 3rd current lens unit.
7. low pressure difference linear voltage regulator as claimed in claim 1 is characterized in that, described adjusting electric current increases with the electric current of the output terminal of described low pressure difference linear voltage regulator.
8. the limit method of adjustment of a low pressure difference linear voltage regulator is characterized in that, comprising:
Reference current is provided and regulates electric current, described adjusting electric current is associated with the electric current of the output terminal of described low pressure difference linear voltage regulator;
Superpose described reference current and regulate electric current is to obtain bias current;
The bias current input end of the error amplifier of described bias current to the described low pressure difference linear voltage regulator is provided.
9. limit method of adjustment as claimed in claim 8 is characterized in that, provides the adjusting electric current to comprise:
Gather the output end current of described low pressure difference linear voltage regulator to produce described adjusting electric current.
10. limit method of adjustment as claimed in claim 8 is characterized in that, provides the adjusting electric current to comprise:
The PMOS that gathers in the described low pressure difference linear voltage regulator adjusts transistorized gate terminal voltage to produce described adjusting electric current.
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| US10168727B2 (en) | 2015-02-17 | 2019-01-01 | Vanchip (Tianjin) Technology Co., Ltd. | Adaptive low-dropout regulator having wide voltage endurance range, chip and terminal |
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