CN104635823B - Low-dropout linear voltage-regulating circuit - Google Patents
Low-dropout linear voltage-regulating circuit Download PDFInfo
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- CN104635823B CN104635823B CN201310567291.8A CN201310567291A CN104635823B CN 104635823 B CN104635823 B CN 104635823B CN 201310567291 A CN201310567291 A CN 201310567291A CN 104635823 B CN104635823 B CN 104635823B
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Abstract
A kind of low-dropout linear voltage-regulating circuit, including: error amplifier, the first resistance, the second resistance, the first current mirroring circuit, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first PMOS and the second current mirroring circuit.The low-dropout linear voltage-regulating circuit that the present invention provides can improve the frequency of time limit so that secondary limit becomes big with dominant pole distance, thus exports stabilization signal.
Description
Technical field
The present invention relates to electronic applications, particularly relate to a kind of low-dropout linear voltage-regulating circuit.
Background technology
Compared with prior art, low-dropout linear voltage-regulating circuit (Low Dropout Regulator, LDO)
Step-down type dc linear voltage regulator, along with SOC(System on Chip, SOC(system on a chip)) technology send out
Exhibition, it is in sector applications such as computer, communication, instrument and meter, consumer electronics, monitoring camera-shootings nowhere
Do not exist.Although compared with DC-DC switching voltage converter, the efficiency of LDO is lower, but its tool
There are the advantages such as peripheral cell is few, ripple is little, noise is low, chip area is little, circuit structure is simple, so
LDO occupies the biggest proportion in power management class chip always.
Along with the raising of integrated level, increasing LDO closes to certain as the submodule of SOC
The module for power supply of key and be integrated in this SOC, and integrated multiple in powerful SOC
LDO module gives different module for power supply very common.Simultaneously continuous along with the operating frequency of SOC system
Improving, digital circuit therein brings power supply disturbance the most increasingly severe, and this is accomplished by LDO high speed wink
The performance requirements such as state response speed, high output voltage control accuracy, high PSRR, low noise.
As it is shown in figure 1, existing LDO circuit includes: error amplifier EA, adjustment pipe MP, the first electricity
Resistance R1 and the second resistance R2.The first input end of described error amplifier is suitable to input reference voltage Vref,
Second input connects the first end and first end of the second resistance R2 of the first resistance R1, and output connects
Adjust the grid of pipe MP.The second end ground connection of the second resistance R2.Adjusting pipe MP is PMOS, adjusts
The source electrode of homogeneous tube MP is suitable to input supply voltage, and drain electrode connects the first end of the first resistance.
But, easily there is the jitter that output VOUT exports in existing LDO.
Summary of the invention
The problem that the present invention solves is that existing low-dropout linear voltage-regulating circuit easily occurs that output signal is unstable.
For solving the problems referred to above, the present invention provides a kind of low-dropout linear voltage-regulating circuit, including: error is put
Big device, the first resistance, the second resistance, the first current mirroring circuit, the first NMOS tube, the 2nd NMOS
Pipe, the 3rd NMOS tube, the first PMOS and the second current mirroring circuit；
The first input end of described error amplifier is suitable to input reference voltage, and the second input connects described
First end of the second resistance and the second end of the first resistance；
First end of described first current mirroring circuit is suitable to input the first voltage, described first current mirroring circuit
The second end be suitable to input described first voltage, described in the three-terminal link of described first current mirroring circuit
The drain electrode of three NMOS tube, the 4th end of described first current mirroring circuit connects described first NMOS tube
Drain electrode, the grid of the first NMOS tube and the grid of the first PMOS；
The source electrode of described 3rd NMOS tube is suitable to input the second voltage, the grid of described 3rd NMOS tube
Connect the drain electrode of described first PMOS, the 3rd end of the second current mirroring circuit and the second NMOS tube
Drain electrode；
First end of described second current mirroring circuit is suitable to input described first voltage, described second current mirror
Second end of circuit is suitable to input described first voltage；
The source electrode of described first PMOS is suitable to input described first voltage；
The source electrode of described first NMOS tube is suitable to input described second voltage；
The output of the grid described error amplifier of connection of described second NMOS tube, described second
The source electrode of NMOS tube is suitable to input described second voltage；
First end of described first resistance connects the 4th end of described second current mirroring circuit；
Second end of described second resistance is suitable to input described second voltage；
The magnitude of voltage of described first voltage is more than the magnitude of voltage of described second voltage.
Compared with prior art, the low-dropout linear voltage-regulating circuit that the present invention provides can improve time limit
Frequency so that secondary limit becomes big with dominant pole distance, thus exports stabilization signal.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing low-dropout linear voltage-regulating circuit；
Fig. 2 is the structural representation of the low-dropout linear voltage-regulating circuit of the embodiment of the present invention 1；
Fig. 3 is a structural representation of the low-dropout linear voltage-regulating circuit of the embodiment of the present invention 2；
Fig. 4 is another structural representation of the low-dropout linear voltage-regulating circuit of the embodiment of the present invention 2.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
As in figure 2 it is shown, the embodiment of the present invention 1 provides a kind of low-dropout linear voltage-regulating circuit, including: by mistake
Difference amplifier EA, the first resistance R1, the second resistance R2, the first current mirroring circuit the 1, the oneth NMOS
Pipe MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the first PMOS MP1 and
Second current mirroring circuit 2.
The first input end of described error amplifier EA is suitable to input reference voltage Vref, and the second input is even
Connect the first end and second end of the first resistance R1 of described second resistance R2.
First end of described first current mirroring circuit 1 is suitable to input the first voltage VCC, described first electric current
Second end of mirror circuit 1 is suitable to input described first voltage VCC, the of described first current mirroring circuit 1
The drain electrode of the 3rd NMOS tube MN3 described in three-terminal link, the 4th end of described first current mirroring circuit 1
Connect the drain electrode of described first NMOS tube MN1, the grid of the first NMOS tube MN1 and a PMOS
The grid of pipe MP1.
The source electrode of described 3rd NMOS tube MN3 is suitable to input the second voltage GND, described 3rd NMOS
The grid of pipe MN3 connect the drain electrode of described first PMOS MP1, the of the second current mirroring circuit 2
Three ends and the drain electrode of the second NMOS tube MN2.
First end of described second current mirroring circuit 2 is suitable to input described first voltage VCC, and described second
Second end of current mirroring circuit 2 is suitable to input described first voltage VCC.
The source electrode of described first PMOS MP1 is suitable to input described first voltage VCC.
The source electrode of described first NMOS tube MN1 is suitable to input described second voltage GND.
The grid of described second NMOS tube MN2 connects the output of described error amplifier EA, described
The source electrode of the second NMOS tube MN2 is suitable to input described second voltage GND.
First end of described first resistance R1 connects the 4th end of described second current mirroring circuit 2.
Second end of described second resistance R2 is suitable to input described second voltage GND.
The magnitude of voltage of described first voltage is more than the magnitude of voltage of described second voltage.
Described reference voltage V ref can be provided by band gap reference or other a reference source.
Described first PMOS MP1 is operated in saturation region, thus increases mutual conductance.
The ratio of the current value of the 4th end of described first current mirroring circuit 1 and the current value of the 3rd end is permissible
More than 1.Such as, the current value of the current value of the 4th end of described first current mirroring circuit 1 and the 3rd end
Ratio is 4:1.
First current mirroring circuit may include that the second PMOS MP2 and the 3rd PMOS MP3.
The size ratio of described 3rd PMOS MP3 and the second PMOS MP2 can be more than 1.
The source electrode of described second PMOS MP2 is the first end of described first current mirroring circuit 1, described
The 3rd end that drain electrode is described first current mirroring circuit 1 of the second PMOS MP2, described 2nd PMOS
The grid of pipe MP2 connects the grid of described 3rd PMOS MP3 and described second PMOS MP2
Drain electrode.The source electrode of described 3rd PMOS MP3 is the second end of described first current mirroring circuit 1,
The 4th end that drain electrode is described first current mirroring circuit 1 of described 3rd PMOS MP3.
The ratio of the current value of the 4th end of described second current mirroring circuit 2 and the current value of the 3rd end is permissible
More than 1.Such as, the current value of the current value of the 4th end of described second current mirroring circuit 2 and the 3rd end
Ratio is 100:1.
Described second current mirroring circuit 2 may include that the 4th PMOS MP4 and the 5th PMOS
MP5.The size ratio of described 5th PMOS MP5 and the 4th PMOS MP4 can be more than 1.
The source electrode of described 4th PMOS MP4 is the first end of described second current mirroring circuit 2, described
The 3rd end that drain electrode is described second current mirroring circuit 2 of the 4th PMOS MP4, described 4th PMOS
The grid of pipe MP4 connects the grid of described 5th PMOS MP5 and described 4th PMOS MP4
Drain electrode, the source electrode of described 5th PMOS MP5 is the second end of described second current mirroring circuit 2,
The 4th end that drain electrode is described second current mirroring circuit 2 of described 5th PMOS MP5.
First end of described first resistance R1 can be as the output of described low-dropout linear voltage-regulating circuit
VOUT.The dominant pole of described low-dropout linear voltage-regulating circuit is positioned at described output VOUT, and secondary limit
P is positioned at the grid of the 3rd NMOS tube MN3.The output VOUT of low-dropout linear voltage-regulating circuit is
During middle low-load, the frequency of secondary limit P can be less than the loop bandwidth of whole low-dropout linear voltage-regulating circuit,
Make the jitter that output VOUT exports.The low pressure difference linearity that the embodiment of the present invention 1 provides is steady
Volt circuit can improve the frequency of time limit P so that secondary limit P becomes big with dominant pole distance, thus defeated
Go out stabilization signal.
As it is shown on figure 3, the difference of the embodiment of the present invention 2 and embodiment 1 is also to include: bias voltage
Circuit 3 and the 6th PMOS MP6 are provided.
Described bias voltage provides circuit 3 to be suitable to export bias voltage, described 6th PMOS MP6
Grid is suitable to input described bias voltage.The source electrode of described 6th PMOS MP6 is suitable to input described
One voltage VCC.The drain electrode of described 6th PMOS MP6 connects described 3rd NMOS tube MN3
Grid.Described 6th PMOS MP6 is operated in linear zone.
Described bias voltage provides circuit 3 to may include that the 7th PMOS MP7 and current source 31.
The source electrode of described 7th PMOS MP7 is suitable to input described first voltage VCC, and the described 7th
The grid of PMOS MP7 connects drain electrode and the input of current source 31 of described 7th PMOS MP7
Hold and be suitable to export described bias voltage.The output of described current source 31 is suitable to input described second voltage
GND。
The size ratio of described 7th PMOS MP7 and the 6th PMOS MP6 can be more than 1.Example
If, the size of described 7th PMOS MP7 and the 6th PMOS MP6 is than for 8:1.Described 7th
The size ratio of PMOS MP7 and the second PMOS MP2 can be equal to 1.
In the present embodiment, described low-dropout linear voltage-regulating circuit can also include: electric capacity C.Described electricity
The first end holding C connects first end of the first resistance R1, and second end of described electric capacity C is suitable to input the
Two voltage GND.
The 6th PMOS MP6 mutual conductance described in the embodiment of the present invention 2 is big, thus at the base of embodiment 1
The frequency of time limit P is improved further so that output signal is more stable on plinth.
As shown in Figure 4, the low-dropout linear voltage-regulating circuit that the embodiment of the present invention 2 provides can also include:
8th PMOS MP8.
The grid of described 8th PMOS MP8 is suitable to input described bias voltage, described 8th PMOS
The source electrode of pipe MP8 is suitable to input described first voltage VCC, the drain electrode of described 8th PMOS MP8
Connect the drain electrode of described 3rd NMOS tube MN3.Described 8th PMOS MP8 can improve loop
Gain.
The first voltage VCC described in above-described embodiment can be the power supply electricity of low-dropout linear voltage-regulating circuit
Pressure, the second voltage GND can be ground voltage.Described first current mirroring circuit 1 and the second current mirroring circuit
2 can also use the current mirroring circuit of other structures in prior art, and the present invention is without limitation.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (9)
1. a low-dropout linear voltage-regulating circuit, it is characterised in that including: error amplifier, the first resistance,
Second resistance, the first current mirroring circuit, the first NMOS tube, the second NMOS tube, the 3rd NMOS
Pipe, the first PMOS and the second current mirroring circuit；
The first input end of described error amplifier is suitable to input reference voltage, and the second input connects described
First end of the second resistance and the second end of the first resistance；
First end of described first current mirroring circuit is suitable to input the first voltage, described first current mirroring circuit
The second end be suitable to input described first voltage, described in the three-terminal link of described first current mirroring circuit
The drain electrode of three NMOS tube, the 4th end of described first current mirroring circuit connects described first NMOS tube
Drain electrode, the grid of the first NMOS tube and the grid of the first PMOS；
The source electrode of described 3rd NMOS tube is suitable to input the second voltage, the grid of described 3rd NMOS tube
Connect the drain electrode of described first PMOS, the 3rd end of the second current mirroring circuit and the second NMOS tube
Drain electrode；
First end of described second current mirroring circuit is suitable to input described first voltage, described second current mirror
Second end of circuit is suitable to input described first voltage；
The source electrode of described first PMOS is suitable to input described first voltage；
The source electrode of described first NMOS tube is suitable to input described second voltage；
The output of the grid described error amplifier of connection of described second NMOS tube, described second
The source electrode of NMOS tube is suitable to input described second voltage；
First end of described first resistance connects the 4th end of described second current mirroring circuit；
Second end of described second resistance is suitable to input described second voltage；
The magnitude of voltage of described first voltage is more than the magnitude of voltage of described second voltage.
2. low-dropout linear voltage-regulating circuit as claimed in claim 1, it is characterised in that described first current mirror
Circuit includes: the second PMOS and the 3rd PMOS, and the source electrode of described second PMOS is described
First end of the first current mirroring circuit, the drain electrode of described second PMOS is described first current mirroring circuit
The 3rd end, the grid of described second PMOS connects the grid and described the of described 3rd PMOS
The drain electrode of two PMOS, source electrode is described first current mirroring circuit the second of described 3rd PMOS
End, the 4th end that drain electrode is described first current mirroring circuit of described 3rd PMOS.
3. low-dropout linear voltage-regulating circuit as claimed in claim 1, it is characterised in that described second current mirror
Circuit includes: the 4th PMOS and the 5th PMOS, and the source electrode of described 4th PMOS is described
First end of the second current mirroring circuit, the drain electrode of described 4th PMOS is described second current mirroring circuit
The 3rd end, the grid of described 4th PMOS connects the grid and described the of described 5th PMOS
The drain electrode of four PMOS, source electrode is described second current mirroring circuit the second of described 5th PMOS
End, the 4th end that drain electrode is described second current mirroring circuit of described 5th PMOS.
4. low-dropout linear voltage-regulating circuit as claimed in claim 1, it is characterised in that also include: biased electrical
Pressure provides circuit and the 6th PMOS, and described bias voltage provides circuit to be suitable to export bias voltage, institute
The grid stating the 6th PMOS is suitable to input described bias voltage, and the source electrode of described 6th PMOS is fitted
In inputting described first voltage, the drain electrode of described 6th PMOS connects the grid of described 3rd NMOS tube
Pole.
5. low-dropout linear voltage-regulating circuit as claimed in claim 4, it is characterised in that described bias voltage carries
Including for circuit: the 7th PMOS and current source, the source electrode of described 7th PMOS is suitable to input institute
Stating the first voltage, the grid of described 7th PMOS connects drain electrode and the electric current of described 7th PMOS
The input in source is also suitable to export described bias voltage, and the output of described current source is suitable to input described
Two voltages.
6. low-dropout linear voltage-regulating circuit as claimed in claim 4, it is characterised in that also include: the 8th
PMOS, the grid of described 8th PMOS is suitable to input described bias voltage, described 8th PMOS
The source electrode of pipe is suitable to input described first voltage, and the drain electrode of described 8th PMOS connects the described 3rd
The drain electrode of NMOS tube.
7. low-dropout linear voltage-regulating circuit as claimed in claim 4, it is characterised in that described 6th PMOS
Pipe works at linear zone.
8. low-dropout linear voltage-regulating circuit as claimed in claim 1, it is characterised in that described first current mirror
The ratio of the current value of the 4th end of circuit and the current value of the 3rd end is more than 1.
9. low-dropout linear voltage-regulating circuit as claimed in claim 1, it is characterised in that described second current mirror
The ratio of the current value of the 4th end of circuit and the current value of the 3rd end is more than 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310567291.8A CN104635823B (en) | 2013-11-14 | 2013-11-14 | Low-dropout linear voltage-regulating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310567291.8A CN104635823B (en) | 2013-11-14 | 2013-11-14 | Low-dropout linear voltage-regulating circuit |
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| CN104635823A CN104635823A (en) | 2015-05-20 |
| CN104635823B true CN104635823B (en) | 2016-09-07 |
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| CN201310567291.8A Active CN104635823B (en) | 2013-11-14 | 2013-11-14 | Low-dropout linear voltage-regulating circuit |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI628528B (en) * | 2017-03-13 | 2018-07-01 | 盛群半導體股份有限公司 | Voltage generator |
| US9989981B1 (en) * | 2017-06-16 | 2018-06-05 | Apple Inc. | Cascaded LDO voltage regulator |
| CN108733118B (en) * | 2018-05-31 | 2023-04-28 | 福州大学 | High-power supply rejection ratio quick response LDO |
| CN109116901B (en) * | 2018-10-31 | 2023-09-15 | 上海艾为电子技术股份有限公司 | Linear voltage stabilizing circuit and integrated circuit |
| CN112527046B (en) * | 2019-09-17 | 2022-07-01 | 成都纳能微电子有限公司 | Voltage conversion current circuit with high power supply rejection ratio |
| CN112783256B (en) * | 2019-11-08 | 2022-06-24 | 奇景光电股份有限公司 | Low dropout regulator based on subthreshold region |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945059A (en) * | 2012-11-21 | 2013-02-27 | 上海宏力半导体制造有限公司 | Low dropout linear regulator and pole adjustment method thereof |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945059A (en) * | 2012-11-21 | 2013-02-27 | 上海宏力半导体制造有限公司 | Low dropout linear regulator and pole adjustment method thereof |
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| CN104635823A (en) | 2015-05-20 |
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