CN101833346A - Low dropout regulator with enhanced precision and power supply rejection rate - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit and in particular relates to a novel low dropout regulator (LDO) with enhanced precision and power supply rejection rate. The low dropout regulator consists of an error amplifier, a voltage buffer, a P-channel metal oxide semiconductor (PMOS) regulating pipe, a resistance feedback network and an output capacitor. Under the conditions of not changing the impedance of an output point and not influencing the stability of the loop of the LDO, in the low dropout regulator, an interstage amplifier section with a certain gain is introduced into the error amplifier and the direct current gain is increased by increasing the impedance of an internal node, so stable frequency compensation is realized and the precision and the power supply rejection rate of the LDO are enhanced.

Description

The low pressure difference linear voltage regulator that a kind of precision and Power Supply Rejection Ratio strengthen

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of novel precision and the low pressure difference linear voltage regulator of Power Supply Rejection Ratio enhancing.

Background technology

Along with adopting battery powered portable electric appts to be widely used, high performance power management becomes more and more important.Low pressure difference linear voltage regulator (LDO) usually is used to provide stable, low noise power supply as the subsequent conditioning circuit of DC-DC converter, is the circuit supplies high to power requirement such as simulation and radio frequency.This just requires LDO realizing also needing to have high precision and high Power Supply Rejection Ratio (PSRR) under the stable frequency compensated condition.

Existing LDO technology generally adjusts pipe (3), resistance-feedback network (4,5) by error amplifier (18), voltage buffer (2), PMOS and output capacitance (6) constitutes.For the requirement to precision and PSRR, error amplifier (18) needs very big gain.This just causes its output terminal impedance r _O1Very big.And large-sized PMOS adjusts the grid capacitance C of pipe (3) _P2Equally very big.Under the situation of making alive impact damper (2) not, in the feedback control loop by 1/r _O1C _P2The low-frequency pole that produces can make frequency compensation become very difficult.And adding voltage buffer (2) afterwards, this limit can be separated into two higher limit 1/r of relative frequency _O1C _P1And 1/r _O2C _P2By using big output capacitance (usually in μ F magnitude), this moment, the dominant pole of loop can design at output terminal.But, in this case to the output impedance r of error amplifier _O1Still conditional, too big output impedance still can cause limit 1/r _O1C _P1Frequency too low.Under the big situation of load current change, the output terminal impedance r of LDO _OLCan diminish, this moment, the LDO backfeed loop might be unstable.

As the above analysis, the requirement to the stability of LDO backfeed loop has limited the output impedance r of error amplifier (18) _O1Thereby, limited its gain.And the precision of LDO and PSRR are by the gain of error amplifier decision.So traditional LDO structural limitations the raising of precision and PSRR.Under this background, when satisfying stability requirement, improve precision and the PSRR of LDO, be to have certain realistic meaning.

Summary of the invention

The purpose of this invention is to provide a kind of novel low pressure difference linear voltage regulator (LDO) circuit.This circuit can be realized high precision and high Power Supply Rejection Ratio (PSRR) when satisfying LDO backfeed loop stability.

The objective of the invention is by introducing the interstage amplifier section with certain gain in that error amplifier is inner, thereby improve the loop gain of LDO, the precision and the Power Supply Rejection Ratio that have promptly improved LDO realize.

Low pressure difference linear voltage regulator provided by the present invention adjusts pipe (3), resistance-feedback network (4,5) by improved error amplifier (1), voltage buffer (2), PMOS and output capacitance (6) constitutes, and its circuit diagram as shown in Figure 2.

Low pressure difference linear voltage regulator provided by the present invention, the output of its error amplifier (1) is connected on the input of voltage buffer (2); The output of voltage buffer (2) is connected on the grid that PMOS adjusts pipe (3); The source electrode that PMOS adjusts pipe (3) is connected on the input voltage, and drain electrode meets feedback resistance R _F1(4) a end; Feedback resistance R _F1(4) the other end is connected on feedback resistance R _F2(5) a end is connected the positive input terminal of error amplifier simultaneously; Feedback resistance R _F2Other end ground connection.

In low pressure difference linear voltage regulator provided by the present invention, the transistor level of error amplifier (1) is realized by metal-oxide-semiconductor M1-M9 (7,8,9,10,11,12,13,14,15) and resistance R 1, R2 (16,17) constitute, M1 wherein, M2 (7,8) constitute input difference to and provide bias current by M9 (15), M1, M2 (7,8) drain electrode and M3, M4 (9,10) drain electrode links to each other, M3, M4 (9,10) source electrode connect high level and grid by resistance R 1, R2 (16,17) be connected M5 with drain electrode, M6, M7, M8 (12,13,14,15) output stage of formation error amplifier (1).

Low pressure difference linear voltage regulator provided by the present invention, input voltage vin links to each other with the source electrode that PMOS adjusts pipe (3), and the while is as the power supply of error amplifier (1) and voltage buffer (2); Reference voltage V _RefLink to each other with the negative input end of error amplifier (1).

Low pressure difference linear voltage regulator provided by the present invention, wherein improved error amplifier (1) is under the situation that does not change output point impedance (promptly not influencing the loop stability of LDO), raising by the internal node impedance, increased DC current gain, therefore, realizing the stable frequency compensated while, improving precision and the Power Supply Rejection Ratio of LDO.

Description of drawings

Fig. 1 is a kind of existing low differential voltage linear voltage stabilizer circuit, and wherein 18 is error amplifier, and 2 is voltage buffer, and 3 for PMOS adjusts pipe, and 4,5 is resistance-feedback network, and 6 is output capacitance.

Fig. 2 is the low differential voltage linear voltage stabilizer circuit that the precision that proposes of the present invention and Power Supply Rejection Ratio strengthen, wherein 1 is error amplifier, 2 is voltage buffer, 3 are PMOS adjustment pipe, 4,5 is resistance-feedback network, 6 is output capacitance, and 7,8,9,10,11,12,13,14,15 is the metal-oxide-semiconductor in the transistor level circuit of error amplifier (1), and 16,17 is the resistance in the transistor level circuit of error amplifier (1).

Specific embodiments

Below in conjunction with specific embodiment, the present invention is further elaborated.Embodiment only is used for the present invention is done explanation rather than limitation of the present invention.

Embodiment 1

Present embodiment 2 further describes the present invention in conjunction with the accompanying drawings.

As shown in Figure 2, the low pressure difference linear voltage regulator of present embodiment adjusts pipe (3), resistance-feedback network (4,5) by error amplifier (1), voltage buffer (2), PMOS and output capacitance (6) constitutes, and wherein the output of error amplifier (1) is connected on the input of voltage buffer (2); The output of voltage buffer (2) is connected on the grid that PMOS adjusts pipe (3); The source electrode that PMOS adjusts pipe (3) is connected on the input voltage, and drain electrode meets feedback resistance R _F1(4) a end; Feedback resistance R _F1(4) the other end is connected on feedback resistance R _{f 2}(5) a end is connected the positive input terminal of error amplifier simultaneously; Feedback resistance R _F2Other end ground connection.The transistor level of error amplifier (1) is realized by metal-oxide-semiconductor M1-M9 (7,8,9,10,11,12,13,14,15) and resistance R 1, R2 (16,17) constitute, wherein M1, M2 (7,8) constitute input difference to and provide bias current by M9 (15), the drain electrode of M1, M2 (7,8) and M3, M4 (9,10) drain electrode links to each other, M3, M4 (9,10) source electrode connect high level and grid by resistance R 1, R2 (16,17) be connected with drain electrode, M5, M6, M7, M8 (12,13,14,15) constitute the output stage of error amplifier (1).The input voltage vin of low pressure difference linear voltage regulator links to each other with the source electrode that PMOS adjusts pipe (3), and the while is as the power supply of error amplifier (1) and voltage buffer (2); Reference voltage V _RefLink to each other with the negative input end of error amplifier (1).

The transistor level of error amplifier (1) has been introduced resistance R 1 and R2 (16,17) in realizing.Wherein R1 is connected between the drain and gate of M3, and R2 is connected between the drain and gate of M4, and they have identical resistance.Such connection can provide galvanic current flat on the one hand for follow-up circuit, this with Fig. 1 in to adopt the effect of M3, the M4 of diode connection be identical.But then, the impedance of being seen into to the drain electrode of M1, M3 by the grid of M5 this moment can be expressed as:

r _int＝r _o，M1//r _o，M3//R ₁ (1)

R wherein _{O, M1}And r _{O, M3}Be the M1 of raceway groove mudulation effect introducing and the resistance between the leakage of M3 source.Generally, r _{O, M1}＞＞R ₁, r _{O, M1}＞＞R ₁So expression formula (1) can abbreviation be:

r _int≈R ₁ (2)

The DC current gain of error amplifier (1) can be expressed as:

A _DC＝g _m1R ₁g _m5r _o1 (3)

G wherein _M1The expression input difference is to the mutual conductance of M1, M2, g _M5The mutual conductance of expression M5, M6.As a comparison, the DC current gain of error amplifier (18) can be expressed as among Fig. 1:

$A_{\mathrm{DC}}^{\&prime;}=\frac{g_{m1}{g}_{m5}{r}_{o1}}{{\mathrm{<figure-callout\; id="3"\; label="g\; m"\; filenames="H200910047606XE0000011.png,H200910047606XE0000012.png"\; state="\{\{state\}\}">g</figure-callout>}}_m}\&ap;g_{m5}{r}_{o1}---\left(4\right)$

G wherein _M3The mutual conductance of expression M3, M4.By comparison expression (3) and (4) as can be known, make A=g by the resistance of choosing R1, R2 _M1R ₁＞1, the DC current gain of error amplifier (1) has improved A doubly than the DC current gain of traditional error amplifier.This will bring the precision of LDO and Power Supply Rejection Ratio to be improved with same ratio.

From the angle of stability, the output impedance r of error amplifier this moment (1) _O1Constant, promptly the limit of error amplifier output terminal still is positioned at 1/r _O1C _P1The place.And the parasitic poles at the inner M5 grid of error amplifier (1) place is by original g _M3/ c _IntBecome 1/R ₁C _Int, step-down A doubly.Because g _M3/ c _IntOriginally be located in the very high frequency place of loop GBW of relative LDO, make the stability of loop not be affected so can choose the value of proper A.In the circuit design of reality, it doubly is acceptable that the frequency of this parasitic poles reduces 3-4.The precision that this means LDO can have 3-4 raising doubly, and PSRR can have the raising of 10-16dB.

Claims (5)

1. low pressure difference linear voltage regulator, adjust pipe (3), resistance-feedback network (4,5) and output capacitance (6) formation by error amplifier (1), voltage buffer (2), PMOS, it is characterized in that having an interstage amplifier section that gain effect is arranged in error amplifier (1) inside.

2. low pressure difference linear voltage regulator according to claim 1 is characterized in that the output of error amplifier (1) is connected on the input of voltage buffer (2); The source electrode that the output of voltage buffer (2) is connected on the grid PMOS adjustment pipe (3) of PMOS adjustment pipe (3) is connected on the input voltage, and drain electrode meets feedback resistance R _F1(4) a end; Feedback resistance R _F1(4) the other end is connected on feedback resistance R _F2(5) a end is connected the positive input terminal of error amplifier simultaneously; Feedback resistance R _F2Other end ground connection.

3. low pressure difference linear voltage regulator according to claim 1, the transistor level that it is characterized in that error amplifier (1) are realized being made of metal-oxide-semiconductor M1-M9 (7,8,9,10,11,12,13,14,15) and resistance R 1, R2 (16,17).

4. low pressure difference linear voltage regulator according to claim 3, it is characterized in that metal-oxide-semiconductor M1, M2 (7,8) in the error amplifier (1) constitute input difference to and provide bias current by metal-oxide-semiconductor M9 (15), the drain electrode of M1, M2 (7,8) and metal-oxide-semiconductor M3, M4 (9,10) drain electrode links to each other, M3, M4 (9,10) source electrode connect high level and grid by resistance R 1, R2 (16,17) be connected with drain electrode, metal-oxide-semiconductor M5, M6, M7, M8 (12,13,14,15) constitute the output stage of error amplifier (1).

5. low pressure difference linear voltage regulator according to claim 1 is characterized in that input voltage vin links to each other with the source electrode that PMOS adjusts pipe (3), and the while is as the power supply of error amplifier (1) and voltage buffer (2); Reference voltage V _RefLink to each other with the negative input end of error amplifier (1).

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