CN110716604A - Protection circuit of anti power consumption attack based on current levels technique - Google Patents
Protection circuit of anti power consumption attack based on current levels technique Download PDFInfo
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- CN110716604A CN110716604A CN201910966437.3A CN201910966437A CN110716604A CN 110716604 A CN110716604 A CN 110716604A CN 201910966437 A CN201910966437 A CN 201910966437A CN 110716604 A CN110716604 A CN 110716604A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
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Abstract
The utility model provides an anti power consumption attack's protection circuit structure based on current levels technique, includes current induction module (1), operational amplifier module (2), current injection compensation module (3), password core circuit module (8), frequency switching control module (6) and voltage regulation module (7). The current sensing module (1) detects the changing current delta Icore generated by the current Icore of the password core circuit and copies the current delta Icore image to the next stage, the high linearity conversion unit I → V (4) and the high linearity conversion unit V → I (5) in the current injection compensation module (3) perform linear conversion on the changing current delta Icore and the voltage delta V, convert the linear conversion of the voltage delta V and the compensating current delta IJ, and compensate the compensating current delta IJ on the changing current delta Icore, so that the changing current delta Itot detected by the password core circuit from a total voltage source is kept constant, and the purpose of current leveling is achieved.
Description
Technical Field
The invention designs a power consumption attack resistant protection circuit based on a current leveling technology, and relates to a protection circuit based on the current leveling technology for defending a power consumption attack resistant means. Belongs to the field of integrated circuit design and integrated system.
Background
Since the modern science and technology is entered, the intelligent chip is integrated on the password card, personal identification password information can be stored more safely, so that password equipment such as the intelligent password card and the like can be widely applied to financial departments, enterprise safety departments and government departments, and the safety problem is the only standard for checking the password chip. Due to the characteristics of the cryptographic equipment, an attacker is difficult to directly contact plaintext information of the cryptographic chip from a physical layer, but the attacker can utilize the information of current, power consumption, electromagnetic radiation, time and the like leaked during the operation of the cryptographic chip to estimate the correlation between the plaintext and the side channel information in the encryption process, so as to estimate the key information used by the cryptographic chip. The power consumption attack resisting technology has the characteristics of high attack speed, high accuracy, easiness in operation, independence on the degree of understanding of an attacker on target hardware and the like, and poses serious threat to the safety of cryptographic chips such as an intelligent cryptographic card and the like. The power consumption attack protection idea of the circuit level is that a special chip current control module or a chip power supply structure is adopted, and the correlation between the chip power consumption and the cryptographic algorithm operation executed by the chip power consumption is reduced.
Disclosure of Invention
The invention solves the problem that the compensation current generated by the current injection compensation module can not meet the requirement of high linearity at present, provides a power attack resistance protection circuit based on the current leveling technology, and adds a high linear voltage (current) conversion module on the basis of the original current injection compensation module to improve the linearity in order to keep the current of the power supply end of a password chip constant and further eliminate the correlation between the power consumption of the chip during working and the data in a password algorithm. In addition, the cipher core circuit in the circuit can operate at high and low clock frequencies, the frequency can be switched according to the magnitude of the power supply voltage of the core cipher circuit, in order to improve the stability, a dead zone is used in the frequency switching control module, and when the power supply voltage of the core cipher circuit reaches a certain value, the clock frequency cannot be changed.
The above object of the present invention is achieved mainly by the following means:
a protection circuit structure for resisting power consumption attack based on a current leveling technology mainly comprises a current induction module (1), an operational amplifier module (2), a current injection compensation module (3), a password core circuit module (8), a frequency switching control module (6) and a voltage regulation module (7);
current sensing module (1): the current control circuit is used for sensing a change current delta Icore generated by a current Icore flowing through the password core circuit and sending the change current delta Icore to the operational amplifier module through the mirror image circuit;
operational amplifier module (2): converting the change current delta Icore sent from the current sensing module (1) into corresponding change voltage delta V, and sending the change voltage delta V to the current injection compensation module (3);
current injection compensation module (3): including a high linearity conversion unit I → V (4) and a high linearity conversion unit V → I (5); the high linearity conversion unit V → I (5) is used for linearly converting the change current delta Icore into a compensation voltage, then linearly converting the change current delta Icore into a compensation current, sending the compensation current to the input end of the password core circuit, and compensating the change current delta Icore through the compensation current delta IJ so as to keep the change current delta Itot detected by the password core circuit from a total voltage source constant; frequency switching control module (6): the switching of 2 clock frequency working states is carried out by detecting the power supply voltage when the password core circuit works;
voltage regulation module (7): the activity of the current injection compensation module is supplemented, when the current passing through the power supply pin is larger than the reference current, the voltage regulation module (7) is activated, and the power supply voltage of the core circuit of the cryptographic chip is inversely proportional to the voltage of the core circuit of the cryptographic chip during normal operation.
The utility model provides a protection circuit structure of anti power consumption attack based on current levels technique which characterized in that: the circuit comprises a current sensing module (1), an operational amplifier module (2), a current injection compensation module (3), a high linearity conversion unit I → V (4), a high linearity conversion unit V → I (5), a frequency switching control module (6), a voltage regulation module (7) and a password core circuit module (8);
the current sensing module (1) is respectively provided with a current input end and an output end for acquiring a variable current delta Icore; the operational amplifier module (2) is respectively provided with an input end of a variable current delta Icore and an output end of a variable voltage delta V; the current injection compensation module (3) is respectively provided with a variable voltage delta V input end and a compensation current delta IJ output end; the frequency switching control module (6) is respectively provided with an input end and an output end; the voltage regulating module (7) is respectively provided with an input end and an output end thereof; the output end of the variable current delta Icore of the current sensing module (1) is connected with the input end of the operational amplifier module (2); the output end of the operational amplifier module (2) is connected with the input end of the current injection compensation module (3) and the input end of the frequency switching control module (6); the output end of the current injection compensation module (3) is respectively connected with one end of the password core circuit, which is connected with the power supply voltage, and one end of the password core circuit, which is grounded; the output end of the frequency switching control module (6) is connected with the password core circuit; the output end of the operational amplifier module (2) is connected with the voltage regulating module (7); the output end of the voltage regulating module (7) is grounded.
The current leveling technology-based power consumption attack resistant protection circuit structure as claimed in claim 1, wherein a high linearity conversion module is added on the basis of an original current leveling protection circuit to improve linearity so as to meet the requirement that compensation current generated by a current injection compensation module in the protection circuit cannot meet high linearity, thereby achieving the purpose of high linearity compensation.
The current flattening technology-based power consumption attack resistant protection circuit structure as claimed in claim 1, wherein a frequency switching control module is added on the basis of an original current flattening protection circuit, so that the cipher core circuit can work at high and low frequencies and can be switched, and the stability of the current flattening technology-based power consumption attack resistant protection circuit structure is further improved due to the addition of a dead zone in the frequency control module.
The structure of claim 1, wherein the current sensing module is modified, and an improved current mirror circuit is used to prevent the input transistor of the mirror circuit from sharing a part of voltage drop to cause the working voltage of the cryptographic core circuit to drop and fail to work.
The current flattening technology-based power consumption attack resistant protection circuit structure as claimed in claim 1, wherein the sense resistor in the current sensing module is improved to meet most of power supply voltages for testing, and the protection circuit can work normally under different power supply voltages.
The structure of claim 1, wherein the current injection compensation module comprises a PMOS transistor M4, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, an NMOS transistor M17, an NMOS transistor M18, an NMOS transistor M5, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M9, an NMOS transistor M10, and an NMOS transistor M6.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
when the cipher core circuit normally works, the current sensing module detects and copies a change current delta Icore generated by the current Icore flowing through the cipher core circuit, the copy and the amplification are realized through the operational amplifier module, the change current delta Icore is linearly converted into a change voltage delta V through the high linear conversion unit I → V in the current injection compensation module, the change voltage delta V is linearly converted into a compensation current delta IJ through the high linear conversion unit V → I, the total current change detected at the power supply voltage is constant, and the aim of leveling the current of the cipher core circuit and hiding the core current change is realized.
Drawings
Fig. 1 is a schematic diagram of a power consumption attack resistant protection circuit structure selection module based on a current leveling technology.
Fig. 2 is a schematic circuit structure diagram of a current injection compensation module of the protection circuit for resisting power consumption attack based on the current leveling and leveling technology.
Detailed Description
The present invention is further introduced to the details, the structural characteristics of the circuit, and the problems that the existing compensation current cannot satisfy high linearity and the cipher core circuit cannot respond quickly at different clock frequencies are solved. The invention is described in detail with particular reference to the accompanying drawings;
the invention provides a protection circuit structure for resisting power consumption attack based on a current leveling technology, which is used for solving the problem that the compensation current of a protection circuit based on the current leveling technology cannot meet the requirement of high linearity and the current leveling effect is not obvious. Fig. 1 is a schematic diagram of a circuit structure selection module according to the present invention, which includes a current sensing module (1), an operational amplifier module (2), a current injection compensation module (3), a high linearity conversion unit I → V (4), a high linearity conversion unit V → I (5), a frequency switching control module (6), a voltage regulation module (7), and a cipher core circuit module (8);
current sensing module (1): the current control circuit is used for sensing a change current delta Icore generated by a current Icore flowing through the password core circuit and sending the change current delta Icore to the operational amplifier module through the mirror image circuit;
operational amplifier module (2): converting the change current delta Icore sent from the current induction module (1) into corresponding change voltage delta V, and sending the change voltage delta V to the current injection compensation module;
current injection compensation module (3): including a high linearity conversion unit I → V (4) and a high linearity conversion unit V → I (5); the high linearity conversion unit V → I (5) is used for linearly converting the change current delta Icore into a compensation voltage, then linearly converting the change current delta Icore into a compensation current, sending the compensation current to the input end of the password core circuit, and compensating the change current delta Icore through the compensation current delta IJ so as to keep the change current delta Itot detected by the password core circuit from a total voltage source constant; frequency switching control module (6): switching between two clock frequency working states by detecting the power supply voltage when the password core circuit works;
voltage regulation module (7): the activity of the current injection compensation module is supplemented, when the current passing through the power supply pin is larger than the reference current, the voltage regulation module (7) is activated, and the power supply voltage of the core circuit of the cryptographic chip is inversely proportional to the voltage of the core circuit of the cryptographic chip during normal operation.
Fig. 2 is a schematic diagram of a power consumption attack resistant protection circuit structure based on a current leveling technology, and it can be seen from the diagram that a current injection compensation module comprises a PMOS transistor M4, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, an NMOS transistor M17, an NMOS transistor M18, an NMOS transistor M5, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M9, an NMOS transistor M10, and an NMOS transistor M6;
the improved circuit capable of increasing the linearity of the compensation current comprises a PMOS tube M7, a PMOS tube M8, a PMOS tube M13, a PMOS tube M14, an NMOS tube M5, an NMOS tube M11, an NMOS tube M12, an NMOS tube M9 and an NMOS tube M10;
the grid electrode of the PMOS tube M7, the grid electrode of the PMOS tube M8, the drain electrode of the PMOS tube M14 and the drain electrode of the NMOS tube M5 are connected with each other, the source electrode of the PMOS tube M7 is connected with the power supply voltage VDD, the source electrode of the PMOS tube M8 is connected with the power supply voltage VDD, the drain electrode of the PMOS tube M7 and the source electrode of the PMOS tube M13 are connected with each other, the drain electrode of the PMOS tube M8 and the source electrode of the PMOS tube M14 are connected with each other, the grid electrode of the PMOS tube M13 and the grid electrode of the PMOS tube M14 are connected with each other and connected with the bias voltage VB4, and the grid electrode of the;
the grid of the NMOS tube M9, the grid of the NMOS tube M10, the drain of the NMOS tube M12 and the constant current source IB2 are connected with each other, the other end of the constant current source IB2 is connected with a power voltage VDD, the source of the NMOS tube M9 is connected with GND, the source of the NMOS tube M10 is connected with GND, the drain of the NMOS tube M9 and the source of the NMOS tube M11 are connected with each other, the drain of the NMOS tube M10 and the source of the NMOS tube M12 are connected with each other, the drain of the NMOS tube M11, the grid of the NMOS tube M6 and the drain of the PMOS tube M13 are connected with each other, the source of the NMOS tube M6 is connected with GND, and the drain of the NMOS tube M6 is connected with;
the source of the PMOS tube M4 is connected with the output end of the current sensing module (1), the drain of the PMOS tube M4, the drain of the NMOS tube M15 and the source of the NMOS tube M5 are connected with each other, the gate of the NMOS tube M15 and the gate of the NMOS tube M16 are connected with a bias voltage VB1, the source of the NMOS tube M15 and the drain of the NMOS tube M17 are connected with each other, the gate of the NMOS tube M17, the gate of the NMOS tube M18 and the drain of the NMOS tube M16 are connected with each other, the drain of the NMOS tube M16 is connected with a constant current source IR, the other end of the constant current source 695IR is connected with a power voltage, the source of the NMOS tube M17 is grounded, the source end of the NMOS tube M2 is grounded GND, the drain of the NMOS tube M5, the gate of the PMOS tube M7, the gate of the PMOS tube M8 and the drain of the PMOS tube M14 are connected with each other, the gate of the NMOS tube M5 is connected with the bias voltage VB 58, the drain of the PMOS tube M7 and the source of the PMOS tube M7 are connected with the, The source of the PMOS transistor M14 is connected with each other, the source of the PMOS transistor M8 is connected with GND, the source of the PMOS transistor M8 is connected with the power voltage VDD, the gate of the PMOS transistor M13 and the gate of the PMOS transistor M14 are connected with the bias voltage VB4, the drain of the PMOS transistor M13, the gate of the NMOS transistor M6 and the drain of the NMOS transistor M11 are connected with each other, the source of the NMOS transistor M11 and the drain of the NMOS transistor M9 are connected with each other, the gate of the NMOS transistor M11 and the gate of the NMOS transistor M12 are connected with each other with the bias voltage VB1, the gate of the NMOS transistor M9, the gate of the NMOS transistor M10, the drain of the NMOS transistor M12 and the constant current source IB2, the other end of the constant current source IB2 is connected with the power voltage VDD, the source of the NMOS transistor M9 is connected with ground, the source of the NMOS transistor M12 and the drain of the NMOS transistor M10, the source of the drain of the NMOS transistor M10 is connected with the core circuit (the input terminal of the cryptographic circuit M368.
The current sensing module (1) detects and transmits a change current delta Icore generated by the core current Icore to be converted into a change voltage delta V, the change voltage delta V is transmitted to the NMOS tube M4, and the change current delta Icore is added or subtracted with a constant current source to obtain a compensation current delta IJThrough the NMOS tube M5, the compensation current delta IJ flowing through the NMOS tube M5 is copied through a mirror image circuit and enters a high linearity conversion unit, wherein the PMOS tube M7, the PMOS tube M8, the PMOS tube M13, the PMOS tube M14, the NMOS tube M5, the NMOS tube M11, the NMOS tube M12, the NMOS tube M9 and the NMOS tube M10 work in a saturation region to improve the conversion of high linearity, so that the compensation current delta IJ and the input voltage can keep a high linearity relation.
In view of the foregoing, it is to be understood that the principles of the invention have been described in connection with specific embodiments thereof. The scope of the invention is not limited thereto. Any person skilled in the art can make simple structural changes within the scope of the present disclosure, and the changes are within the scope of the present disclosure. Therefore, the protection scope of the present invention shall be subject to the scope of the claims.
Claims (6)
1. The utility model provides a protection circuit structure of anti power consumption attack based on current levels technique which characterized in that: the circuit comprises a current sensing module (1), an operational amplifier module (2), a current injection compensation module (3), a high linearity conversion unit I → V (4), a high linearity conversion unit V → I (5), a frequency switching control module (6), a voltage regulation module (7) and a password core circuit module (8);
the current sensing module (1) is respectively provided with a circuit input end and an output end for acquiring a variable current delta Icore; the operational amplifier module (2) is respectively provided with an input end of a variable current delta Icore and an output end of a variable voltage delta V; the current injection compensation module (3) is respectively provided with a variable voltage delta V input end and a compensation current delta IJ output end; the frequency switching control module (6) is respectively provided with an input end and an output end; the voltage regulating module (7) is respectively provided with an input end and an output end thereof; the output end of the variable current delta Icore of the current sensing module (1) is connected with the input end of the operational amplifier module (2); the output end of the operational amplifier module (2) is connected with the input end of the current injection compensation module (3) and the input end of the frequency switching control module (6); the output end of the current injection compensation module (3) is respectively connected with one end of the password core circuit, which is connected with the power supply voltage, and one end of the password core circuit, which is grounded; the output end of the frequency switching control module (6) is connected with the password core circuit; the output end of the operational amplifier module (2) is connected with the voltage regulating module (7); the output end of the voltage regulating module (7) is grounded;
current sensing module (1): the current control circuit is used for sensing a change current delta Icore generated by a current Icore flowing through the password core circuit and sending the change current delta Icore to the operational amplifier module through the mirror image circuit;
operational amplifier module (2): converting a change circuit delta Icore sent from the current sensing module (1) into corresponding change voltage delta V, and sending the change voltage delta V to the current injection compensation module (3);
current injection compensation module (3): the high linearity conversion unit I → V (4) and the high linearity conversion unit V → I (5) are linearly converted into compensation current and sent to the input end of the password core circuit, and the change current delta Icore is compensated through the compensation current delta IJ, so that the change current delta Itot detected by the password core circuit from a total voltage source is kept constant;
frequency switching control module (6): the switching of 2 clock frequency working states is carried out by detecting the power supply voltage when the password core circuit works;
voltage regulation module (7): the activity of the current injection compensation module is supplemented, when the current passing through the power supply pin is larger than the reference current, the voltage regulation module (7) is activated, and the power supply voltage of the core circuit of the cryptographic chip is inversely proportional to the voltage of the core circuit of the cryptographic chip during normal operation.
2. The current flattening technology-based power consumption attack resistant protection circuit structure as claimed in claim 1, wherein a frequency switching module is added on the basis of the original current flattening protection circuit, so that the cipher core circuit can work at high and low frequencies and can be switched.
3. The structure of claim 1, wherein the current sensing module is modified, and an improved current mirror circuit is used to prevent the input transistor of the mirror circuit from sharing a part of voltage drop to cause the working voltage of the cryptographic core circuit to drop and fail to work.
4. The current flattening technology-based power consumption attack resistant protection circuit structure as claimed in claim 1, wherein the sense resistor in the current sensing module is improved to meet most of power supply voltages for testing, and the protection circuit can work normally under different power supply voltages.
5. The circuit structure of claim 1, wherein the high linearity converting unit I → V (4), the high linearity converting unit V → I (5), and the improved circuit for increasing the linearity of the compensation current comprises a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M5, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M9, an NMOS transistor M10;
the grid electrode of the PMOS tube M7, the grid electrode of the PMOS tube M8, the drain electrode of the PMOS tube M14 and the drain electrode of the NMOS tube M5 are connected with each other, the source electrode of the PMOS tube M7 is connected with a power supply voltage VDD, the source electrode of the PMOS tube M8 is connected with the power supply voltage VDD, the drain electrode of the PMOS tube M7 and the source electrode of the PMOS tube M13 are connected with each other, the drain electrode of the PMOS tube M8 and the source electrode of the PMOS tube M14 are connected with each other, the grid electrode of the PMOS tube M13 and the grid electrode of the PMOS tube M14 are connected with a bias voltage VB4, and the grid electrode of the NMOS tube M5 is;
the grid of the NMOS tube M9, the grid of the NMOS tube M10, the drain of the NMOS tube M12 and the constant current source IB2 are connected with each other, the other end of the constant current source IB2 is connected with a power voltage VDD, the source of the NMOS tube M9 is connected with GND, the source of the NMOS tube M10 is connected with GND, the drain of the NMOS tube M9 and the source of the NMOS tube M11 are connected with each other, the drain of the NMOS tube M10 and the source of the NMOS tube M12 are connected with each other, the drain of the NMOS tube M11, the grid of the NMOS tube M6 and the drain of the PMOS tube M13 are connected with each other, the source of the NMOS tube M6 is connected with GND, and the drain of the NMOS tube M6 is connected with.
6. The protection circuit structure of claim 1, wherein the circuit structure of the current injection compensation module (3) comprises a PMOS transistor M4, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, an NMOS transistor M17, an NMOS transistor M18, an NMOS transistor M5, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M6;
the source of the PMOS tube M4 is connected with the output end of the current sensing module (1), the drain of the PMOS tube M4, the drain of the NMOS tube M15 and the source of the NMOS tube M5 are connected with each other, the gate of the NMOS tube M15 and the gate of the NMOS tube M16 are connected with a bias voltage VB1, the source of the NMOS tube M15 and the drain of the NMOS tube M17 are connected with each other, the gate of the NMOS tube M17, the gate of the NMOS tube M18 and the drain of the NMOS tube M16 are connected with each other, the drain of the NMOS tube M16 is connected with a constant current source IR, the other end of the constant current source IR is connected with a power voltage, the source of the NMOS tube M17 is grounded, the source end of the NMOS tube M18 is grounded, the drain of the NMOS tube M5, the gate of the PMOS tube M7, the gate of the PMOS tube M8 and the drain of the PMOS tube M14 are connected with each other, the gate of the NMOS tube M5 is connected with the bias voltage VB 58, the drain of the PMOS tube M7 and the source of the PMOS tube M7 are grounded, the source of the PMOS, The source of the PMOS transistor M14 is connected with each other, the source of the PMOS transistor M8 is connected with GND, the source of the PMOS transistor M8 is connected with the power voltage VDD, the gate of the PMOS transistor M13 and the gate of the PMOS transistor M14 are connected with the bias voltage VB4, the drain of the PMOS transistor M13, the gate of the NMOS transistor M6 and the drain of the NMOS transistor M11 are connected with each other, the source of the NMOS transistor M11 and the drain of the NMOS transistor M9 are connected with each other, the gate of the NMOS transistor M11 and the gate of the NMOS transistor M12 are connected with each other with the bias voltage VB1, the gate of the NMOS transistor M9, the gate of the NMOS transistor M10, the drain of the NMOS transistor M12 and the constant current source IB2, the other end of the constant current source IB2 is connected with the power voltage VDD, the source of the NMOS transistor M9 is connected with ground, the source of the NMOS transistor M12 and the drain of the NMOS transistor M10, the source of the drain of the NMOS transistor M10 is connected with the core circuit (the input terminal of the cryptographic circuit M368.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910966437.3A CN110716604B (en) | 2019-10-11 | 2019-10-11 | Protection circuit for resisting power consumption attack based on current leveling technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910966437.3A CN110716604B (en) | 2019-10-11 | 2019-10-11 | Protection circuit for resisting power consumption attack based on current leveling technology |
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| CN110716604A true CN110716604A (en) | 2020-01-21 |
| CN110716604B CN110716604B (en) | 2023-06-13 |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0401498D0 (en) * | 2003-02-06 | 2004-02-25 | Samsung Electronics Co Ltd | Smart cards having protection circuits therein that inhibit power analysis attacks and methods of operating same |
| US20070076890A1 (en) * | 2005-08-24 | 2007-04-05 | The University Of Guelph | Current flattening and current sensing methods and devices |
| CN102063146A (en) * | 2011-01-21 | 2011-05-18 | 东南大学 | Adaptive frequency-compensation linear voltage stabilizer with low voltage difference |
| CN102999077A (en) * | 2012-12-03 | 2013-03-27 | 哈尔滨工业大学（威海） | Current leveling circuit with high linear compensation |
| CN103023324A (en) * | 2012-11-21 | 2013-04-03 | 东南大学 | Fast transient response DC-DC (direct-current to direct-current) switching converter with high load regulation rate |
| CN103838286A (en) * | 2012-11-20 | 2014-06-04 | 杨洁 | Low dropout linear regulator with quick transient response and high stability |
| CN107483172A (en) * | 2017-08-30 | 2017-12-15 | 哈尔滨工业大学（威海） | A kind of password protecting circuit for being used to defend energy consumption to attack |
| CN109327206A (en) * | 2018-09-30 | 2019-02-12 | 天津大学 | Power consumption planarizes standard integrated circuit |
| US20190097786A1 (en) * | 2018-09-24 | 2019-03-28 | Lovely Professional University | System and method for generating a symmetrically balanced output |
-
2019
- 2019-10-11 CN CN201910966437.3A patent/CN110716604B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0401498D0 (en) * | 2003-02-06 | 2004-02-25 | Samsung Electronics Co Ltd | Smart cards having protection circuits therein that inhibit power analysis attacks and methods of operating same |
| US20070076890A1 (en) * | 2005-08-24 | 2007-04-05 | The University Of Guelph | Current flattening and current sensing methods and devices |
| CN102063146A (en) * | 2011-01-21 | 2011-05-18 | 东南大学 | Adaptive frequency-compensation linear voltage stabilizer with low voltage difference |
| CN103838286A (en) * | 2012-11-20 | 2014-06-04 | 杨洁 | Low dropout linear regulator with quick transient response and high stability |
| CN103023324A (en) * | 2012-11-21 | 2013-04-03 | 东南大学 | Fast transient response DC-DC (direct-current to direct-current) switching converter with high load regulation rate |
| CN102999077A (en) * | 2012-12-03 | 2013-03-27 | 哈尔滨工业大学（威海） | Current leveling circuit with high linear compensation |
| CN107483172A (en) * | 2017-08-30 | 2017-12-15 | 哈尔滨工业大学（威海） | A kind of password protecting circuit for being used to defend energy consumption to attack |
| US20190097786A1 (en) * | 2018-09-24 | 2019-03-28 | Lovely Professional University | System and method for generating a symmetrically balanced output |
| CN109327206A (en) * | 2018-09-30 | 2019-02-12 | 天津大学 | Power consumption planarizes standard integrated circuit |
Non-Patent Citations (3)
| Title |
|---|
| 严迎建;许纪钧;于敬超;: "基于电流补偿电路的密码芯片抗功耗攻击设计", 计算机应用与软件, no. 01 * |
| 王晨旭;王进祥;韩志伟;喻明艳;: "一种用于DPA防御的电流平整电路设计", 华中科技大学学报(自然科学版), no. 02 * |
| 顾勇;王晨旭;周童;管旭光;罗敏;: "一种新型抗功耗分析的电流平坦化电路有效性研究", 密码学报, no. 05 * |
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