CN109327206A - Power consumption planarizes standard integrated circuit - Google Patents
Power consumption planarizes standard integrated circuit Download PDFInfo
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- CN109327206A CN109327206A CN201811160694.XA CN201811160694A CN109327206A CN 109327206 A CN109327206 A CN 109327206A CN 201811160694 A CN201811160694 A CN 201811160694A CN 109327206 A CN109327206 A CN 109327206A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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Abstract
The present invention relates to information security fields, anti-power consumption attack field, to realize that safety circuit does not have the leakage of internal information on power supply, prevent attacker obtains key from attacking by DPA.Simultaneously because having used the charging method of self-timing, reduces the risk that discharge signal is attacked, improve the protective performance of unit.For this reason, the technical scheme adopted by the present invention is that power consumption planarizes standard integrated circuit, it is made of the logic unit being sequentially connected in series, the basic structure of the logic unit is double track dynamic logic, wherein A,B,The input signal of the logic, CLK andIt is the clock control signal of the logic unit, XOR is the output signal of the logic unit.Present invention is mainly applied to information security fields, anti-power consumption attack occasion.
Description
Technical field
The present invention relates to information security fields, anti-power consumption attack field.Concretely relate to the integrated electricity of power consumption planarization standard
Road unit.
Background technique
Today's society, it is just wide for the encryption device of representative with smart card (Smart Card), usb key (USB Key) etc.
It is general to be applied to the key areas such as telecommunications, finance, pay TV, become the key component of these applications, therefore, their safety is extremely
It closes important.Although the embeddability of encryption device makes attacker that can not directly acquire the key information in crypto chip, due to
Most of crypto chips are made of cmos circuit, and in this kind of circuits, circuit can reveal certain function at work
Consumption, the sides such as electromagnetism channel information, attacker utilize differential power consumption analysis (Differential Power Analysis, DPA) skill
Art analyzes the correlation between key data and power consumption information, and is analyzed by way of mathematical statistics and can be obtained key.
The basic thought for resisting DPA attack is correlation when eliminating crypto chip work between electric current and internal data.
Wherein, since circuit-level protection focuses more on the bottom circuit structure of realization crypto chip rather than cryptographic algorithm itself, thus more
Add general.Circuit-level protection usually realizes that main design idea is that double track precharge is patrolled by design new logic unit
It collects and three stage work modes.It mainly include sense amplifier logic (Sense using the unit that double track precharge logical is realized
Amplifier Based Logic, SABL), traveling wave dynamic difference logic (Wave Dynamic Differential Logic,
WDDL), the double track precharge logical DDPL based on delay (Delay-Based Dual-Rail Pre-charge Logic) and
Differential logic LBDL (LUT Based Differential Logic) based on look-up table；It is realized using three stage work modes
Logic unit have three stage double track precharge logical TDPL (Three-phase Dual-rail Pre-charge Logic)
With three stage single track precharge logical TSPL (Three-phase Single-rail Pre-charge Logic).Wherein TDPL
Using precharge, evaluation, three stage work modes of discharging avoid influence of the output loading mismatch to unit protective performance,
So that power consumption of the logic unit within each evaluation period does not have correlation with input signal, to there is outstanding resistance
The ability of DPA attack.However due to using complicated three phase clock, requirement to clock signal and placement-and-routing are increased
Difficulty, attacker can also carry out risk of the attack to make TDPL unit have protection to fail for the discharge signal of unit.
Bibliography
1.Bucci M,Giancane L,Luzzi R,et al.Three-phase dual-rail pre-charge
logic[C]//International Conference on Cryptographic Hardware and Embedded
Systems.Springer-Verlag,2006:232-241.
2.Akkaya N E C,Erbagci B,Carley R,et al.A DPA-resistant self-timed
three-phase dual-rail pre-charge logic family[C]//IEEE International
Symposium on Hardware Oriented Security and Trust.IEEE,2015:112-117.
3.Hassoune I,Mace F,Flandre D,et al.Dynamic differential self-timed
logic families for robust and low-power security ICs[J].Integration the Vlsi
Journal,2007,40(3):355-364.
4.Menendez E,Mai K.Extended abstract:A high-performance,low-overhead,
power-analysis-resistant,single-rail logic style[C]//IEEE International
Workshop on Hardware-Oriented Security and Trust.IEEE,2008:33-36。
Summary of the invention
In order to overcome the deficiencies of the prior art, the present invention is directed to propose a kind of novel standard unit suitable for safety chip,
This kind of logic unit can make the power consumption of unit be balanced and independently of internal signal activity, utilize this kind of logic unit
The safety circuit of realization does not have the leakage of internal information on power supply, prevent attacker obtains key from attacking by DPA.
Simultaneously because having used the charging method of self-timing, reduces the risk that discharge signal is attacked, improve the protective performance of unit.For
This, the technical solution adopted by the present invention is that, power consumption planarizes standard integrated circuit, is made of the logic unit being sequentially connected in series, institute
The basic structure for stating logic unit is double track dynamic logic, wherein A,B,The input signal of the logic, CLK and
It is the clock control signal of the logic unit, XOR is the output signal of the logic unit, indicates signal A and B XOR operation
Output as a result, XNOR is also the output signal of the unit, indicate the output of signal A and B exclusive or inverse as a result, DONE signal
It is the marking signal that unitary operation is completed, DCH signal is discharge signal, is provided by the DONE signal of next stage unit.
The logic unit includes PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4,
PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, NMOS transistor N1, NMOS transistor N2, NMOS transistor
N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS crystal
Pipe N9, NMOS transistor N10, NMOS transistor N11, NMOS transistor N12 and phase inverter I1, phase inverter I2；PMOS transistor
The source electrode of P1 connects power supply, and grid meets input signal DCH, and drain electrode and the source electrode of PMOS transistor pipe P2, P3 are connected；X node with
The drain electrode of PMOS transistor P2, the grid of P3, the drain electrode of P4, the grid of P6, the drain electrode of NMOS transistor N2, the drain electrode of N5, N8
Drain electrode and phase inverter I1 input terminal it is commonly connected；The drain electrode of Y node and PMOS transistor P3, the grid of P2, the grid of P5
Pole, the grid of P7, the drain electrode of NMOS transistor N1, the drain electrode of N4, the public company of input terminal of the drain electrode and phase inverter I2 of N10
It connects；The source electrode of PMOS transistor P4, P5 connect power supply, and grid meets input signal CLK；The source electrode of PMOS transistor P6, P7 connect power supply,
Drain electrode meets output signal DONE；NMOS transistor N1 grid meets input signal A, source electrode and N2 source electrode and the public company of N3 source electrode
It connects；NMOS transistor N2 grid and N4 grid connect input signalNMOS transistor N4 source electrode and N5 source electrode and N6 drain electrode are public
It is connected；NMOS transistor N5 grid meets input signal A；NMOS transistor N3 grid meets input signal B, and source electrode drains public with N7
Connection；NMOS transistor N6 grid connects input signalSource electrode drains commonly connected with N7；NMOS transistor N7 grid connects input
Signal CLK, source electrode ground connection；NMOS transistor N8 grid meets input signal DCH, and source electrode connects N9 drain electrode；NMOS transistor N9 grid
Connect input signal CLK, source electrode ground connection；NMOS transistor N10 grid meets input signal DCH, and source electrode connects N11 drain electrode；NMOS crystal
Pipe N11 grid connects input signal CLK, source electrode ground connection；NMOS transistor N12 drain electrode meets output signal DONE, and grid connects input letter
NumberSource electrode ground connection.
The operating mode of the unit is divided into precharge, three working stages of evaluation and electric discharge, specifically, when clock is low
When level, unit is in pre-charging stage, at this time PMOS tube P4 and P5 conducting, so that nodes X, Y is precharged to high potential, together
When signal by two inverter transfers to output end so that element output signal XOR and XNOR is low potential at this time；NMOS
Pipe N12 conducting, so that marking signal DONE is pulled down to low potential；Due to the DONE signal that DCH signal is next stage unit, institute
Using in pre-charging stage DCH signal as low potential so that P1 pipe be connected；NMOS tube N7 shutdown, so that the pulldown network of unit is closed
It is disconnected, it will not be since the input of double track complementary signal be so that internal node discharges；NMOS tube N9, N11 shutdown, so that nodes X, Y is protected
High potential is held without being pulled low.
When clock is high level, unit enters the evaluation stage, at this time PMOS tube P4, P5 shutdown, so that nodes X, Y and electricity
Source disconnects, and will not be pulled up to high potential；The pulldown network of unit according to double track complementary signal A andB withInput control
The on-off of NMOS tube N1, N2, N3, N4, N5, N6 pipe a, so that electricity in a wherein drop-down channel conductive, nodes X and node Y
Position is pulled low, and is transferred to output end by phase inverter.
When the one of node of X and Y is pulled down to low potential, one of conducting in PMOS tube P6 at this time, P7, mark
Will signal DONE is pulled up to high potential, indicates the completion in evaluation stage, into discharge regime；DCH signal is next stage list
The DONE signal of member, after the completion of the evaluation of next stage, DCH becomes high potential, so that PMOS tube P1 is turned off, prevents power supply internal
The charging of portion's node；Simultaneously because NMOS tube N8, N9, N10, N11 conducting, so that nodes X, Y is pulled down to low potential, is transmitted to
Output end, so that output signal XOR and XNOR are high potential.
The features of the present invention and beneficial effect are:
By the novel standard block of design, power consumption difference of the logic unit under the input of operation unlike signal is eliminated,
So that within each period, unit internal node all can evaluation and discharge operation again, ensure that the anti-DPA attack of unit
Ability.The characteristics of being exported simultaneously using double track precharge logical, is devised independently of the discharge signal generation circuit except clock,
Avoiding attacker leads to the risk of protection failure by separating discharge signal or slowing down clock.
Detailed description of the invention:
Fig. 1 ST-TDPL logic XOR/XNOR element circuit figure.
Fig. 2 ST-TDPL unit concatenating logic structure chart.
Specific embodiment
To solve the problems of the prior art, the present invention is based on three stage double track precharge logicals to propose a kind of self-timing
Three stage double track precharge logical units (ST-TDPL), the unit be used only a clock signal, but still remain for three stages
Operating mode, reduces the complexity of unit on the basis of realizing that power consumption is unrelated with internal signal, while improving unit
Security performance.
For the anti-DPA attacking ability for improving unit, a kind of novel three stage of self-timing double track precharge logical is proposed
Structure (ST-TDPL).The cellular construction and working principle of the standard block are introduced below with reference to Fig. 1 and Fig. 2.The logic unit
Basic structure is double track dynamic logic, and Fig. 1 is the circuit diagram of the XOR/XNOR unit of a ST-TDPL structure, wherein A,B,
The input signal of unit, CLK andIt is the clock control signal of unit, XOR is the output signal of the unit, indicates signal
The output of A and B XOR operation indicates the output of signal A and B exclusive or inverse as a result, XNOR is also the output signal of the unit
As a result, DONE signal is the marking signal that unitary operation is completed, DCH signal is discharge signal, is believed by the DONE of next stage unit
Number provide.
The logic unit includes PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4,
PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, NMOS transistor N1, NMOS transistor N2, NMOS transistor
N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS crystal
Pipe N9, NMOS transistor N10, NMOS transistor N11, NMOS transistor N12 and phase inverter I1, phase inverter I2；PMOS transistor
The source electrode of P1 connects power supply, and grid meets input signal DCH, and drain electrode and the source electrode of PMOS transistor pipe P2, P3 are connected；X node with
The drain electrode of PMOS transistor P2, the grid of P3, the drain electrode of P4, the grid of P6, the drain electrode of NMOS transistor N2, the drain electrode of N5, N8
Drain electrode and phase inverter I1 input terminal it is commonly connected；The drain electrode of Y node and PMOS transistor P3, the grid of P2, the grid of P5
Pole, the grid of P7, the drain electrode of NMOS transistor N1, the drain electrode of N4, the public company of input terminal of the drain electrode and phase inverter I2 of N10
It connects；The source electrode of PMOS transistor P4, P5 connect power supply, and grid meets input signal CLK；The source electrode of PMOS transistor P6, P7 connect power supply,
Drain electrode meets output signal DONE；NMOS transistor N1 grid meets input signal A, source electrode and N2 source electrode and the public company of N3 source electrode
It connects；NMOS transistor N2 grid and N4 grid connect input signalNMOS transistor N4 source electrode and N5 source electrode and N6 drain electrode are public
It is connected；NMOS transistor N5 grid meets input signal A；NMOS transistor N3 grid meets input signal B, and source electrode and N7 drain, public
Connection altogether；NMOS transistor N6 grid connects input signalSource electrode drains commonly connected with N7；NMOS transistor N7 grid connects defeated
Enter signal CLK, source electrode ground connection；NMOS transistor N8 grid meets input signal DCH, and source electrode connects N9 drain electrode；NMOS transistor N9 grid
Pole connects input signal CLK, source electrode ground connection；NMOS transistor N10 grid meets input signal DCH, and source electrode connects N11 drain electrode；NMOS is brilliant
Body pipe N11 grid connects input signal CLK, source electrode ground connection；NMOS transistor N12 drain electrode meets output signal DONE, and grid connects input
SignalSource electrode ground connection.
The operating mode of the standard block is divided into precharge, three working stages of evaluation and electric discharge.Three are made a concrete analysis of below
The working condition of a stage lower unit.
When clock is low level, unit is in pre-charging stage, at this time PMOS tube P4 and P5 conducting, so that nodes X, Y
Be precharged to high potential, synchronous signal by two inverter transfers to output end so that at this time element output signal XOR with
XNOR is low potential；NMOS tube N12 conducting, so that marking signal DONE is pulled down to low potential；Since DCH signal is next
The DONE signal of grade unit, so being low potential in pre-charging stage DCH signal, so that P1 pipe is connected；NMOS tube N7 shutdown, makes
The pulldown network shutdown of unit is obtained, it will not be since the input of double track complementary signal be so that internal node discharges；NMOS tube N9, N11
Shutdown, so that nodes X, Y keeps high potential without being pulled low.
When clock is high level, unit enters the evaluation stage, at this time PMOS tube P4, P5 shutdown, so that nodes X, Y and electricity
Source disconnects, and will not be pulled up to high potential；The pulldown network of unit according to double track complementary signal A andB withInput control
The on-off of NMOS tube N1, N2, N3, N4, N5, N6 pipe a, so that electricity in a wherein drop-down channel conductive, nodes X and node Y
Position is pulled low, and is transferred to output end by phase inverter.
When the one of node of X and Y is pulled down to low potential, one of conducting in PMOS tube P6 at this time, P7, mark
Will signal DONE is pulled up to high potential, indicates the completion in evaluation stage, into discharge regime；DCH signal is next stage list
The DONE signal of member, after the completion of the evaluation of next stage, DCH becomes high potential, so that PMOS tube P1 is turned off, prevents power supply internal
The charging of portion's node；Simultaneously because NMOS tube N8, N9, N10, N11 conducting, so that nodes X, Y is pulled down to low potential, is transmitted to
Output end, so that output signal XOR and XNOR are high potential.
In this unit, phase inverter has primarily served two effects: first is that making double track output be low in pre-charging stage
Current potential, ensure that the domino structure connection of unit, and make double track output be high potential in discharge regime, so that next stage
NMOS tube in NMOS pulldown network all turns on, and ensure that the complete electric discharge in all internal nodes of discharge regime；Second is that electric
Flat to repair, there is the incomplete problem of signal in transmission process in signal in order to prevent, and it is anti-to joined level-one in double track output end
Phase device.
PMOS tube P2, P3 play the role of latching current potential in this configuration: in the evaluation stage, when in nodes X and node Y
One of them when being discharged to low potential, the PMOS tube conducting that it can be made to control, so that another node in the two be made to connect
It is connected to power supply, guarantees the holding of evaluation stage current potential.
This unit realizes that the function of self-timing is realized by PMOS tube P6, P7 and NMOS tube N12.When clock is low electricity
Usually, NMOS tube N12 clock is connected, so that DONE signal is " 0 " always, and after the completion of clock is high level and evaluation, section
One becomes low potential in point X and node Y, so that one in PMOS tube P6, P7 is connected, DONE signal is drawn high high electricity
Position, to generate evaluating completion signal.Fig. 2 is multiple concatenated logical constructions of ST-TDPL unit, and wherein IN signal is unit fortune
Positive input signal when calculation, i.e. A in Fig. 1, B signal；Complementary input signal when signal is unitary operation, i.e. in Fig. 1
'sSignal.
Evaluating completion signal is unrelated with clock, but fully takes into account double rail logic when evaluation is completed, two output letters
The characteristics of must to have one in number be low potential, to devise the generation circuit of evaluating completion signal using this feature.Just
Because discharge signal is generated by clock generator, attacker cannot discharge regime by discharge signal separate or
It eliminates.Attacker cannot obtain the discharge information of discharge regime, while within each period, unit internal node all can be once
Evaluation and discharge operation, thus ST-TDPL shows good power consumption harmony.
When building ST-TDPL logic unit, it should consider the anti-DPA attack performance of unit, guarantee the face of unit again
Product consumption.In Fig. 1, when designing NMOS pulldown network, it should be noted that guarantee the symmetry of pulldown network, guarantee varying input signal
The discharge scenario of lower unit internal node is identical, and when designing discharge signal generation circuit, then to use as few as possible patrol
Unit is collected, has only used 3 metal-oxide-semiconductors in Fig. 1.Protection scope of the present invention is not limited with above embodiment, and this field is general
Logical technical staff equivalent modification or variation made by disclosure according to the present invention, should all be included in protection scope.
Claims (5)
1. a kind of power consumption planarizes standard integrated circuit, characterized in that be made of the logic unit being sequentially connected in series, the logic list
The basic structure of member is double track dynamic logic, wherein A,B,The input signal of the logic, CLK andIt is described patrol
The clock control signal of unit is collected, XOR is the output signal of the logic unit, indicates the output knot of signal A and B XOR operation
Fruit, XNOR are also the output signal of the unit, indicate the output of signal A and B exclusive or inverse as a result, DONE signal is unit fortune
The marking signal completed is calculated, DCH signal is discharge signal, is provided by the DONE signal of next stage unit.
2. power consumption as described in claim 1 planarizes standard integrated circuit, characterized in that the logic unit includes PMOS crystalline substance
Body pipe P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS
Transistor P7, NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5,
NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS transistor N9, NMOS transistor N10, NMOS transistor
N11, NMOS transistor N12 and phase inverter I1, phase inverter I2；The source electrode of PMOS transistor P1 connects power supply, and grid connects input signal
The source electrode of DCH, drain electrode and PMOS transistor pipe P2, P3 are connected；The drain electrode of X node and PMOS transistor P2, the grid of P3, P4's
Drain electrode, the grid of P6, the drain electrode of NMOS transistor N2, the drain electrode of N5, the public company of input terminal of the drain electrode and phase inverter I1 of N8
It connects；The drain electrode of Y node and PMOS transistor P3, the grid of P2, the grid of P5, the grid of P7, the drain electrode of NMOS transistor N1, N4
Drain electrode, the drain electrode of N10 and the input terminal of phase inverter I2 are commonly connected；The source electrode of PMOS transistor P4, P5 connect power supply, grid
Meet input signal CLK；The source electrode of PMOS transistor P6, P7 connect power supply, and drain electrode meets output signal DONE；NMOS transistor N1 grid
Input signal A is met, source electrode and N2 source electrode and N3 source electrode are commonly connected；NMOS transistor N2 grid and N4 grid connect input signalNMOS transistor N4 source electrode drains public be connected with N5 source electrode and N6；NMOS transistor N5 grid meets input signal A；NMOS
Transistor N3 grid meets input signal B, and source electrode drains commonly connected with N7；NMOS transistor N6 grid connects input signalSource electrode
It drains with N7 commonly connected；NMOS transistor N7 grid connects input signal CLK, source electrode ground connection；NMOS transistor N8 grid connects defeated
Enter signal DCH, source electrode connects N9 drain electrode；NMOS transistor N9 grid connects input signal CLK, source electrode ground connection；NMOS transistor N10 grid
Pole meets input signal DCH, and source electrode connects N11 drain electrode；NMOS transistor N11 grid connects input signal CLK, source electrode ground connection；NMOS is brilliant
Body pipe N12 drain electrode meets output signal DONE, and grid connects input signalSource electrode ground connection.
3. power consumption as described in claim 1 planarizes standard integrated circuit, characterized in that the operating mode of the unit is divided into
Precharge, three working stages of evaluation and electric discharge, specifically, when clock is low level, unit is in pre-charging stage, at this time
PMOS tube P4 and P5 conducting, so that nodes X, Y is precharged to high potential, and synchronous signal is by two inverter transfers to output
End, so that element output signal XOR and XNOR is low potential at this time；NMOS tube N12 conducting, so that marking signal DONE is drawn
As low as low potential；Due to the DONE signal that DCH signal is next stage unit, so be low potential in pre-charging stage DCH signal,
So that P1 pipe is connected；NMOS tube N7 shutdown, so that the pulldown network of unit turns off, will not be made due to the input of double track complementary signal
Obtain internal node electric discharge；NMOS tube N9, N11 shutdown, so that nodes X, Y keeps high potential without being pulled low.
4. power consumption as described in claim 1 planarizes standard integrated circuit, characterized in that when clock is high level, unit
Into the evaluation stage, PMOS tube P4, P5 shutdown will not be pulled up to high potential so that nodes X, Y and power supply disconnect at this time；It is single
The pulldown network of member according to double track complementary signal A andB withInput control NMOS tube N1, N2, N3, N4, N5, N6 pipe it is logical
It is disconnected, so that a current potential is pulled low in a wherein drop-down channel conductive, nodes X and node Y, and it is transferred to by phase inverter defeated
Outlet.
5. power consumption as described in claim 1 planarizes standard integrated circuit, characterized in that when the one of node of X and Y is drawn
When as low as low potential, one of conducting in PMOS tube P6 at this time, P7, marking signal DONE is pulled up to high potential, indicates
The completion in evaluation stage, into discharge regime；DCH signal is the DONE signal of next stage unit, when the evaluation of next stage is complete
Cheng Hou, DCH become high potential, so that PMOS tube P1 is turned off, prevent charging of the power supply to internal node；Simultaneously because NMOS tube
N8, N9, N10, N11 conducting so that nodes X, Y is pulled down to low potential, be transmitted to output end so that output signal XOR and
XNOR is high potential.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110119640A (en) * | 2019-05-22 | 2019-08-13 | 北京智芯微电子科技有限公司 | Double track precharge logical unit and its pre-charge method |
| CN110716604A (en) * | 2019-10-11 | 2020-01-21 | 哈尔滨理工大学 | Protection circuit of anti power consumption attack based on current levels technique |
| CN113346894A (en) * | 2021-06-08 | 2021-09-03 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| CN113726331A (en) * | 2021-07-22 | 2021-11-30 | 杭州师范大学 | Power consumption constancy gate circuit unit based on double-mask technology |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01204137A (en) * | 1988-02-09 | 1989-08-16 | Nec Corp | Full addition circuit |
| US6150848A (en) * | 1997-11-10 | 2000-11-21 | The United States Of America As Represented By The Secretary Of The Navy | Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication |
| CN1471668A (en) * | 2000-10-23 | 2004-01-28 | ŦԼ�и��ױ��Ǵ�ѧ�йܻ� | Asynchronous pipeline with latch controllers |
| CN102684679A (en) * | 2012-06-05 | 2012-09-19 | 北京大学 | Delay-based dual-rail precharge logic output converter |
| CN102684677A (en) * | 2012-06-01 | 2012-09-19 | 北京大学 | Delay-based dual-rail precharge logic input converter |
| CN102857217A (en) * | 2012-09-11 | 2013-01-02 | 宁波大学 | Low-power-consumption xor/xnor gate circuit |
| CN104333362A (en) * | 2014-09-16 | 2015-02-04 | 哈尔滨工业大学（威海） | XNOR-XOR double-rail pre-charge logic unit |
| CN104378103A (en) * | 2014-09-16 | 2015-02-25 | 哈尔滨工业大学（威海） | Dual-track precharge logic unit structure |
| CN104467815A (en) * | 2014-12-05 | 2015-03-25 | 北京大学 | Double-track pre-charge logic P type full adder circuit based on time delay and double-track pre-charge logic N type full adder circuit based on time delay |
| CN104682950A (en) * | 2014-12-05 | 2015-06-03 | 北京大学 | Time delay-based double-track pre-charge logic NAND gate circuit and Time delay-based double-track pre-charge logic exclusive or gate circuit |
| CN105720970A (en) * | 2016-01-22 | 2016-06-29 | 宁波大学 | XOR/XNOR gate circuit based on FinFET devices |
| WO2017177243A1 (en) * | 2016-04-14 | 2017-10-19 | Metadat It-Beratungs- Und Entwicklungs-Gmbh | Code generator |
-
2018
- 2018-09-30 CN CN201811160694.XA patent/CN109327206B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01204137A (en) * | 1988-02-09 | 1989-08-16 | Nec Corp | Full addition circuit |
| US6150848A (en) * | 1997-11-10 | 2000-11-21 | The United States Of America As Represented By The Secretary Of The Navy | Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication |
| CN1471668A (en) * | 2000-10-23 | 2004-01-28 | ŦԼ�и��ױ��Ǵ�ѧ�йܻ� | Asynchronous pipeline with latch controllers |
| CN102684677A (en) * | 2012-06-01 | 2012-09-19 | 北京大学 | Delay-based dual-rail precharge logic input converter |
| CN102684679A (en) * | 2012-06-05 | 2012-09-19 | 北京大学 | Delay-based dual-rail precharge logic output converter |
| CN102857217A (en) * | 2012-09-11 | 2013-01-02 | 宁波大学 | Low-power-consumption xor/xnor gate circuit |
| CN104333362A (en) * | 2014-09-16 | 2015-02-04 | 哈尔滨工业大学（威海） | XNOR-XOR double-rail pre-charge logic unit |
| CN104378103A (en) * | 2014-09-16 | 2015-02-25 | 哈尔滨工业大学（威海） | Dual-track precharge logic unit structure |
| CN104467815A (en) * | 2014-12-05 | 2015-03-25 | 北京大学 | Double-track pre-charge logic P type full adder circuit based on time delay and double-track pre-charge logic N type full adder circuit based on time delay |
| CN104682950A (en) * | 2014-12-05 | 2015-06-03 | 北京大学 | Time delay-based double-track pre-charge logic NAND gate circuit and Time delay-based double-track pre-charge logic exclusive or gate circuit |
| CN105720970A (en) * | 2016-01-22 | 2016-06-29 | 宁波大学 | XOR/XNOR gate circuit based on FinFET devices |
| WO2017177243A1 (en) * | 2016-04-14 | 2017-10-19 | Metadat It-Beratungs- Und Entwicklungs-Gmbh | Code generator |
Non-Patent Citations (1)
| Title |
|---|
| 周可基 等: "Design of power balance SRAM for DPA-resistance", 《JOURNAL OF SEMICONDUCTORS》 * |
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