CN104333362A - XNOR-XOR double-rail pre-charge logic unit - Google Patents
XNOR-XOR double-rail pre-charge logic unit Download PDFInfo
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- CN104333362A CN104333362A CN201410470485.0A CN201410470485A CN104333362A CN 104333362 A CN104333362 A CN 104333362A CN 201410470485 A CN201410470485 A CN 201410470485A CN 104333362 A CN104333362 A CN 104333362A
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- nmos tube
- pmos
- input signal
- drain electrode
- xor
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Abstract
The invention relates to an XNOR-XOR double-rail pre-charge logic unit and belongs to the field of circuit electronics. The XNOR-XOR double-rail pre-charge logic unit comprises a single-rail XOR logic circuit and a single-rail XNOR logic circuit complementing the single-rail XOR logic circuit. The two circuits are each provided with four input ends respectively connected with four input signals a, a<->, b and b<->; the output signal y of the single-rail XOR logic circuit is an XOR logic result of the input signals a and b; and the output signal y<-> of the single-rail XNOR logic circuit is an XNOR logic result of the input signals a and b. According to the invention, under the condition of not large area expenditure, power consumption of nodes inside a logic unit can be effectively balanced, the memory effect of the internal nodes is eliminated, the problem of early spreading effect of the XNOR-XOR double-rail pre-charge logic unit is effectively solved, and safe and effective XNOR-XOR logic is realized.
Description
Technical field
The present invention relates to logical unit structure, for resisting the Differential power attack analysis of crypto chip, belonging to electric circuit electronics technical field.
Background technology
The encryption devices such as smart card are able to extensive use in the various industry departments such as telecommunications, finance, enterprise security and government, and the importance of its safety is self-evident.Although the embedded characteristic of encryption device makes assailant directly cannot contact key information in crypto chip, but the side channel informations such as certain power consumption, electromagnetic radiation can be leaked during crypto chip work, differential power consumption analysis (Differential Power Analysis, DPA) attack technology utilizes the correlation between key data and these information, can be analyzed the value drawing key by modes such as mathematical statistics.The noninvasive attacked due to DPA, universality and the feature such as simple, it causes serious threat to the fail safe of the crypto chips such as smart card.Opposing DPA attacks the correlation of the data used when the most basic thought is operating current and its execution algorithm eliminating crypto chip.
Circuit-level protection is independent of concrete cryptographic algorithm, and therefore circuit-level protection is an important research direction of anti-power consumption attack, if can propose a kind of effective circuit structure, the safety problem of various cryptographic algorithm is just readily solved.DRP logic is that circuit-level protects most important branch, but propagation effect causes more serious security threat to DRP logic in advance, although the solution being eliminated propagation effect in advance by the mode adding lock unit is effective, but also bring great area overhead thus, therefore, how when area is paid wages little, effectively solve propagation effect in advance and remain the topic that researcher pays special attention to.
Summary of the invention
Technical problem to be solved by this invention overcomes above-mentioned the deficiencies in the prior art, there is provided a kind of can the power consumption of balanced logic unit internal node effectively, eliminate the memory effect of internal node, efficiently solve the XOR-XNOR double track precharge logical unit of the impact of propagation effect in advance.
The technical scheme that the present invention solves the problems of the technologies described above employing is: a kind of XOR-XNOR double track precharge logical unit, based on differential transfer pipe logical circuit, be made up of two single track circuit, be respectively single track with or logic circuitry portions and single track XOR circuit part, two parts circuit has the symmetry of height, ensure that the balance of power consumption;
Described single track XOR circuit part, is made up of NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4 and PMOS P1, PMOS P2, PMOS P3, PMOS P4 and inverter I1;
Wherein NMOS tube N1 source electrode connects input signal
a, grid connects input signal
b; NMOS tube N2 source electrode connects input signal
, grid connects input signal
; The drain electrode short circuit of NMOS tube N1 and NMOS tube N2 simultaneously;
PMOS P1 connects with PMOS P2, and wherein the source electrode of PMOS P1 connects power supply
v dD, grid connects input signal
b, the source shorted of drain electrode and PMOS P2, the grid of PMOS P2 connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N1 and NMOS tube N2;
NMOS tube N3 grid connects input signal
, NMOS tube N4 grid connects input signal
a; The source shorted of NMOS tube N3 and NMOS tube N4, and with the drain electrode short circuit of NMOS tube N1 and NMOS tube N2; The drain electrode short circuit of NMOS tube N3 and NMOS tube N4;
PMOS P3 connects with PMOS P4, and wherein the source electrode of PMOS P3 connects power supply
v dD, grid connects input signal
a, the source shorted of drain electrode and PMOS P4, the grid of PMOS P4 connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N3 and NMOS tube N4;
The drain electrode of NMOS tube N3 and NMOS tube N4 is input to inverter I1, and the output of inverter I1 is output signal
y(XOR);
Described single track with or logic circuitry portions, be made up of NMOS tube N1 ', NMOS tube N2 ', NMOS tube N3 ', NMOS tube N4 ' and PMOS P1 ', PMOS P2 ', PMOS P3 ', PMOS P4 ' and inverter I1 ';
Wherein NMOS tube N1 ' source electrode connects input signal
, grid connects input signal
b; NMOS tube N2 ' source electrode connects input signal
a, grid connects input signal
; The drain electrode short circuit of NMOS tube N1 ' and NMOS tube N2 ' simultaneously;
PMOS P1 ' connects with PMOS P2 ', and wherein the source electrode of PMOS P1 ' connects power supply
v dD, grid connects input signal
b, the source shorted of drain electrode and PMOS P2 ', the grid of PMOS P2 ' connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N1 ' and NMOS tube N2 ';
NMOS tube N3 ' grid connects input signal
, NMOS tube N4 ' grid connects input signal
a; The source shorted of NMOS tube N3 ' and NMOS tube N4 ', and with the drain electrode short circuit of NMOS tube N1 ' and NMOS tube N2 '; The drain electrode short circuit of NMOS tube N3 ' and NMOS tube N4 ';
PMOS P3 ' connects with PMOS P4 ', and wherein the source electrode of PMOS P3 ' connects power supply
v dD, grid connects input signal
a, the source shorted of drain electrode and PMOS P4 ', the grid of PMOS P4 ' connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N3 ' and NMOS tube N4 ';
The drain electrode of NMOS tube N3 ' and NMOS tube N4 ' is input to inverter I1 ', and the output of inverter I1 ' is output signal
(XNOR).
The present invention is based on differential transfer pipe logical circuit, less metal-oxide-semiconductor is used to achieve XOR-XNOR double track precharge logical unit, the logic unit circuit proposed has the symmetry of height, under preliminary filling and evaluation alternation, ' 0 ' of logic unit circuit reaches balance with the upset of ' 1 ', and the power consumption of unit reaches balance.Against existing technologies, the present invention can the power consumption of balanced logic unit internal node effectively, eliminates the memory effect of internal node, efficiently solves the impact of propagation effect in advance.
Accompanying drawing explanation
Fig. 1 is that the present invention forms structured flowchart.
Fig. 2 is single track XOR circuit part composition connection diagram in the present invention.
Fig. 3 be in the present invention single track with or logic circuit unit be grouped into connection diagram.
Embodiment
As can be seen from Fig. 1, Fig. 2 and Fig. 3, a kind of XOR-XNOR double track of the present invention precharge logical unit, comprise single track with or circuit part and single track XOR circuit part.
Described single track XOR circuit part, is made up of NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4 and PMOS P1, PMOS P2, PMOS P3, PMOS P4 and inverter I1.
NMOS tube N1 source electrode connects input signal
a, grid connects input signal
b; NMOS tube N2 source electrode connects input signal
, grid connects input signal
; The drain electrode short circuit of NMOS tube N1 and NMOS tube N2 simultaneously.
PMOS P1 connects with PMOS P2, and wherein the source electrode of PMOS P1 connects power supply
v dD, grid connects input signal
b, the source shorted of drain electrode and PMOS P2, the grid of PMOS P2 connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N1 and NMOS tube N2.
NMOS tube N3 grid connects input signal
, NMOS tube N4 grid connects input signal
a; The source shorted of NMOS tube N3 and NMOS tube N4, and with the drain electrode short circuit of NMOS tube N1 and NMOS tube N2; The drain electrode short circuit of NMOS tube N3 and NMOS tube N4.
PMOS P3 connects with PMOS P4, and wherein the source electrode of PMOS P3 connects power supply
v dD, grid connects input signal
a, the source shorted of drain electrode and PMOS P4, the grid of PMOS P4 connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N3 and NMOS tube N4.
The drain electrode of NMOS tube N3 and NMOS tube N4 is input to inverter I1, and the output of inverter I1 is output signal
y(XOR).
Described single track with or logic circuitry portions, be made up of NMOS tube N1 ', NMOS tube N2 ', NMOS tube N3 ', NMOS tube N4 ' and PMOS P1 ', PMOS P2 ', PMOS P3 ', PMOS P4 ' and inverter I1 '.
NMOS tube N1 ' source electrode connects input signal
, grid connects input signal
b; NMOS tube N2 ' source electrode connects input signal
a, grid connects input signal
; The drain electrode short circuit of NMOS tube N1 ' and NMOS tube N2 ' simultaneously.
PMOS P1 ' connects with PMOS P2 ', and wherein the source electrode of PMOS P1 ' connects power supply
v dD, grid connects input signal
b, the source shorted of drain electrode and PMOS P2 ', the grid of PMOS P2 ' connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N1 ' and NMOS tube N2 '.
NMOS tube N3 ' grid connects input signal
, NMOS tube N4 ' grid connects input signal
a; The source shorted of NMOS tube N3 ' and NMOS tube N4 ', and with the drain electrode short circuit of NMOS tube N1 ' and NMOS tube N2 '; The drain electrode short circuit of NMOS tube N3 ' and NMOS tube N4 '.
PMOS P3 ' connects with PMOS P4 ', and wherein the source electrode of PMOS P3 ' connects power supply
v dD, grid connects input signal
a, the source shorted of drain electrode and PMOS P4 ', the grid of PMOS P4 ' connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N3 ' and NMOS tube N4 '.
The drain electrode of NMOS tube N3 ' and NMOS tube N4 ' is input to inverter I1 ', and the output of inverter I1 ' is output signal
(XNOR).
Below in conjunction with Fig. 2 and 3, the circuit function in the present invention is described.In the preliminary filling cycle, the present invention's four input signals are ' 0 ', and now NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4 and NMOS tube N1 ', NMOS tube N2 ', NMOS tube N3 ', NMOS tube N4 ' are all turned off; And PMOS P1, PMOS P2, PMOS P3, PMOS P4 and PMOS P1 ', PMOS P2 ', PMOS P3 ', PMOS P4 ' all open, internal node n1, n2, nb1, nb2 are all charged to ' 1 ', due to inverter I1, I1 ' effect, two outputs all export ' 0 '.
In the evaluation cycle, input signal
awith
complementation, input signal
bwith
complementation, PMOS P1 and PMOS P2 is turned off one of them, and node n1 and power supply disconnect, PMOS P3 and PMOS P4 is turned off one of them, node n2 and power supply disconnect, and PMOS P1 ' and PMOS P2 ' are turned off one of them, and node nb1 and power supply disconnect, PMOS P3 ' and PMOS P4 ' are turned off one of them, node nb2 and power supply disconnect, and namely in the evaluation cycle, node n1, n2, nb1, nb2 all disconnect with power supply, stop charging, and according to input signal
a,
,
b,
realize evaluation function, output
yexport
a,
bxOR result, output
export
a,
bsame or result.
Illustrate that the XOR-XNOR logic unit circuit that the present invention proposes is eliminating the effect shifted to an earlier date in propagation effect below in conjunction with Fig. 2 and Fig. 3.When logic unit circuit is the preliminary filling cycle by evaluation periodic conversion, if input signal
a,
preliminary filling signal arrive in advance, namely
a,
become ' 0 ' in advance, for single track XOR circuit part, NMOS tube N3 and NMOS tube N4 turns off, and PMOS P3, PMOS P4 open simultaneously, and power supply starts to charge to node n2,
yexport and supplement ' 0 ' in advance with money, in like manner, now or logic circuitry portions same for single track, NMOS tube N3 ' and NMOS tube N4 ' turns off, and PMOS P3 ', PMOS P4 ' open simultaneously, and power supply starts to charge to node nb2,
export and supplement ' 0 ' in advance with money.
If input signal
b,
preliminary filling signal arrive in advance, namely
b,
become ' 0 ' in advance, for single track XOR circuit part, NMOS tube N1 and NMOS tube N2 turns off, and PMOS P1, PMOS P2 open simultaneously, and power supply starts to charge to node n1, now
a,
preliminary filling signal also do not arrive, one of them of NMOS tube N3 and NMOS tube N4 is in unlatching,
yexport and supplement ' 0 ' in advance with money, in like manner, now or logic circuitry portions same for single track, NMOS tube N1 ' and NMOS tube N2 ' turns off, and PMOS P1 ', PMOS P2 ' open simultaneously, and power supply starts to charge to node nb1, now
a,
preliminary filling signal also do not arrive, one of them of NMOS tube N3 ' and NMOS tube N4 ' is in unlatching,
export and supplement ' 0 ' in advance with money, logic unit circuit realizes preliminary filling.
Therefore, input signal
a,
with
b,
one group of preliminary filling signal wherein arrives, and logic unit circuit just starts to carry out preliminary filling, output
y,
export and supplement with money in advance.
When logic unit circuit is the evaluation cycle by preliminary filling periodic conversion, if input signal
a,
evaluation signal arrive in advance, namely
a,
become complementary in advance, now
b,
also remain preliminary filling signal, namely
b,
be all ' 0 ', now NMOS tube N1 and NMOS tube N2 and NMOS tube N1 ' and NMOS tube N2 ' are all in off state, and PMOS P1 and PMOS P2 and PMOS P1 ' and PMOS P2 ' are still held open, two outputs
y,
output valve remains supplements ' 0 ' in advance with money, and now logic unit circuit still keeps precharging state, by the time input signal
b,
when evaluation signal arrives, as described in embodiment two, circuit carries out evaluation.
If input signal
b,
evaluation signal arrive in advance, namely
b,
become complementary in advance, now
a,
also remain preliminary filling signal, namely
a,
be all ' 0 ', now NMOS tube N3 and NMOS tube N4 and NMOS tube N3 ' and NMOS tube N4 ' are all in off state, and PMOS P3 and PMOS P4 and PMOS P3 ' and PMOS P4 ' are still held open, two outputs
y,
output valve remains supplements ' 0 ' in advance with money, and now logic unit circuit still keeps precharging state, by the time input signal
a,
when evaluation signal arrives, by aforementioned, evaluation is carried out to circuit.
Therefore, only have and work as input signal
a,
with
b,
evaluation signal when all arriving, logic unit circuit just starts to carry out evaluation.
The present invention can the power consumption of balanced logic unit internal node effectively, eliminates the memory effect of internal node, efficiently solves the impact of propagation effect in advance.
Claims (1)
1. an XOR-XNOR double track precharge logical unit, is characterized in that: its by single track with or logic circuitry portions and single track or logic circuit unit is grouped into;
Described single track XOR circuit part, is made up of NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4 and PMOS P1, PMOS P2, PMOS P3, PMOS P4 and inverter I1;
Wherein NMOS tube N1 source electrode connects input signal
a, grid connects input signal
b; NMOS tube N2 source electrode connects input signal
, grid connects input signal
; The drain electrode short circuit of NMOS tube N1 and NMOS tube N2 simultaneously;
PMOS P1 connects with PMOS P2, and wherein the source electrode of PMOS P1 connects power supply
v dD, grid connects input signal
b, the source shorted of drain electrode and PMOS P2, the grid of PMOS P2 connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N1 and NMOS tube N2;
NMOS tube N3 grid connects input signal
, NMOS tube N4 grid connects input signal
a; The source shorted of NMOS tube N3 and NMOS tube N4, and with the drain electrode short circuit of NMOS tube N1 and NMOS tube N2; The drain electrode short circuit of NMOS tube N3 and NMOS tube N4;
PMOS P3 connects with PMOS P4, and wherein the source electrode of PMOS P3 connects power supply
v dD, grid connects input signal
a, the source shorted of drain electrode and PMOS P4, the grid of PMOS P4 connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N3 and NMOS tube N4;
The drain electrode of NMOS tube N3 and NMOS tube N4 is input to inverter I1, and the output of inverter I1 is output signal
y(XOR);
Described single track with or logic circuitry portions, be made up of NMOS tube N1 ', NMOS tube N2 ', NMOS tube N3 ', NMOS tube N4 ' and PMOS P1 ', PMOS P2 ', PMOS P3 ', PMOS P4 ' and inverter I1 ';
Wherein NMOS tube N1 ' source electrode connects input signal
, grid connects input signal
b; NMOS tube N2 ' source electrode connects input signal
a, grid connects input signal
; The drain electrode short circuit of NMOS tube N1 ' and NMOS tube N2 ' simultaneously;
PMOS P1 ' connects with PMOS P2 ', and wherein the source electrode of PMOS P1 ' connects power supply
v dD, grid connects input signal
b, the source shorted of drain electrode and PMOS P2 ', the grid of PMOS P2 ' connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N1 ' and NMOS tube N2 ';
NMOS tube N3 ' grid connects input signal
, NMOS tube N4 ' grid connects input signal
a; The source shorted of NMOS tube N3 ' and NMOS tube N4 ', and with the drain electrode short circuit of NMOS tube N1 ' and NMOS tube N2 '; The drain electrode short circuit of NMOS tube N3 ' and NMOS tube N4 ';
PMOS P3 ' connects with PMOS P4 ', and wherein the source electrode of PMOS P3 ' connects power supply
v dD, grid connects input signal
a, the source shorted of drain electrode and PMOS P4 ', the grid of PMOS P4 ' connects input signal
, the drain electrode short circuit of drain electrode and NMOS tube N3 ' and NMOS tube N4 ';
The drain electrode of NMOS tube N3 ' and NMOS tube N4 ' is input to inverter I1 ', and the output of inverter I1 ' is output signal
(XNOR.
Priority Applications (1)
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|---|---|---|---|
| CN201410470485.0A CN104333362B (en) | 2014-09-16 | 2014-09-16 | A kind of same or XOR double track precharge logical unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410470485.0A CN104333362B (en) | 2014-09-16 | 2014-09-16 | A kind of same or XOR double track precharge logical unit |
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| CN104333362A true CN104333362A (en) | 2015-02-04 |
| CN104333362B CN104333362B (en) | 2017-07-04 |
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Cited By (3)
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| CN109327206A (en) * | 2018-09-30 | 2019-02-12 | 天津大学 | Power consumption planarizes standard integrated circuit |
| CN109546997A (en) * | 2018-11-01 | 2019-03-29 | 宁波大学 | A kind of digital comparator based on TDPL logic |
| CN112104357A (en) * | 2020-09-07 | 2020-12-18 | 杭州师范大学 | Power consumption balance type current type CMOS gate circuit unit based on double-track precharge logic |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109327206A (en) * | 2018-09-30 | 2019-02-12 | 天津大学 | Power consumption planarizes standard integrated circuit |
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| CN109546997A (en) * | 2018-11-01 | 2019-03-29 | 宁波大学 | A kind of digital comparator based on TDPL logic |
| CN109546997B (en) * | 2018-11-01 | 2022-07-15 | 宁波大学 | Numerical value comparator based on TDPL logic |
| CN112104357A (en) * | 2020-09-07 | 2020-12-18 | 杭州师范大学 | Power consumption balance type current type CMOS gate circuit unit based on double-track precharge logic |
| CN112104357B (en) * | 2020-09-07 | 2023-12-19 | 杭州师范大学 | Power consumption balance type current type CMOS gate circuit unit based on double-rail precharge logic |
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