CN102394637B - Anti-differential power attack ternary counter based on sense amplification logic - Google Patents
Anti-differential power attack ternary counter based on sense amplification logic Download PDFInfo
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- CN102394637B CN102394637B CN201110305818.0A CN201110305818A CN102394637B CN 102394637 B CN102394637 B CN 102394637B CN 201110305818 A CN201110305818 A CN 201110305818A CN 102394637 B CN102394637 B CN 102394637B
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Abstract
The invention discloses an anti-differential power attack ternary counter based on sense amplification logic, characterized by comprising a binary logic switching circuit and a sense amplification logic switching circuit, wherein the sense amplification logic switching circuit is provided with a current compensation circuit; the binary logic switching circuit is composed of a first D flip-flop, a second D flip-flop, an NAND gate and an XNOR gate; the sense amplification logic switching circuit is composed of a first PMOS (P-channel Metal Oxide Semiconductor) FET (Field Effect Transistor), a second PMOS FET, a third PMOS FET, a first NMOS (N-channel Metal Oxide Semiconductor) FET, a second NMOS FET, a third NMOS FET and a fourth NMOS FET; and a first signal output end and a second signal output end of the sense amplification logic switching circuit are connected in parallel with the current compensation circuit. The invention has the advantages that the circuit of the ternary counter has the characteristic of constant power consumption, the ternary counter has good anti-differential power attack effect, the complexity and cost of wire connection among circuits are greatly reduced, and the reliability of the circuits is improved.
Description
Technical field
The present invention relates to a kind of ternary counter, especially relate to a kind of ternary counter of the resisting differential Attacks based on sense amplification logic.
Background technology
Since the Kocher of cryptology institute of the U.S. in 1998 proposes the concept of lie attack
[1], as a hot research direction, in every field, caused widely and paid close attention to.Conventional cipher is attacked the weakness that discloses cryptographic algorithm by the method for mathematical analysis.This just requires assailant aspect cryptanalysis and cryptographic algorithm, having quite high attainments.Lie is attacked and is just used the information attack encryption chips such as some marginal information, such as, output when power consumption, time of implementation, fault and input behavior, radiation, electric power spike situation, and it does not require that assailant is proficient in cryptanalysis and cryptographic algorithm.This just causes safely very large threat to chip.Lie attack method comprises differential power attack (Differential Power Analysis, DPA)
[2], fault analysis (Fault Attacks, FA)
[3]attack (Electromagnetic Attacks, EMA) with electromagnetic wave
[4]etc..Wherein, DPA attack be one efficiently, lie attack method cheaply, the safety of crypto chip is formed to significant threat.The general principle that DPA attacks is: when chip is in the time that various computing is carried out in the different instruction of execution, and corresponding also respective change of power consumption.By using special electronic gauge and mathematical statistics technology, these change to carry out determination and analysis, thereby obtain the specific key message in chip.This is a kind of method of utilizing the change of power consumption of instruction to analyze cryptographic algorithm and password
[5].In existing document about the circuit structure of resisting differential Attacks, such as sense amplification logic SABL (Sense Amplifier Based Logic) circuit, fluctuation state differential logic WDDL (Wave Dynamic Differential Logic) circuit etc., but the contained information density of its power hungry of these circuit and hardware circuit reduces by 50%.And MULTI-VALUED LOGIC CIRCUIT can not only increase the ability of single line carry information, improve the information density of digital circuit, and can reduce VLSI pin count, reduce complexity and cost that between circuit, wiring connects, improve the reliability of circuit.Therefore, design many-valued anti-DPA attack circuit unit and become the new research direction of scholar.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of complexity and cost that can reduce wiring connection between circuit, improves the ternary counter of the resisting differential Attacks based on sense amplification logic of the reliability of circuit.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of ternary counter of the resisting differential Attacks based on sense amplification logic, it comprises a two-valued function change-over circuit and a sense amplification logic change-over circuit, described sense amplification logic change-over circuit is provided with current compensation circuit, described two-valued function change-over circuit is by the first d type flip flop, the second d type flip flop, NAND gate and biconditional gate composition, the first input end of the first input end of the first described d type flip flop and the second described d type flip flop is connected to clock signal input terminal, the positive output end of the positive output end of the first described d type flip flop and the second described d type flip flop is connected with two inputs of described NAND gate respectively, the reversed-phase output of the reversed-phase output of the first described d type flip flop and the second described d type flip flop is connected with two inputs of described biconditional gate respectively, the second input of the first described d type flip flop is connected with the output of described NAND gate, the second input of the second described d type flip flop is connected with the positive output end of the first described d type flip flop, described sense amplification logic change-over circuit is managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe composition, the source electrode of a described PMOS pipe connects power supply, the source electrode of the source electrode of the 2nd described PMOS pipe and the 3rd described PMOS pipe is connected to the drain electrode of a described PMOS pipe, the drain electrode of the 2nd described PMOS pipe is connected with the drain electrode of the 2nd described NMOS pipe, the drain electrode of the 3rd described PMOS pipe is connected with the drain electrode of the 3rd described NMOS pipe, the source electrode of the source electrode of the 2nd described NMOS pipe and the 3rd described NMOS pipe is connected to the drain electrode of a described NMOS pipe, the source ground of a described NMOS pipe, in the drain electrode of the drain electrode of the 2nd NMOS pipe described in the 4th described NMOS pipe is connected across and the 3rd described NMOS pipe, the grid of the grid of a described PMOS pipe and the 4th described NMOS pipe is connected to inversion clock signal input part, the drain electrode of the grid of the 3rd described PMOS pipe and the 2nd described PMOS pipe is connected to first signal output, the drain electrode of the grid of the 2nd described PMOS pipe and the 3rd described PMOS pipe is connected to secondary signal output, the grid of a described NMOS pipe is connected with clock signal input terminal, the grid of the 2nd described NMOS pipe is connected with the output of described NAND gate, the grid of the 3rd described NMOS pipe is connected with the output of described biconditional gate, described first signal output and described secondary signal output are connected to described current compensation circuit.
Described current compensation circuit is managed by the 4th PMOS, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe composition, described first signal output and described secondary signal output are connected to the drain and gate of the 4th described PMOS pipe, the 4th described PMOS pipe source electrode is connected with the drain electrode of the 5th described PMOS pipe, the source electrode of the source electrode of the 5th described PMOS pipe and the 6th described PMOS pipe is connected to power supply, the drain electrode of the grid of the 6th described PMOS pipe and drain electrode and described the 5th NMOS pipe is connected to the grid of the 5th described PMOS pipe, grid and the source ground of the 5th described NMOS pipe.
Compared with prior art, the invention has the advantages that and utilize binary-coding and sense amplification logic pre-charging stage capacitive coupling characteristic, design a kind of ternary counter, the two-valued function change-over circuit that this scheme only need be used a sense amplification logic change-over circuit and corresponding conventional two-value components and parts to form just can be realized the function of ternary counter, and by a current compensation circuit is set, make the circuit of ternary counter of the present invention there is the characteristic that power consumption is constant, not only there is good resisting differential Attacks effect, and the complexity that between circuit, wiring connects and all reductions greatly of cost, improve the reliability of circuit, also the cascade of multidigit counter unit can be obtained to the ternary counter of position arbitrarily simultaneously.
Brief description of the drawings
Fig. 1 is structural representation and the circuit symbol schematic diagram of ternary counter of the present invention;
Fig. 2 is the structural representation of sense amplification logic change-over circuit of the present invention;
Fig. 3 is the structural representation of two-valued function change-over circuit of the present invention;
Fig. 4 is the structural representation of current compensation circuit of the present invention;
Fig. 5 is the structural representation of three ternary counters being made up of ternary counter of the present invention;
Fig. 6 is the computer simulation waveform schematic diagram of three ternary counters;
Fig. 7 is the schematic diagram of the current waveform of three ternary counters within a count cycle;
Fig. 8 is the power consumption waveform schematic diagram of three ternary counters.
Embodiment
Below in conjunction with accompanying drawing, embodiment is described in further detail the present invention.
As shown in Figure 1 to 4, a kind of ternary counter of the resisting differential Attacks based on sense amplification logic, it comprises a two-valued function change-over circuit 1 and a sense amplification logic change-over circuit 2, sense amplification logic change-over circuit 2 is provided with current compensation circuit 3, two-valued function change-over circuit 1 is by the first d type flip flop D1, the second d type flip flop D2, NAND gate T1 and biconditional gate T2 composition, the first input end 2D of the first input end 1D of the first d type flip flop D1 and the second d type flip flop D2 is connected to clock signal input terminal clk, the positive output end of the first d type flip flop D1 is connected with two inputs of NAND gate T1 respectively with the positive output end of the second d type flip flop D2, the reversed-phase output of the first d type flip flop D1 is connected with two inputs of biconditional gate T2 respectively with the reversed-phase output of the second d type flip flop D2, the second input 1C of the first d type flip flop D1 is connected with the output of NAND gate T1, the second input 2C of the second d type flip flop D2 is connected with the positive output end of the first d type flip flop D1, sense amplification logic change-over circuit 2 is by a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the one NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the 4th NMOS pipe N4 composition, the source electrode of the one PMOS pipe P1 connects power supply, the source electrode of the source electrode of the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 is connected to the drain electrode of a PMOS pipe P1, the drain electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 2nd NMOS pipe N2, the drain electrode of the 3rd PMOS pipe P3 is connected with the drain electrode of the 3rd NMOS pipe N3, the source electrode of the source electrode of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 is connected to the drain electrode of a NMOS pipe N1, the source ground of the one NMOS pipe N1, the 4th NMOS pipe N4 is connected across in the drain electrode of the 2nd NMOS pipe N2 and the drain electrode of the 3rd NMOS pipe N3, the grid of the grid of the one PMOS pipe P1 and the 4th NMOS pipe N4 is connected to inversion clock signal input part
the drain electrode of the grid of the 3rd PMOS pipe P3 and the 2nd PMOS pipe P2 is connected to first signal output end vo ut, the drain electrode of the grid of the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 is connected to secondary signal output CP, the grid of the one NMOS pipe N1 is connected with clock signal input terminal clk, the grid of the 2nd NMOS pipe N2 is connected with the output of NAND gate T1, the grid of the 3rd NMOS pipe N3 is connected with the output of biconditional gate T2, current compensation circuit 3 is by the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6 and the 5th NMOS pipe N5 composition, the 4th PMOS pipe P4 source electrode is connected with the drain electrode of the 5th PMOS pipe P5, the source electrode of the source electrode of the 5th PMOS pipe P5 and the 6th PMOS pipe P6 is connected to power supply, the drain electrode of the grid of the 6th PMOS pipe P6 and drain electrode and the 5th NMOS pipe N5 is connected to the grid of the 5th PMOS pipe P5, grid and the source ground of the 5th NMOS pipe N5, first signal output end vo ut and secondary signal output CP are connected to the drain and gate of the 4th PMOS pipe P4.
Fig. 5 has provided the structural representation of three ternary counters that utilize ternary counter formation of the present invention.
Under CANDANCE environment, adopt the 0.13 μ m CMOS technique of TSMC, three ternary counters are carried out to computer simulation.Fig. 6 has provided the analog waveform of three ternary counters.Clk is clock signal, V
out0, V
out1, V
out2represent respectively first, counter, second and tertiary output, output logic 0, logical one and logic 2 successively under clock control.Analog result shows that output waveform is more satisfactory, and counter has correct logic function.
Fig. 7 is the current waveforms of three ternary counters within a count cycle, and main electric current occurs on counting edge, and size of current is basic identical.
Fig. 8 is the power consumption waveform of three ternary counters, and within each clock cycle, power consumption curve is all the same, has the characteristic that power consumption is constant.
Claims (2)
1. the ternary counter of the resisting differential Attacks based on sense amplification logic, it is characterized in that it comprises a two-valued function change-over circuit and a sense amplification logic change-over circuit, described sense amplification logic change-over circuit is provided with current compensation circuit, described two-valued function change-over circuit is by the first d type flip flop, the second d type flip flop, NAND gate and biconditional gate composition, the first input end of the first input end of the first described d type flip flop and the second described d type flip flop is connected to clock signal input terminal, the positive output end of the positive output end of the first described d type flip flop and the second described d type flip flop is connected with two inputs of described NAND gate respectively, the reversed-phase output of the reversed-phase output of the first described d type flip flop and the second described d type flip flop is connected with two inputs of described biconditional gate respectively, the second input of the first described d type flip flop is connected with the output of described NAND gate, the second input of the second described d type flip flop is connected with the positive output end of the first described d type flip flop, described sense amplification logic change-over circuit is managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe composition, the source electrode of a described PMOS pipe connects power supply, the source electrode of the source electrode of the 2nd described PMOS pipe and the 3rd described PMOS pipe is connected to the drain electrode of a described PMOS pipe, the drain electrode of the 2nd described PMOS pipe is connected with the drain electrode of the 2nd described NMOS pipe, the drain electrode of the 3rd described PMOS pipe is connected with the drain electrode of the 3rd described NMOS pipe, the source electrode of the source electrode of the 2nd described NMOS pipe and the 3rd described NMOS pipe is connected to the drain electrode of a described NMOS pipe, the source ground of a described NMOS pipe, in the drain electrode of the drain electrode of the 2nd NMOS pipe described in the 4th described NMOS pipe is connected across and the 3rd described NMOS pipe, the grid of the grid of a described PMOS pipe and the 4th described NMOS pipe is connected to inversion clock signal input part, the drain electrode of the grid of the 3rd described PMOS pipe and the 2nd described PMOS pipe is connected to first signal output, the drain electrode of the grid of the 2nd described PMOS pipe and the 3rd described PMOS pipe is connected to secondary signal output, the grid of a described NMOS pipe is connected with clock signal input terminal, the grid of the 2nd described NMOS pipe is connected with the output of described NAND gate, the grid of the 3rd described NMOS pipe is connected with the output of described biconditional gate, described first signal output and described secondary signal output are connected to described current compensation circuit.
2. the ternary counter of the resisting differential Attacks based on sense amplification logic as claimed in claim 1, current compensation circuit described in it is characterized in that is managed by the 4th PMOS, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe composition, described first signal output and described secondary signal output are connected to the drain and gate of the 4th described PMOS pipe, the 4th described PMOS pipe source electrode is connected with the drain electrode of the 5th described PMOS pipe, the source electrode of the source electrode of the 5th described PMOS pipe and the 6th described PMOS pipe is connected to power supply, the drain electrode of the grid of the 6th described PMOS pipe and drain electrode and described the 5th NMOS pipe is connected to the grid of the 5th described PMOS pipe, grid and the source ground of the 5th described NMOS pipe.
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| CN102394637B true CN102394637B (en) | 2014-06-25 |
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| CN103595371B (en) * | 2013-10-25 | 2015-09-30 | 宁波大学 | A kind of Double-edge D trigger based on N-type SABL logic |
| CN107682006B (en) * | 2017-09-28 | 2020-11-10 | 宁波大学 | Three-value reversible counter using carbon nano field effect transistor |
| CN108446556B (en) * | 2018-03-01 | 2020-04-07 | 北京智芯微电子科技有限公司 | Power consumption resisting analysis circuit and method for cryptographic chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777139A (en) * | 2009-12-30 | 2010-07-14 | 宁波大学 | Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter |
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| JP2000090668A (en) * | 1998-09-07 | 2000-03-31 | Texas Instr Inc <Ti> | Semiconductor memory circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777139A (en) * | 2009-12-30 | 2010-07-14 | 宁波大学 | Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter |
Non-Patent Citations (5)
| Title |
|---|
| A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits;Massimo Alioto 等;《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION(VLSI)SYSTEMS》;20100422;第18卷(第5期);711-724 * |
| JP特开2000-90668A 2000.03.31 |
| Massimo Alioto 等.A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits.《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION(VLSI)SYSTEMS》.2010,第18卷(第5期),711-724. |
| 一种新型灵敏放大器的设计;高宁 等;《电子与封装》;20070723;第7卷(第6期);21-24 * |
| 高宁 等.一种新型灵敏放大器的设计.《电子与封装》.2007,第7卷(第6期),21-24. |
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