CN102624378B - Low-power-consumption domino three-value character arithmetic circuit - Google Patents
Low-power-consumption domino three-value character arithmetic circuit Download PDFInfo
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Abstract
The invention discloses a low-power-consumption domino three-value character arithmetic circuit, which comprises a first character arithmetic circuit unit, a second character arithmetic circuit unit and a third character arithmetic circuit unit. The first character arithmetic circuit unit, the second character arithmetic circuit unit and the third character arithmetic circuit unit all achieve functions through a heat insulation circuit, a three-value character arithmetic circuit and a domino circuit. The low-power-consumption domino three-value character arithmetic circuit has the advantages of integrating the heat insulation circuit and the domino circuit into the three-value character arithmetic circuit, converting energy of circuits according to a sequence of a power supply-a signal node-a power supply through the heat insulation circuit, being capable of effectively reducing power consumption of the circuits, enabling the power consumption of the circuits to be low, enabling the circuits to have smaller area by combining the domino circuit with a multi-value circuit, further improving information density of the circuits, reducing the quantity of chip pins and connecting wires, and enabling the circuits to have simple structures.
Description
Technical field
The present invention relates to a kind of three value word computing circuits, especially relate to a kind of low-power consumption domino three and be worth word computing circuit.
background technology
At present, semiconductor technology has been stepped into the deep-submicron epoch, and transistor size integrated on monolithic chip is very huge, and still to surmount the speed increment of Moore's Law.Estimate at the year two thousand twenty, the characteristic size of integrated circuit will reach 14nm, and the thing followed is the problem of circuit power consumption surge and circuit structure complexity, become two targets of chip design overriding concern so reduce the power consumption of circuit and simplify circuit structure.In many methods that realizes low-power consumption, adopt the adiabatic circuits of AC pulse power supply to change the Energy Transfer mode of traditional circuit, energy is recycled by power supply → signal node → power supply, significantly improve capacity usage ratio, greatly reduce circuit power consumption, become the focus of low consumption circuit research.And simplifying aspect circuit structure, compared with traditional binarization circuit, multivalued circuit, owing to can improving the information density of circuit, reduces the quantity of chip pin and interconnection line, has been subject to domestic and international researcher's attention.Wherein, because domino circuit area is little, speed is fast, therefore domino circuit is applied in multivalued circuit, can further improves information density and the performance of circuit, promote the fast development of multivalued circuit.
Three value word computings (three value threshold operations), three values and computing and three value exclusive disjunctions etc. are the basic operations in ternary algebra, and three value word computing circuits, as the one in three value fundamental arithmetic circuits, are one of common circuit in three value digital systems.But compared with the gate circuit such as three values and door or door, the research of three value word computing circuits is but relatively less, to being applicable to the researches of word computing circuit of adiabatic domino circuit.In view of this, the research of adiabatic circuits, domino circuit and three value word computing circuits is had to realistic meaning.
summary of the invention
Technical problem to be solved by this invention is to provide a kind of circuit power consumption low-power consumption domino three lower and simple in structure and is worth word computing circuit.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of low-power consumption domino three is worth word computing circuit, comprise the first word computing circuit unit, the second word computing circuit unit and the 3rd word computing circuit unit, the first described word computing circuit unit is mainly managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe composition, the drain electrode of the source electrode of a described PMOS pipe and a described NMOS pipe is connected to first signal output, described first signal output is first output signal of 0 o'clock for output logic value, the source electrode of a described NMOS pipe is connected with the drain electrode of the 2nd described NMOS pipe, the source electrode of the 2nd described PMOS pipe is connected with the drain electrode of the 3rd described PMOS pipe, the drain electrode of the source electrode of the 3rd described PMOS pipe and the 3rd described NMOS pipe is connected to the first complementary signal output, the first described complementary signal output is first complementary output signal of 0 o'clock for output logic value, the grid of a described NMOS pipe connects signal input part, the grid of the 3rd described PMOS pipe connects described first signal output, the grid of a described PMOS pipe, the grid of the 2nd described NMOS pipe, the source electrode of the drain electrode of the 2nd described PMOS pipe and the 3rd described NMOS pipe is connected to clock clock signal input terminal, the drain electrode of a described PMOS pipe, the source electrode of the 2nd described NMOS pipe, the grid of the grid of the 2nd described PMOS pipe and the 3rd described NMOS pipe is connected to power clock signal input part, the second described word computing circuit unit is managed by the 4th PMOS, the 5th PMOS pipe, the 6th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe and the 6th NMOS pipe composition, the drain electrode of the source electrode of the 4th described PMOS pipe and the 4th described NMOS pipe is connected to the second complementary signal output, the second described complementary signal output is second complementary output signal of 2 o'clock for output logic value, the source electrode of the 4th described NMOS pipe is connected with the drain electrode of the 5th described NMOS pipe, the source electrode of the 5th described PMOS pipe is connected with the drain electrode of the 6th described PMOS pipe, the drain electrode of the source electrode of the 6th described PMOS pipe and the 6th described NMOS pipe is connected to secondary signal output, described secondary signal output is second output signal of 2 o'clock for output logic value, the grid of the 4th described NMOS pipe connects described signal input part, the grid of the 6th described PMOS pipe connects the second described complementary signal output, the grid of the 4th described PMOS pipe, the grid of the 5th described NMOS pipe, the source electrode of the drain electrode of the 5th described PMOS pipe and the 6th described NMOS pipe is connected to described clock clock signal input terminal, the drain electrode of the 4th described PMOS pipe, the source electrode of the 5th described NMOS pipe, the grid of the grid of the 5th described PMOS pipe and the 6th described NMOS pipe is connected to described power clock signal input part, the 3rd described word computing circuit unit is made up of the 7th NMOS pipe, the drain electrode of the 7th described NMOS pipe connects the first described complementary signal output, the grid of the 7th described NMOS pipe connects the second described complementary signal output, the source electrode of the 7th described NMOS pipe connects the 3rd signal output part, the 3rd described signal output part is the 3rd output signal of 1 o'clock for output logic value.
The first described word computing circuit unit is connected with the first waveform changing circuit, the second described word computing circuit unit is connected with the second waveform changing circuit, the 3rd described word computing circuit unit is connected with the 3rd waveform changing circuit, the first described waveform changing circuit is mainly made up of the 8th NMOS pipe and the 9th NMOS pipe, the drain electrode of the 8th described NMOS pipe is connected with described first signal output, the source electrode of the 8th described NMOS pipe is connected with the grid of the 9th described NMOS pipe, the grid of the 8th described NMOS pipe connects described clock clock signal input terminal, the source electrode of the 9th described NMOS pipe connects described power clock signal input part, the drain electrode of the 9th described NMOS pipe is the first waveform switching signal output, the second described waveform changing circuit is mainly made up of the tenth NMOS pipe and the 11 NMOS pipe, the drain electrode of the tenth described NMOS pipe is connected with described secondary signal output, the source electrode of the tenth described NMOS pipe is connected with the grid of the 11 described NMOS pipe, the grid of the tenth described NMOS pipe connects described clock clock signal input terminal, the source electrode of the 11 described NMOS pipe connects described power clock signal input part, the drain electrode of the 11 described NMOS pipe is the second waveform switching signal output, the 3rd described waveform changing circuit is mainly made up of the 12 NMOS pipe and the 13 NMOS pipe, the drain electrode of the 12 described NMOS pipe is connected with the 3rd described signal output part, the source electrode of the 12 described NMOS pipe is connected with the grid of the 13 described NMOS pipe, the grid of the 12 described NMOS pipe connects described clock clock signal input terminal, the source electrode of the 13 described NMOS pipe connects described power clock signal input part, the drain electrode of the 13 described NMOS pipe is the 3rd waveform transformation signal output part.
Compared with prior art, the invention has the advantages that adiabatic circuits and domino circuit are incorporated in three value word computing circuits, by adiabatic circuits, the energy of circuit is transformed by power supply → signal node → power supply, can effectively reduce the power consumption of circuit, make circuit power consumption lower, make circuit there is less area by the combination of domino circuit and multivalued circuit, further improve the information density of circuit, the quantity that reduces chip pin and interconnection line, makes circuit have simple structure;
When increasing respectively a waveform changing circuit at three signal output parts of circuit, each output signal is carried out to waveform optimization, make circuit output be applicable to the gradual trapezoidal wave signal of adiabatic circuits, this gradual trapezoidal wave signal and clock phase error are minimum, basic and clock signal synchronization, can effectively reduce the extra power consumption that the adiabatic domino circuit of rear class produces because of the phase difference of signal and clock in the time discharging and recharging, for the design of many-valued adiabatic domino complicated circuit is laid a good foundation.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of the embodiment of the present invention one;
Fig. 2 is the structural representation of switch-signal algebra system;
Fig. 3 is the structural representation of domino circuit;
Fig. 4 is the structural representation of adiabatic domino circuit;
Fig. 5 is clock waveform figure of the present invention;
Fig. 6 is the circuit structure diagram of the first waveform changing circuit, the second waveform changing circuit and the 3rd waveform changing circuit of the embodiment of the present invention two;
Fig. 7 is the circuit simulation oscillogram that in the embodiment of the present invention two, low-power consumption domino three is worth word computing circuit;
Fig. 8 is that in the embodiment of the present invention two, low-power consumption domino three is worth the transient state energy consumption comparison diagram that word computing circuit and conventional domino three are worth word computing circuit.
Embodiment
Below in conjunction with accompanying drawing, embodiment is described in further detail the present invention.
Embodiment mono-: as shown in Figure 1, a kind of low-power consumption domino three is worth word computing circuit, comprise the first word computing circuit unit 1, the second word computing circuit unit 2 and the 3rd word computing circuit unit 3, the first word computing circuit unit 1 is mainly by a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the one NMOS pipe N1, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 composition, the drain electrode of the source electrode of the one PMOS pipe P1 and NMOS pipe N1 is connected to first signal output, first signal output is first output signal of 0 o'clock for output logic value
0 x 0the source electrode of the one NMOS pipe N1 is connected with the drain electrode of the 2nd NMOS pipe N2, the source electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 3rd PMOS pipe P3, the drain electrode of the source electrode of the 3rd PMOS pipe P3 and the 3rd NMOS pipe N3 is connected to the first complementary signal output, and the first complementary signal output is first complementary output signal of 0 o'clock for output logic value
, the grid of a NMOS pipe N1 connects signal input part, signal input part access three value input signals
x,
the grid of the 3rd PMOS pipe P3 connects first signal output, the grid of the one PMOS pipe P1, the grid of the 2nd NMOS pipe N2, the drain electrode of the 2nd PMOS pipe P2 and the source electrode of the 3rd NMOS pipe N3 are connected to clock clock signal input terminal, clock clock signal input terminal access clock clock signal
clk, the drain electrode of a PMOS pipe P1, the source electrode of the 2nd NMOS pipe N2, the grid of the 2nd PMOS pipe P2 and the grid of the 3rd NMOS pipe N3 are connected to power clock signal input part, power clock signal input part access power clock signal input terminal
nclkthe second word computing circuit unit 2 is made up of the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 4th NMOS pipe N4, the 5th NMOS pipe N5 and the 6th NMOS pipe N6, the drain electrode of the source electrode of the 4th PMOS pipe P4 and the 4th NMOS pipe N4 is connected to the second complementary signal output, and the second complementary signal output is second complementary output signal of 2 o'clock for output logic value
the source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5, the source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 6th PMOS pipe P6, the drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe N6 is connected to secondary signal output, and secondary signal output is second output signal of 2 o'clock for output logic value
2 x 2, the grid of the 4th NMOS pipe N4 connects signal input part, the grid of the 6th PMOS pipe P6 connects the second complementary signal output, the grid of the 4th PMOS pipe P4, the grid of the 5th NMOS pipe N5, the source electrode of the drain electrode of the 5th PMOS pipe P5 and the 6th NMOS pipe N6 is connected to clock clock signal input terminal, the drain electrode of the 4th PMOS pipe P4, the source electrode of the 5th NMOS pipe N5, the grid of the grid of the 5th PMOS pipe P5 and the 6th NMOS pipe N6 is connected to power clock signal input part, the 3rd word computing circuit unit 3 is made up of the 7th NMOS pipe N7, the drain electrode of the 7th NMOS pipe N7 connects the first complementary signal output, the grid of the 7th NMOS pipe N7 connects the second complementary signal output, the source electrode of the 7th NMOS pipe N7 connects the 3rd signal output part, the 3rd signal output part is the 3rd output signal of 1 o'clock for output logic value
1 x 1.
It is as described below that low-power consumption domino three in the present embodiment is worth design principle and the design process of word computing circuit: in the design of binarization circuit, mainly take Boolean algebra as basis, therefore in the design of multivalued circuit, also once generally believed it is mainly take post algebra as Fundamentals of Mathematics.The function representing with Boolean logic is generally realized with gate circuit, but the complexity of multivalued gate circuit is more much higher than two-value gate circuit, so the design of the gate leve of multivalued circuit is not the most simple and effective method for designing.Boolean algebra is just used for describing merely the algebra system of signal, variable in this type systematic is only described the value of signal, the gate leve processing to signal is only described in computing, ignore the existence of switch, switch-signal theory is introduced switching variable, be used for representing transistorized on off state, set up switching algebra and the signal algebraically of correspondence with it, for the design of multivalued circuit provides reliable theory.
In switching algebra, switching variable
α,
βvalue
twith
frepresent respectively transistorized turn-on and turn-off, have and () or (+), non-(-) three kinds of basic operations; In signal algebraically, signal variable
x,
yvalue be 0,1 ...,
m-1, be used for representing multivalued circuit
mkind of voltage signal, get little (∩), get large (∪) and word computing (
i x i ) etc. basic operation.
Switching algebra and signal algebraically are not separate, relation between them as shown in Figure 2, connective operation I is used for describing the physical process of signal controlling element switch state, and connective operation II is described the transmission of on off state control signal and the physical process of formation of element.
Wherein, connective operation I mainly contains high threshold comparison operation and low threshold comparison operation:
High threshold comparison operation:
(1)
Low threshold comparison operation:
(2)
Connective operation II mainly contains transmission computing and union:
Transmission computing:
(3)
Union:
(4)
In formula (3)
sfor transmission sources,
for high-impedance state, * is transmission computing; In formula (4)
s 1with
s 2represent respectively two different transmission sources, transmit computing " * " priority higher than union " # ", and for preventing the appearance of short circuit current, when
s 1≠
s 2in time, does not allow
α 1,
α 2be simultaneously
t(conducting).
Domino circuit, owing to having little, the fireballing advantage of area, is widely used in the design in system core path, is mainly divided into two kinds of P type domino circuit and N-type domino circuits, and its structure as shown in Figure 3.The course of work of P type domino circuit is:
clk=1 o'clock, NMOS managed M
1conducting, PMOS manages M
2cut-off, dynamic output node
outby pre-arcing to low level;
clk=0 o'clock, NMOS managed M
1cut-off, PMOS manages M
2conducting, P logical circuit is according to whether conducting of input-signal judging, if the conducting of P logical circuit, dynamic output node
outjust be charged to supply voltage
v dDif the not conducting of P logical circuit, remains unchanged.The course of work of N-type domino circuit is:
clk=0 o'clock, PMOS managed M
3conducting, NMOS manages M
4cut-off, dynamic output node
outbe charged in advance supply voltage
v dD;
clk=1 o'clock, PMOS managed M
3cut-off, NMOS manages M
4conducting, N logical circuit is according to whether conducting of input-signal judging, if the conducting of N logical circuit, dynamic output node
outjust be discharged to low level, if the not conducting of N logical circuit remains unchanged.
The input signal of P type domino circuit is Low level effective, and output signal is that high level is effective, and N-type domino circuit is just the opposite.Therefore, the circuit of two types can be replaced to cascade, not only easily design, and can reduce the frequency of utilization of inverter, thereby reduce the power consumption of circuit.
According to adiabatic circuits design principle, replace the DC power supply of conventional domino circuit with power clock, circuit just becomes the adiabatic domino circuit that can carry out energy recovery, and its circuit and clock waveform are respectively as shown in Figure 4 and Figure 5.Due to NMOS pipe, to discharge and recharge speed than PMOS pipe fast, and therefore N-type domino circuit more can be brought into play the fireballing advantage of domino circuit, applies more extensive.Take the adiabatic domino circuit of N-type as example, introduce the course of work of adiabatic domino circuit below: when
clk=0 o'clock, PMOS managed M
5conducting, NMOS manages M
6cut-off,
nclkto dynamic output node
outprecharge; When
clk=1 o'clock, PMOS managed M
5cut-off, NMOS manages M
6conducting, N logical circuit is according to whether conducting of input-signal judging, if the conducting of N logical circuit, dynamic output node
outthe electric charge of upper storage is just recycled to power clock
nclkif the not conducting of N logical circuit, remains unchanged.Compared with the adiabatic circuits of adiabatic domino circuit and other types, circuit structure is simple, be easy to design; Simultaneously, because adiabatic domino circuit has the characteristic that energy reclaims, therefore adiabatic domino circuit is combined with multivalued circuit and can further improve the information density of circuit, the power consumption of reduction circuit, for the realization of low-power consumption high information density circuit provides new approach.
Three value word (Literal) computings, are called again three value threshold (Threshold) computings, are one of basic operations in ternary algebra, and it defines suc as formula shown in (5):
(5)
The truth table of three value word computings is as shown in table 1:
The truth table of table 1 three value word computings
Three value word computings have mutual exclusion and complementary character:
Mutual exclusion rule:
(6)
Complementary frequency response:
(7)
Owing to there is mutual exclusion and complementary restriction relation between three word computings, therefore one of them word computing always can be obtained by two other word computing:
Therefore, in the time of design three value word computing circuit, only need to derive the wherein structural formula of two circuit by switch-signal theory, recycling formula (8) just can obtain complete circuit structure formula.So not only simplify the design process of circuit, and reduced complexity and the cost of circuit, be conducive to further design many-valued complicated circuit.
According to truth table and the switch-signal theory of three value word computings, can derive the first output signal
0 x 0the switching stage structural formula of word computing.Wherein,
clkfor the clock clock signal of circuit,
nclkfor the power clock signal of circuit,
xfor input signal, the first output signal
0 x 0the switching stage structural formula of word computing is as follows:
In formula (9), Section 1
represent power clock signal
nclkto the pre-charge process of the first output signal end, Section 2
represent to work as input signal
x≠ 0 o'clock, the electric charge that is stored in the first output signal end was recycled to power clock signal
nclkprocess; What formula (10) represented is the first output signal
0 x 0obtain the first complementary output signal through adiabatic domino inverter
process.
In like manner can obtain the second output signal
2 x 2the switching stage structural formula of word computing:
(12)
In formula (11), Section 1
represent power clock signal
nclkto the pre-charge process of the second complementary signal output, Section 2
represent to work as input signal
x=2 o'clock, the electric charge that is stored in the second complementary signal output was recycled to power clock signal
nclkprocess.Because circuit exists
x=2 carry out electric charge recovery, and making dynamic output node is low level, so will, through the adiabatic domino inverter representing suc as formula (12), obtain the second output signal
2 x 2.According to formula (8), formula (10) and formula (11), can obtain the 3rd output signal
1 x 1the switching stage structural formula of word computing:
By formula (8) ~ formula (13), we can obtain the circuit structure diagram that a kind of low-power consumption domino three is as shown in Figure 1 worth word computing circuit.In the design process of the present embodiment, by adiabatic circuits, domino circuit and three value word computing circuit reasonable combination, guaranteeing under the prerequisite of correct logic, making circuit there is lower power consumption and simple circuit structure.
Embodiment bis-: as shown in Figure 6, the present embodiment and embodiment mono-are basic identical, its difference is only that the first word computing circuit unit 1 is connected with the first waveform changing circuit 11, the second word computing circuit unit 2 is connected with the second waveform changing circuit 21, the 3rd word computing circuit unit 3 is connected with the 3rd waveform changing circuit 31, the first waveform changing circuit 11 is mainly made up of the 8th NMOS pipe N8 and the 9th NMOS pipe N9, the drain electrode of the 8th NMOS pipe N8 is connected with first signal output, the source electrode of the 8th NMOS pipe N8 is connected with the grid of the 9th NMOS pipe N9, the grid of the 8th NMOS pipe N8 connects clock clock signal input terminal, the source electrode of the 9th NMOS pipe N9 connects power clock signal input part, the drain electrode of the 9th NMOS pipe N9 is the first waveform switching signal output, the first waveform switching signal output is exported the first waveform switching signal
out 0the second waveform changing circuit 21 is mainly made up of the tenth NMOS pipe N10 and the 11 NMOS pipe N11, the drain electrode of the tenth NMOS pipe N10 is connected with secondary signal output, the source electrode of the tenth NMOS pipe N10 is connected with the grid of the 11 NMOS pipe N11, the grid of the tenth NMOS pipe N10 connects clock clock signal input terminal, the source electrode of the 11 NMOS pipe N11 connects power clock signal input part, the drain electrode of the 11 NMOS pipe N11 is the second waveform switching signal output, and the second waveform switching signal output is exported the second waveform switching signal
out 2the 3rd waveform changing circuit 31 is mainly made up of the 12 NMOS pipe N12 and the 13 NMOS pipe N13, the drain electrode of the 12 NMOS pipe N12 is connected with the 3rd signal output part, the source electrode of the 12 NMOS pipe N12 is connected with the grid of the 13 NMOS pipe N13, the grid of the 12 NMOS pipe N12 connects clock clock signal input terminal, the source electrode of the 13 NMOS pipe N13 connects power clock signal input part, the drain electrode of the 13 NMOS pipe N13 is the 3rd waveform transformation signal output part, the 3rd waveform transformation signal output part output the 3rd waveform transformation signal
out 1.
In the present embodiment, design principle and the process of the first waveform changing circuit 11, the second waveform changing circuit 21 and the 3rd waveform changing circuit 31 are as described below: in the evaluation circuit of adiabatic domino circuit, generally only have NMOS pipe or PMOS pipe, this just causes logical one in the time realizing ternary circuit to be difficult to identification, and therefore the first order circuit of tri-valued, thermal-insulating domino circuit is generally three value word computing circuits.If the output signal of tri-valued, thermal-insulating domino circuit and clock signal phase are poor excessive, can make late-class circuit in the time discharging and recharging, produce extra power consumption, and the complexity of late-class circuit is larger, also larger on the total power consumption impact of circuit.Therefore be necessary output waveform to change, make it to become rule with the poor less trapezoidal wave of clock signal phase.
According to switch-signal theory, obtain
0 x 0,
1 x 1, and
2 x 2waveform changing circuit structural formula is as follows, wherein
out 0,
out 1,
out 2be respectively
0 x 0,
1 x 1,
2 x 2output signal after waveform transformation:
The circuit structure diagram that can obtain optimization as shown in Figure 6 according to formula (14) ~ formula (16), the course of work of the first waveform changing circuit 11 is as follows: when clock clock signal
clkduring for high level, the first output signal of three value word computing circuits
0 x 0to node, A charges; When clock clock signal
clkbecome after low level, node A still keeps high level, output node
out 0waveform with power clock signal
nclkchange, thereby by the first output signal
0 x 0waveform be converted into gradual trapezoidal wave.The course of work of the second waveform changing circuit 21 and the 3rd waveform changing circuit 31 is all similar with the first waveform changing circuit 11.
Hence one can see that, the first output signal in the present embodiment
0 x 0, the second output signal
2 x 2with the 3rd output signal
1 x 1
Change by the first waveform changing circuit 11, the second waveform changing circuit 21 and the 3rd waveform changing circuit 31 respectively, after three waveform transformation signals obtaining
out 0,
out 1with
out 2waveform be more regular gradual trapezoidal wave, and minimum with clock phase error, can effectively reduce the extra power consumption that the adiabatic domino circuit of rear class produces because of the phase difference of signal and clock in the time discharging and recharging, for the design of many-valued adiabatic domino complicated circuit is laid a good foundation.
Utilize Spice software, under TSMC 0.25 μ mCMOS technological parameter, to the present embodiment is carried out to emulation, wherein
clkwith
nclkcycle is 1.2 ns, and amplitude is 2.5V; Logical value 0,1, the level of 2 correspondences is respectively 0V, 1.5V, 2.5V; Load capacitance is 10 fF; PMOS pipe breadth length ratio is 2.4 μ m/0.24 μ m, and NMOS pipe breadth length ratio is 2.88 μ m/0.24 μ m.When input signal is " 012012012 ... " time, the simulation waveform of circuit is as shown in Figure 7.Analysis chart 7 is known, and the logic function of circuit and three value word computing truth tables are consistent, and output waveform is regular trapezoidal wave, with clock
nclkphase error is minimum, has perfectly realized purpose of design.
Fig. 8 is that the low-power consumption domino three in the present embodiment is worth the transient state energy consumption comparison diagram that word computing circuit and conventional domino three are worth word computing circuit, wherein ordinate is circuit energy consumption, within 12 ns times, the former saves approximately 39% than the latter energy consumption, proves that this low-power consumption domino three is worth word computing circuit and has significant low-power consumption characteristic.
Claims (2)
1. a low-power consumption domino three is worth word computing circuit, it is characterized in that comprising the first word computing circuit unit, the second word computing circuit unit and the 3rd word computing circuit unit, the first described word computing circuit unit is mainly managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe composition, the drain electrode of the source electrode of a described PMOS pipe and a described NMOS pipe is connected to first signal output, described first signal output is first output signal of 0 o'clock for output logic value, the source electrode of a described NMOS pipe is connected with the drain electrode of the 2nd described NMOS pipe, the source electrode of the 2nd described PMOS pipe is connected with the drain electrode of the 3rd described PMOS pipe, the drain electrode of the source electrode of the 3rd described PMOS pipe and the 3rd described NMOS pipe is connected to the first complementary signal output, the first described complementary signal output is first complementary output signal of 0 o'clock for output logic value, the grid of a described NMOS pipe connects signal input part, the grid of the 3rd described PMOS pipe connects described first signal output, the grid of a described PMOS pipe, the grid of the 2nd described NMOS pipe, the source electrode of the drain electrode of the 2nd described PMOS pipe and the 3rd described NMOS pipe is connected to clock clock signal input terminal, the drain electrode of a described PMOS pipe, the source electrode of the 2nd described NMOS pipe, the grid of the grid of the 2nd described PMOS pipe and the 3rd described NMOS pipe is connected to power clock signal input part, the second described word computing circuit unit is managed by the 4th PMOS, the 5th PMOS pipe, the 6th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe and the 6th NMOS pipe composition, the drain electrode of the source electrode of the 4th described PMOS pipe and the 4th described NMOS pipe is connected to the second complementary signal output, the second described complementary signal output is second complementary output signal of 2 o'clock for output logic value, the source electrode of the 4th described NMOS pipe is connected with the drain electrode of the 5th described NMOS pipe, the source electrode of the 5th described PMOS pipe is connected with the drain electrode of the 6th described PMOS pipe, the drain electrode of the source electrode of the 6th described PMOS pipe and the 6th described NMOS pipe is connected to secondary signal output, described secondary signal output is second output signal of 2 o'clock for output logic value, the grid of the 4th described NMOS pipe connects described signal input part, the grid of the 6th described PMOS pipe connects the second described complementary signal output, the grid of the 4th described PMOS pipe, the grid of the 5th described NMOS pipe, the source electrode of the drain electrode of the 5th described PMOS pipe and the 6th described NMOS pipe is connected to described clock clock signal input terminal, the drain electrode of the 4th described PMOS pipe, the source electrode of the 5th described NMOS pipe, the grid of the grid of the 5th described PMOS pipe and the 6th described NMOS pipe is connected to described power clock signal input part, the 3rd described word computing circuit unit is made up of the 7th NMOS pipe, the drain electrode of the 7th described NMOS pipe connects the first described complementary signal output, the grid of the 7th described NMOS pipe connects the second described complementary signal output, the source electrode of the 7th described NMOS pipe connects the 3rd signal output part, the 3rd described signal output part is the 3rd output signal of 1 o'clock for output logic value.
2. a kind of low-power consumption domino three according to claim 1 is worth word computing circuit, it is characterized in that the first described word computing circuit unit is connected with the first waveform changing circuit, the second described word computing circuit unit is connected with the second waveform changing circuit, the 3rd described word computing circuit unit is connected with the 3rd waveform changing circuit, the first described waveform changing circuit is mainly made up of the 8th NMOS pipe and the 9th NMOS pipe, the drain electrode of the 8th described NMOS pipe is connected with described first signal output, the source electrode of the 8th described NMOS pipe is connected with the grid of the 9th described NMOS pipe, the grid of the 8th described NMOS pipe connects described clock clock signal input terminal, the source electrode of the 9th described NMOS pipe connects described power clock signal input part, the drain electrode of the 9th described NMOS pipe is the first waveform switching signal output, the second described waveform changing circuit is mainly made up of the tenth NMOS pipe and the 11 NMOS pipe, the drain electrode of the tenth described NMOS pipe is connected with described secondary signal output, the source electrode of the tenth described NMOS pipe is connected with the grid of the 11 described NMOS pipe, the grid of the tenth described NMOS pipe connects described clock clock signal input terminal, the source electrode of the 11 described NMOS pipe connects described power clock signal input part, the drain electrode of the 11 described NMOS pipe is the second waveform switching signal output, the 3rd described waveform changing circuit is mainly made up of the 12 NMOS pipe and the 13 NMOS pipe, the drain electrode of the 12 described NMOS pipe is connected with the 3rd described signal output part, the source electrode of the 12 described NMOS pipe is connected with the grid of the 13 described NMOS pipe, the grid of the 12 described NMOS pipe connects described clock clock signal input terminal, the source electrode of the 13 described NMOS pipe connects described power clock signal input part, the drain electrode of the 13 described NMOS pipe is the 3rd waveform transformation signal output part.
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| CN102902508B (en) * | 2012-09-14 | 2015-06-24 | 宁波大学 | Ternary adiabatic domino multiplication unit |
| CN103219990B (en) * | 2013-04-02 | 2016-01-20 | 宁波大学 | Based on three value low-power consumption T computing circuits of adiabatic domino logic |
| CN104333374B (en) * | 2014-09-29 | 2017-05-03 | 宁波大学 | Low-power domino three-value reversible counter unit circuit |
| CN107731254B (en) * | 2017-10-10 | 2020-05-12 | 宁波大学 | Ternary static memory using character arithmetic circuit and CNFET |
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| JPH10189884A (en) * | 1998-01-14 | 1998-07-21 | Hitachi Ltd | Low power-consumption type semiconductor integrated circuit |
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