CN105141290B - A kind of power control single track current-mode d type flip flop - Google Patents
A kind of power control single track current-mode d type flip flop Download PDFInfo
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- CN105141290B CN105141290B CN201510505396.XA CN201510505396A CN105141290B CN 105141290 B CN105141290 B CN 105141290B CN 201510505396 A CN201510505396 A CN 201510505396A CN 105141290 B CN105141290 B CN 105141290B
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- nmos tube
- pmos
- power control
- latch
- type flip
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Abstract
The invention discloses a kind of power control single track current-mode d type flip flop, including main latch, from latch and power control module；Main latch includes the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube；Include the 3rd PMOS, the 4th PMOS, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the tenth NMOS tube from latch；Power control module includes the 5th PMOS, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube and the 14th NMOS tube；Power control module is opened or cut-out main latch in work with replacing under idle condition, and making main latch, section is in a dormant state at one's leisure；Critical path uses Low threshold transistor, and non-critical path uses middle and high threshold transistor；Advantage is to reduce the leakage power consumption in d type flip flop, reduces delay, power consumption and the power-consumption design of integrated circuit, and smaller delay, power consumption and power-consumption design are respectively provided with low frequency and high frequency service condition, the performance of d type flip flop is improved.
Description
Technical field
The present invention relates to a kind of d type flip flop, more particularly, to a kind of power control single track current-mode d type flip flop.
Background technology
At present, in digital circuitry, sequential logical circuit is made up of storage circuit and combinational logic, and storage circuit is used
In the state for keeping digital circuitry.Trigger plays an important role as a kind of storage circuit in digital circuitry.
With the continuous progress of VLSI technologies, the speed of service and power consumption requirements of digital circuitry are improved constantly, to trigger performance
Requirement it is also harsher, it is desirable to trigger should have low-power consumption and short delay, speed, power consumption and area of trigger etc.
Performance will directly influence the overall performance of digital circuitry.Delay, power consumption and power consumption-delay product are to embody trigger performance
Three principal elements, the performance of trigger can be optimized so as to improve the performance of digital circuitry by optimizing these three factors,
Wherein, power consumption-delay product is power consumption and the product of delay, and unit is joule, therefore power consumption-delay product is the measurement of energy, can
Using the measurement as a switching device performance.
Existing d type flip flop mainly has two kinds, and a kind of is traditional hypotactic edge D flip-flops of static CMOS, separately
One kind is single track current-mode d type flip flop.Traditional hypotactic edge D flip-flops of static CMOS, be by cmos logic gate and
The D master-slave flip-flop of cmos transmission gate composition, its circuit structure diagram is as shown in Figure 1.The D master-slave flip-flop is as a result of multiple
Cmos transmission gate structure, its speed close to or logic, be delayed higher, and can produce under higher operational frequency larger
Power consumption.Single track current-mode d type flip flop is constituted by main latch, from latch and biased witch, main latch by NMOS tube N1,
N2, N3, N4 and N5 constitute, be made up of from latch NMOS tube N6, N7, N8, N9 and N10, biased witch by PMOS P1, P2,
NMOS tube N11 and N12 are constituted, and its circuit diagram is as shown in Figure 2；Clk is that clock signal, clkb are negating for clock signal in Fig. 2
Signal, D are that input signal, Q are output signal, VddFor standard mains voltage, VrfpFor PMOS bias supply signal, VrfnFor
NMOS tube bias supply signal；In a cycle T, interior main latch is in effective working condition, P1 during 0-0.5T
Phase inverter is constituted with N1, transmission signal X is producedb, X is realized in N2 and N3 series connectionbWith clkb's and logic, N4 connects with N5 realizes D
With clk's and logic, P1, P2, N1, N2, N3, N4 and N5 combinational logic produce transmission signal XbComplementary signal X, now lead
Function of the latch in the complete T cycles has been fully achieved, although normal work in during 0.5T-T, unreal
Border is acted on；During 0-T, working condition is constantly in from latch, P4 and N10 constitutes phase inverter, produces output signal Qb,
N6 and N7 series connection realizes X and clkb's and logic, and N8 connects with N9 realizes QbWith clk's and logic, P3, P4, N6, N7,
N8, N9 and N10 combinational logic produce output signal Q, realize d type flip flop function.Although single track current-mode d type flip flop is more traditional
The hypotactic edge D flip-flops of static CMOS delay it is lower, power consumption is also more excellent under higher operational frequency, but the list
Rail current-mode d type flip flop is within a complete work period, main latch and, leakage in running order always from latch
Power consumption is bigger than normal, thus causes the power consumption and power consumption-delay product of single track current-mode d type flip flop still larger.
The content of the invention
The technical problems to be solved by the invention be to provide it is a kind of be respectively provided with low frequency and high frequency service condition it is less
The power control single track current-mode d type flip flop of delay, power consumption and power consumption-delay product.
The present invention solve the technical scheme that is used of above-mentioned technical problem for：A kind of power control single track current-mode d type flip flop, bag
Include main latch, from latch and power control module；
Described main latch includes the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd
NMOS tube, the 4th NMOS tube and the 5th NMOS tube；The source electrode of the first described PMOS, the source electrode of the second described PMOS,
The substrate of the first described PMOS and the substrate of the second described PMOS are connected and its connection end is described main latch
Power end, the power end of described main latch accesses the first power supply, the draining of described the first PMOS, described first
The grid connection of the draining of NMOS tube, the drain electrode of the 3rd described NMOS tube and the 5th described NMOS tube and its connection end is institute
The output end for the main latch stated, the draining of described the second PMOS, the grid and described of the 3rd described NMOS tube
The drain electrode connection of five NMOS tubes, the drain electrode connection of the source electrode of described the first NMOS tube and the second described NMOS tube is described
The drain electrode connection of the source electrode of 3rd NMOS tube and the 4th described NMOS tube, the grid of described the first PMOS and described the
The grid of two PMOSs is connected and its connection end is the bias supply input of described main latch, the second described NMOS tube
Source electrode, the source electrode of described 4th NMOS tube and the source electrode connection of the 5th described NMOS tube and its connection end is described master
The control signal input of latch, the grid of the first described NMOS tube is the input of described main latch, described
The grid of second NMOS tube is the clock signal terminal of described main latch, and the grid of the 4th described NMOS tube is described master
The complementary clock signal end of latch；The substrate of the first described NMOS tube, the substrate of the second described NMOS tube, described
The substrate of the substrate of three NMOS tubes, the substrate of the 4th described NMOS tube and the 5th described NMOS tube is grounded；
Described includes the 3rd PMOS, the 4th PMOS, the 6th NMOS tube, the 7th NMOS tube, the 8th from latch
NMOS tube, the 9th NMOS tube and the tenth NMOS tube；The source electrode of the 3rd described PMOS, the source electrode of the 4th described PMOS,
The substrate of the 3rd described PMOS and the substrate of the 4th described PMOS are connected and its connection end is described from latch
Power end, the power end from latch accesses second source, the grid of described the 3rd PMOS and described the
The grid of four PMOSs is connected and its connection end is the bias supply input from latch, the 3rd described PMOS
Drain, the draining of described 6th NMOS tube, the grid of the drain electrode of the 8th described NMOS tube and the tenth described NMOS tube
Connection and its connection end are the output end from latch, the draining of described the 4th PMOS, the 8th described NMOS
The drain electrode of the grid of pipe and the tenth described NMOS tube is connected and its connection end is the complementary output end from latch, institute
The drain electrode connection of the source electrode for the 6th NMOS tube stated and the 7th described NMOS tube, the source electrode of described the 8th NMOS tube and described
The 9th NMOS tube drain electrode connection, the source electrode of described the 7th NMOS tube, the source electrode of the 9th described NMOS tube and described
The source electrode of tenth NMOS tube is connected and its connection end is the control signal input from latch, the 6th described NMOS
The substrate of pipe, the substrate of the 7th described NMOS tube, the substrate of the 8th described NMOS tube, the substrate of the 9th described NMOS tube
It is grounded with the substrate of the tenth described NMOS tube, the grid of the 6th described NMOS tube is the input from latch
End, the grid of described the 7th NMOS tube is the complementary clock end from latch, the grid of described the 9th NMOS tube
For the clock end from latch；
Described power control module include the 5th PMOS, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube and
14th NMOS tube；The draining of the 5th described PMOS, the drain of the 11st described NMOS tube, the 12nd described NMOS
The grid of pipe and the connection of the grid of the 13rd described NMOS tube, the source electrode and the described the 14th of described the 5th PMOS
The grid connection of NMOS tube and its connection end are the bias supply input of described power control module, described the 5th PMOS
Grid and the grid of the 11st described NMOS tube are connected and its connection end is the power control signal input part of described power control module,
The substrate access NMOS tube bias supply signal of the 5th described PMOS, it is the substrate of described the 11st NMOS tube, described
The substrate of 12nd NMOS tube, the substrate of the 13rd described NMOS tube, the substrate of the 14th described NMOS tube, described
The source electrode of 11 NMOS tubes, the source electrode of the 12nd described NMOS tube, the source electrode of the 13rd described NMOS tube and described
The source grounding of 14 NMOS tubes；The drain electrode of the 12nd described NMOS tube is the first output end of described power control module,
The drain electrode of the 13rd described NMOS tube and the drain electrode of the 14th described NMOS tube are connected and its connection end is described power control
Second output end of module；
The input of described main latch be described power control single track current-mode d type flip flop input, it is described from
The output end of latch is the output end of described power control single track current-mode d type flip flop, the complementary output from latch
Hold as the complementary output end of described power control single track current-mode d type flip flop, the output end of described main latch and it is described from
The input connection of latch, the bias supply input and the bias supply from latch of described main latch is defeated
Enter end connection and its connection end is the pmos bias power input of described power control single track current-mode d type flip flop, described work(
Control the pmos bias power input access PMOS bias supply signal of single track current-mode d type flip flop, described power control module
Bias supply input be described power control single track current-mode d type flip flop NMOS bias supply inputs, described power control
The NMOS bias supplies input access NMOS tube bias supply signal of single track current-mode d type flip flop, described main latch
Clock end and the clock end connection from latch and it is connected as the clock of described power control single track current-mode d type flip flop
End, the clock of described power control single track current-mode d type flip flop terminates the first clock signal into amplitude level counterlogic 1, institute
The complementary clock end for the main latch stated and the complementary clock end connection from latch and it is connected as described power control
The complementary clock end of single track current-mode d type flip flop, the clock of described power control single track current-mode d type flip flop is terminated into amplitude level
The phase difference 180 of the second clock signal of counterlogic 1, described the first clock signal and described second clock signal
Degree；The power control signal input part of described power control module inputs for the power control signal of described power control single track current-mode d type flip flop
End, the power control signal input part of described power control single track current-mode d type flip flop accesses power control signal.
The first described power supply is 1.2V, and described second source is 1V, described PMOS bias supply signal and institute
The NMOS tube bias supply signal stated is produced by current-mode biasing circuit.
The channel length of the first described NMOS tube, the channel length of the second described NMOS tube, the 3rd described NMOS
The channel length of pipe, the channel length of the 4th described NMOS tube, the channel length of the 5th described NMOS tube, the described the 6th
It is the channel length of NMOS tube, the channel length of the 7th described NMOS tube, the channel length of the 8th described NMOS tube, described
The channel length of 9th NMOS tube, the channel length of the tenth described NMOS tube, the channel length of the 11st described NMOS tube,
The channel length and the 14th described NMOS tube of the channel length of the 12nd described NMOS tube, the 13rd described NMOS tube
Channel length be 1~1.2 times of minimum channel length under NMOS standard technologies, the raceway groove of the first described PMOS is long
Degree, the channel length of the second described PMOS, the channel length of the 3rd described PMOS, the ditch of the 4th described PMOS
The channel length of road length and the 5th described PMOS is 2~2.4 times of minimum channel length under PMOS standard technologies.
The threshold voltage of the first described NMOS tube, the threshold voltage of the second described NMOS tube, the 3rd described NMOS
The threshold voltage of pipe, the threshold voltage of the 4th described NMOS tube, the threshold voltage of the 5th described NMOS tube, the described the 6th
It is the threshold voltage of NMOS tube, the threshold voltage of the 7th described NMOS tube, the threshold voltage of the 8th described NMOS tube, described
The threshold voltage of the threshold voltage of 9th NMOS tube, the threshold voltage of the tenth described NMOS tube and the 11st described NMOS tube
It is 0.1914V, the described threshold voltage of the 12nd NMOS tube and the threshold voltage of the 13rd NMOS tube is 0.3100V,
The threshold voltage of the 14th described NMOS tube is 0.3980V, the threshold voltage of described the first PMOS, described second
The threshold voltage of PMOS, the threshold voltage of the 3rd described PMOS, the threshold voltage of the 4th described PMOS and described
The threshold voltage of the 5th PMOS be -0.2515V.
Compared with prior art, the advantage of the invention is that by the first PMOS, the second PMOS, the first NMOS tube,
Second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute main latch, pass through the 3rd PMOS, the 4th
PMOS, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the tenth NMOS tube are constituted from latch, are led to
Cross the 5th PMOS, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube and the 14th NMOS tube and constitute power control mould
Block, in main latch, the second PMOS constitutes phase inverter with the 5th NMOS tube and produces transmission signal Xb, the first NMOS tube,
Signal X is transmitted in two NMOS tubes, the 3rd NMOS tube, the combinational logic generation of the 4th NMOS tube and the 5th NMOS tubebComplementary signal
X, is achieved in the function of main latch；From latch, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS
Pipe and the combinational logic of the tenth NMOS tube produce output signal Q, realize d type flip flop function；Power control module accesses power control signal
Sleep, when power control signal sleep is low level, the conducting of the 5th PMOS, the cut-off of the 11st NMOS tube, NMOS tube biased electrical
Source signal is connected with the grid of the 12nd NMOS tube and the grid of the 13rd NMOS tube, main latch and normal from latch
Work；When power control signal sleep is high level, the cut-off of the 5th PMOS, the conducting of the 11st NMOS tube, the 12nd NMOS tube
Grid is directly grounded and ended, and conducting loop, in a dormant state, the 13rd NMOS tube from latch is not present in main latch
Cut-off, the 14th NMOS tube is connected with NMOS tube bias supply signal, makes still normally to preserve latch data from latch；Thus
Opened or cut-out main latch, reduced well in d type flip flop with replacing under idle condition in work by power control module
Leakage power consumption, delay, power consumption and the power consumption of integrated circuit-delay product are significantly reduced, under low frequency and high frequency service condition
Less delay, power consumption and power consumption-delay product are respectively provided with, the performance of d type flip flop is improved；
When the first power supply is 1.2V, second source is 1V, NMOS tube bias supply signal and PMOS bias supply signal
When being produced by current-mode biasing circuit, can reduce from latch continuous firing when the leakage current that produces, maintain main latch
Operating rate；
Channel length, the channel length of the second NMOS tube, the channel length of the 3rd NMOS tube when the first NMOS tube, the 4th
The channel length of NMOS tube, the channel length of the 5th NMOS tube, the channel length of the 6th NMOS tube, the 7th NMOS tube raceway groove it is long
Degree, the channel length of the 8th NMOS tube, the channel length of the 9th NMOS tube, the channel length of the tenth NMOS tube, the 11st NMOS
The channel length of pipe, the channel length of the 12nd NMOS tube, the ditch of the channel length of the 13rd NMOS tube and the 14th NMOS tube
Road length is 1~1.2 times of minimum channel length under NMOS standard technologies, the channel length of the first PMOS, the 2nd PMOS
The channel length of pipe, the channel length of the 3rd PMOS, the channel length of the channel length of the 4th PMOS and the 5th PMOS
When being 2~2.4 times of minimum channel length under PMOS standard technologies, the resistance of d type flip flop can be reduced, d type flip flop is improved
The speed of service；
Threshold voltage, the threshold voltage of the second NMOS tube, the threshold voltage of the 3rd NMOS tube when the first NMOS tube, the 4th
The threshold voltage of NMOS tube, the threshold voltage of the 5th NMOS tube, the threshold voltage of the 6th NMOS tube, the threshold value electricity of the 7th NMOS tube
Pressure, the threshold voltage of the 8th NMOS tube, the threshold voltage of the 9th NMOS tube, the threshold voltage and the 11st NMOS of the tenth NMOS tube
The threshold voltage of pipe is 0.1914V, and the threshold voltage of the 12nd NMOS tube and the threshold voltage of the 13rd NMOS tube are
0.3100V, the threshold voltage of the 14th NMOS tube is 0.3980V, the threshold voltage of the first PMOS, the threshold value of the second PMOS
Voltage, the threshold voltage of the 3rd PMOS, the threshold voltage of the 4th PMOS and the threshold voltage of the 5th PMOS be-
During 0.2515V, main latch and the transistor from latch are realized using the transistor of Low threshold, for ensureing the property of circuit
Can, power control module is realized using the transistor of middle and high threshold value, for the leakage current of further reduction d type flip flop, so that further
Low leakage power consumption drops.
Brief description of the drawings
Fig. 1 is the circuit diagram of traditional hypotactic edge D flip-flops of static CMOS；
Fig. 2 is the circuit diagram of existing single track current-mode d type flip flop；
Fig. 3 is the circuit diagram of the power control single track current-mode d type flip flop of the present invention；
Simulation waveforms of the Fig. 4 for power control single track current-mode d type flip flop of the invention under SMIC130nm standard technologies.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment one：As shown in figure 3, a kind of power control single track current-mode d type flip flop, including main latch, from latch and
Power control module；Main latch includes the first PMOS P1, the second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd
NMOS tube N3, the 4th NMOS tube N4 and the 5th NMOS tube N5；First PMOS P1 source electrode, the second PMOS P2 source electrode,
One PMOS P1 substrate and the second PMOS P2 substrate are connected and its connection end is the power end of main latch, main latch
Power end access the first power supply VDD, the first PMOS P1 drain electrode, the first NMOS tube N1 drain electrode, the 3rd NMOS tube N3 leakage
Pole and the 5th NMOS tube N5 grid connection and its connection end are the output end of main latch, the second PMOS P2 drain electrode, the
The drain electrode connection of three NMOS tube N3 grid and the 5th NMOS tube N5, the first NMOS tube N1 source electrode and the second NMOS tube N2 leakage
Pole is connected, the drain electrode connection of the 3rd NMOS tube N3 source electrode and the 4th NMOS tube N4, the first PMOS P1 grid and second
PMOS P2 grid connection and its connection end are the bias supply input of main latch, the second NMOS tube N2 source electrode, the
Four NMOS tube N4 source electrode and the 5th NMOS tube N5 source electrode are connected and its connection end is the control signal input of main latch,
First NMOS tube N1 grid is the input of main latch, and the second NMOS tube N2 grid is the clock signal of main latch
End, the 4th NMOS tube N4 grid is the complementary clock signal end of main latch；First NMOS tube N1 substrate, the second NMOS tube
N2 substrate, the 3rd NMOS tube N3 substrate, the 4th NMOS tube N4 substrate and the 5th NMOS tube N5 substrate are grounded；
Include the 3rd PMOS P3, the 4th PMOS P4, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th from latch
NMOS tube N8, the 9th NMOS tube N9 and the tenth NMOS tube N10；3rd PMOS P3 source electrode, the 4th PMOS P4 source electrode,
Three PMOS P3 substrate and the 4th PMOS P4 substrate connection and its connection end are the power end from latch, from latch
Power end access second source VDD1, the 3rd PMOS P3 grid and the 4th PMOS P4 grid are connected and its connection end
For from the bias supply input of latch, the 3rd PMOS P3 drain electrode, the 6th NMOS tube N6 drain electrode, the 8th NMOS tube N8
Drain electrode and the tenth NMOS tube N10 grid connection and its connection end is from the output end of latch, the 4th PMOS P4 leakage
Pole, the 8th NMOS tube N8 grid and the tenth NMOS tube N10 drain electrode connection and its connection end are the complementary output from latch
End, the drain electrode connection of the 6th NMOS tube N6 source electrode and the 7th NMOS tube N7, the 8th NMOS tube N8 source electrode and the 9th NMOS tube
N9 drain electrode connection, the source electrode connection of the 7th NMOS tube N7 source electrode, the 9th NMOS tube N9 source electrode and the tenth NMOS tube N10 and
Its connection end is the 6th NMOS tube N6 substrate, the 7th NMOS tube N7 substrate, the 8th from the control signal input of latch
The substrate of NMOS tube N8 substrate, the 9th NMOS tube N9 substrate and the tenth NMOS tube N10 is grounded, the 6th NMOS tube N6 grid
Extremely from the input of latch, the 7th NMOS tube N7 grid be from the complementary clock end of latch, the 9th NMOS tube N9's
Grid is from the clock end of latch；
Power control module includes the 5th PMOS P5, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube
N13 and the 14th NMOS tube N14；5th PMOS P5 drain electrode, the 11st NMOS tube N11 drain, the 12nd NMOS tube N12
Grid and the 13rd NMOS tube N13 grid connection, the 5th PMOS P5 source electrode and the 14th NMOS tube N14 grid connects
Connect and its connection end be power control module bias supply input, the 5th PMOS P5 grid and the 11st NMOS tube N11's
Grid is connected and its connection end is the power control signal input part of power control module, the 5th PMOS P5 substrate access NMOS tube biasing
Power supply signal Vrfn, the 11st NMOS tube N11 substrate, the 12nd NMOS tube N12 substrate, the 13rd NMOS tube N13 lining
Bottom, the 14th NMOS tube N14 substrate, the 11st NMOS tube N11 source electrode, the 12nd NMOS tube N12 source electrode, the 13rd
The source grounding of NMOS tube N13 source electrode and the 14th NMOS tube N14；12nd NMOS tube N12 drain electrode is power control module
The first output end, the 13rd NMOS tube N13 drain electrode and the 14th NMOS tube N14 drain electrode connection and its connection end be power control
Second output end of module；
The input of main latch is the input of power control single track current-mode d type flip flop, is work(from the output end of latch
The output end of single track current-mode d type flip flop is controlled, from the complementation that the complementary output end of latch is power control single track current-mode d type flip flop
Output end, the output end of main latch and is connected from the input of latch, the bias supply input of main latch and from lock
The bias supply input of storage is connected and its connection end is the pmos bias power input of power control single track current-mode d type flip flop
End, the pmos bias power input access PMOS bias supply signal V of power control single track current-mode d type flip floprfp, power control mould
The bias supply input of block is the NMOS bias supply inputs of power control single track current-mode d type flip flop, power control single track current-mode D
The NMOS bias supplies input access NMOS tube bias supply signal V of triggerrfn, the clock end of main latch and from latch
The clock end connection of device and it is connected as the clock end of power control single track current-mode d type flip flop, power control single track current-mode d type flip flop
Clock terminates the first clock signal into amplitude level counterlogic 1, the complementary clock end of main latch and from the mutual of latch
Complement clock end is connected and it is connected as the complementary clock end of power control single track current-mode d type flip flop, power control single track current-mode d type flip flop
Clock terminate the phase of second clock signal into amplitude level counterlogic 1, the first clock signal and second clock signal
Differ 180 degree；The power control signal input part of power control module is the power control signal input part of power control single track current-mode d type flip flop, work(
Control the power control signal input part access power control signal of single track current-mode d type flip flop.
In the present embodiment, the first power supply VDDFor 1.2V, second source VDD1For 1V, NMOS tube bias supply signal VrfnWith
PMOS bias supply signal VrfpProduced by existing normalized current mould biasing circuit, PMOS bias supply signal VrfpAbout
For -0.68V, NMOS tube bias supply signal VrfnAbout 1.1V.
In the present embodiment, the first NMOS tube N1 channel length, the second NMOS tube N2 channel length, the 3rd NMOS tube N3
Channel length, the 4th NMOS tube N4 channel length, the 5th NMOS tube N5 channel length, the 6th NMOS tube N6 raceway groove it is long
Degree, the 7th NMOS tube N7 channel length, the 8th NMOS tube N8 channel length, the 9th NMOS tube N9 channel length, the tenth
NMOS tube N10 channel length, the 11st NMOS tube N11 channel length, the 12nd NMOS tube N12 channel length, the tenth
Three NMOS tube N13 channel length and the 14th NMOS tube N14 channel length be under NMOS standard technologies minimum channel it is long
Degree 1.2 times, the first PMOS P1 channel length, the second PMOS P2 channel length, the 3rd PMOS P3 raceway groove it is long
Degree, the 4th PMOS P4 channel length and the 5th PMOS P5 channel length be under PMOS standard technologies minimum channel it is long
2.4 times of degree.
In the present embodiment, the first NMOS tube N1 threshold voltage, the second NMOS tube N2 threshold voltage, the 3rd NMOS tube N3
Threshold voltage, the 4th NMOS tube N4 threshold voltage, the 5th NMOS tube N5 threshold voltage, the 6th NMOS tube N6 threshold value electricity
Pressure, the 7th NMOS tube N7 threshold voltage, the 8th NMOS tube N8 threshold voltage, the 9th NMOS tube N9 threshold voltage, the tenth
NMOS tube N10 threshold voltage and the 11st NMOS tube N11 threshold voltage are 0.1914V, the 12nd NMOS tube N12 threshold
Threshold voltage and the 13rd NMOS tube N13 threshold voltage are 0.3100V, and the 14th NMOS tube N14 threshold voltage is
0.3980V, the first PMOS P1 threshold voltage, the second PMOS P2 threshold voltage, the 3rd PMOS P3 threshold voltage,
4th PMOS P4 threshold voltage and the 5th PMOS P5 threshold voltage are -0.2515V.
Embodiment two：As shown in figure 3, a kind of power control single track current-mode d type flip flop, including main latch, from latch and
Power control module；Main latch includes the first PMOS P1, the second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd
NMOS tube N3, the 4th NMOS tube N4 and the 5th NMOS tube N5；First PMOS P1 source electrode, the second PMOS P2 source electrode,
One PMOS P1 substrate and the second PMOS P2 substrate are connected and its connection end is the power end of main latch, main latch
Power end access the first power supply VDD, the first PMOS P1 drain electrode, the first NMOS tube N1 drain electrode, the 3rd NMOS tube N3 leakage
Pole and the 5th NMOS tube N5 grid connection and its connection end are the output end of main latch, the second PMOS P2 drain electrode, the
The drain electrode connection of three NMOS tube N3 grid and the 5th NMOS tube N5, the first NMOS tube N1 source electrode and the second NMOS tube N2 leakage
Pole is connected, the drain electrode connection of the 3rd NMOS tube N3 source electrode and the 4th NMOS tube N4, the first PMOS P1 grid and second
PMOS P2 grid connection and its connection end are the bias supply input of main latch, the second NMOS tube N2 source electrode, the
Four NMOS tube N4 source electrode and the 5th NMOS tube N5 source electrode are connected and its connection end is the control signal input of main latch,
First NMOS tube N1 grid is the input of main latch, and the second NMOS tube N2 grid is the clock signal of main latch
End, the 4th NMOS tube N4 grid is the complementary clock signal end of main latch；First NMOS tube N1 substrate, the second NMOS tube
N2 substrate, the 3rd NMOS tube N3 substrate, the 4th NMOS tube N4 substrate and the 5th NMOS tube N5 substrate are grounded；
Include the 3rd PMOS P3, the 4th PMOS P4, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th from latch
NMOS tube N8, the 9th NMOS tube N9 and the tenth NMOS tube N10；3rd PMOS P3 source electrode, the 4th PMOS P4 source electrode,
Three PMOS P3 substrate and the 4th PMOS P4 substrate connection and its connection end are the power end from latch, from latch
Power end access second source VDD1, the 3rd PMOS P3 grid and the 4th PMOS P4 grid are connected and its connection end
For from the bias supply input of latch, the 3rd PMOS P3 drain electrode, the 6th NMOS tube N6 drain electrode, the 8th NMOS tube N8
Drain electrode and the tenth NMOS tube N10 grid connection and its connection end is from the output end of latch, the 4th PMOS P4 leakage
Pole, the 8th NMOS tube N8 grid and the tenth NMOS tube N10 drain electrode connection and its connection end are the complementary output from latch
End, the drain electrode connection of the 6th NMOS tube N6 source electrode and the 7th NMOS tube N7, the 8th NMOS tube N8 source electrode and the 9th NMOS tube
N9 drain electrode connection, the source electrode connection of the 7th NMOS tube N7 source electrode, the 9th NMOS tube N9 source electrode and the tenth NMOS tube N10 and
Its connection end is the 6th NMOS tube N6 substrate, the 7th NMOS tube N7 substrate, the 8th from the control signal input of latch
The substrate of NMOS tube N8 substrate, the 9th NMOS tube N9 substrate and the tenth NMOS tube N10 is grounded, the 6th NMOS tube N6 grid
Extremely from the input of latch, the 7th NMOS tube N7 grid be from the complementary clock end of latch, the 9th NMOS tube N9's
Grid is from the clock end of latch；
Power control module includes the 5th PMOS P5, the 11st NMOS tube N11, the 12nd NMOS tube N12, the 13rd NMOS tube
N13 and the 14th NMOS tube N14；5th PMOS P5 drain electrode, the 11st NMOS tube N11 drain, the 12nd NMOS tube N12
Grid and the 13rd NMOS tube N13 grid connection, the 5th PMOS P5 source electrode and the 14th NMOS tube N14 grid connects
Connect and its connection end be power control module bias supply input, the 5th PMOS P5 grid and the 11st NMOS tube N11's
Grid is connected and its connection end is the power control signal input part of power control module, the 5th PMOS P5 substrate access NMOS tube biasing
Power supply signal Vrfn, the 11st NMOS tube N11 substrate, the 12nd NMOS tube N12 substrate, the 13rd NMOS tube N13 lining
Bottom, the 14th NMOS tube N14 substrate, the 11st NMOS tube N11 source electrode, the 12nd NMOS tube N12 source electrode, the 13rd
The source grounding of NMOS tube N13 source electrode and the 14th NMOS tube N14；12nd NMOS tube N12 drain electrode is power control module
The first output end, the 13rd NMOS tube N13 drain electrode and the 14th NMOS tube N14 drain electrode connection and its connection end be power control
Second output end of module；
The input of main latch is the input of power control single track current-mode d type flip flop, is work(from the output end of latch
The output end of single track current-mode d type flip flop is controlled, from the complementation that the complementary output end of latch is power control single track current-mode d type flip flop
Output end, the output end of main latch and is connected from the input of latch, the bias supply input of main latch and from lock
The bias supply input of storage is connected and its connection end is the pmos bias power input of power control single track current-mode d type flip flop
End, the pmos bias power input access PMOS bias supply signal V of power control single track current-mode d type flip floprfp, power control mould
The bias supply input of block is the NMOS bias supply inputs of power control single track current-mode d type flip flop, power control single track current-mode D
The NMOS bias supplies input access NMOS tube bias supply signal V of triggerrfn, the clock end of main latch and from latch
The clock end connection of device and it is connected as the clock end of power control single track current-mode d type flip flop, power control single track current-mode d type flip flop
Clock terminates the first clock signal into amplitude level counterlogic 1, the complementary clock end of main latch and from the mutual of latch
Complement clock end is connected and it is connected as the complementary clock end of power control single track current-mode d type flip flop, power control single track current-mode d type flip flop
Clock terminate the phase of second clock signal into amplitude level counterlogic 1, the first clock signal and second clock signal
Differ 180 degree；The power control signal input part of power control module is the power control signal input part of power control single track current-mode d type flip flop, work(
Control the power control signal input part access power control signal of single track current-mode d type flip flop.
In the present embodiment, the first power supply VDDFor 1.2V, second source VDD1For 1V, NMOS tube bias supply signal VrfnWith
PMOS bias supply signal VrfpProduced by existing normalized current mould biasing circuit, PMOS bias supply signal VrfpAbout
For -0.68V, NMOS tube bias supply signal VrfnAbout 1.1V.
In the present embodiment, the first NMOS tube N1 channel length, the second NMOS tube N2 channel length, the 3rd NMOS tube N3
Channel length, the 4th NMOS tube N4 channel length, the 5th NMOS tube N5 channel length, the 6th NMOS tube N6 raceway groove it is long
Degree, the 7th NMOS tube N7 channel length, the 8th NMOS tube N8 channel length, the 9th NMOS tube N9 channel length, the tenth
NMOS tube N10 channel length, the 11st NMOS tube N11 channel length, the 12nd NMOS tube N12 channel length, the tenth
Three NMOS tube N13 channel length and the 14th NMOS tube N14 channel length be under NMOS standard technologies minimum channel it is long
Degree 1 times, the first PMOS P1 channel length, the second PMOS P2 channel length, the 3rd PMOS P3 channel length,
4th PMOS P4 channel length and the 5th PMOS P5 channel length are minimum channel length under PMOS standard technologies
2 times.
In the present embodiment, the first NMOS tube N1 threshold voltage, the second NMOS tube N2 threshold voltage, the 3rd NMOS tube N3
Threshold voltage, the 4th NMOS tube N4 threshold voltage, the 5th NMOS tube N5 threshold voltage, the 6th NMOS tube N6 threshold value electricity
Pressure, the 7th NMOS tube N7 threshold voltage, the 8th NMOS tube N8 threshold voltage, the 9th NMOS tube N9 threshold voltage, the tenth
NMOS tube N10 threshold voltage and the 11st NMOS tube N11 threshold voltage are 0.1914V, the 12nd NMOS tube N12 threshold
Threshold voltage and the 13rd NMOS tube N13 threshold voltage are 0.3100V, and the 14th NMOS tube N14 threshold voltage is
0.3980V, the first PMOS P1 threshold voltage, the second PMOS P2 threshold voltage, the 3rd PMOS P3 threshold voltage,
4th PMOS P4 threshold voltage and the 5th PMOS P5 threshold voltage are -0.2515V.
The present invention operation principle be：When power control signal sleep is low level, the 5th PMOS P5 conductings, the 11st
NMOS tube N11 ends, now NMOS tube bias supply signal VrfnWith the 12nd NMOS tube N12 grid and the 13rd NMOS tube
N13 grid is connected, main latch, from latch and power control module normal work；When power control signal sleep is high level
When, the 5th PMOS P5 cut-offs, the 11st NMOS tube N11 conductings, the 12nd NMOS tube N12 grid is directly grounded and ended,
Conducting loop is not present in main latch, in a dormant state, and the 13rd NMOS tube N13 ends from latch, the 14th NMOS
Pipe N14 is in NMOS tube bias supply signal VrfnIn the presence of conducting make still normally to preserve latch data from latch, thus,
Opened or cut-out main latch, reduced well in d type flip flop with replacing under idle condition in work by power control module
Leakage power consumption, significantly reduce delay, power consumption and the power consumption of integrated circuit-delay product.
Under SMIC130nm standard technologies, the power control single track current-mode d type flip flop of the present invention is emulated, it is emulated
Oscillogram is as shown in figure 4, as can be seen from Figure 4, power control single track current-mode d type flip flop of the invention has correct logic function.
In order to verify the present invention low delay of the power control single track current-mode d type flip flop under low frequency and high frequency service condition,
Low-power consumption and low-power consumption-delay product characteristic, trigger the power control single track current-mode D of the present invention under SMIC130nm standard technologies
The performance of device and traditional static CMOS D master-slave flip-flop and existing single track current-mode d type flip flop is compared.Use circuit
Emulation tool HSPICE is touched under conditions of incoming frequency is 100MHz, 800MHz, 1.2GHz, 1.8GHz, 2GHz to three kinds of D
Hair device structure has carried out Comparative Simulation, and the first power supply is 1.2V, and second source is 1V, and the 12nd NMOS tube N12 width is long
Than for the λ (λ=65nm) of W/L=8 λ/6, the 13rd NMOS tube N13 breadth length ratio is W/L=8 λ/10 λ, the 14th NMOS tube N14
Breadth length ratio be the λ of W/L=8 λ/10, power control signal sleep activity factor α is 0.5.The power control single track current-mode D of the present invention
Trigger show that current data is as shown in table 1 in SMIC130nm standard technologies, incoming frequency when being 100MHz.
Current data of the power control single track current-mode d type flip flop of the present invention of table 1 in 100MHz
As can be drawn from Table 1：The power control single track current-mode d type flip flop of the present invention is total in main latch working condition
Electric current is 14uA, and power consumption is 16uW；Main latch in a dormant state when total current be 3.6uA, power consumption is 3.6uW, institute
Using the power consumption of whole cycle as 19.6uW.
In SMIC130nm standard technologies, incoming frequency be power control single track current-mode d type flip flop of the invention under 100MHz with
The performance comparision of single track current-mode d type flip flop and traditional static CMOS D master-slave flip-flops is as shown in table 2.
The performance of three kinds of d type flip flops during 2 100MHz of table
| Circuit types | It is delayed (ns) | Average total power consumption (μ W) | Power consumption-delay product (pJ) |
| Power control single track current-mode d type flip flop | 0.21 | 1.96 | 0.4116 |
| Single track current-mode d type flip flop | 0.23 | 2.34 | 0.5382 |
| Traditional static CMOS D master-slave flip-flops | 0.35 | 0.85 | 0.2975 |
As can be drawn from Table 2：Power control single track current-mode d type flip flop and the single track current-mode d type flip flop of the present invention and
Traditional static CMOS D master-slave flip-flops are compared under SMIC130nm standard technologies, and delay reduces 8% and 42% respectively, average
Total power consumption reduces 17% and rises 56.6% respectively, and power consumption-time delay integration does not reduce 23.5% and rises 27.7%.
In SMIC130nm standard technologies, incoming frequency be power control single track current-mode d type flip flop of the invention under 800MHz with
The performance comparision of single track current-mode d type flip flop and traditional static CMOS D master-slave flip-flops is as shown in table 3.
The performance of three kinds of d type flip flops during 3 800MHz of table
| Circuit types | It is delayed (ns) | Average total power consumption (μ W) | Power consumption-delay product (pJ) |
| Power control single track current-mode d type flip flop | 0.21 | 1.96 | 0.4116 |
| Single track current-mode d type flip flop | 0.25 | 2.35 | 0.5875 |
| Traditional static CMOS D master-slave flip-flops | 0.36 | 1.83 | 0.6588 |
As can be drawn from Table 3：Power control single track current-mode d type flip flop and the single track current-mode d type flip flop of the present invention and
Traditional static CMOS D master-slave flip-flops are compared under SMIC130nm standard technologies, and delay reduces 16% and 42% respectively, are put down
Equal total power consumption reduces 17% and rises 6% respectively, and power consumption-time delay integration does not reduce 30% and 37.5%.
In SMIC130nm standard technologies, incoming frequency be power control single track current-mode d type flip flop of the invention under 1.2GHz with
The performance comparision of single track current-mode d type flip flop and traditional static CMOS D master-slave flip-flops is as shown in table 4.
The performance of three kinds of d type flip flops during 4 1.2GHz of table
| Circuit types | It is delayed (ns) | Average total power consumption (μ W) | Power consumption-delay product (pJ) |
| Power control single track current-mode d type flip flop | 0.21 | 1.96 | 0.4116 |
| Single track current-mode d type flip flop | 0.24 | 2.35 | 0.5641 |
| Traditional static CMOS D master-slave flip-flops | 0.35 | 2.61 | 0.9135 |
As can be drawn from Table 4：Power control single track current-mode d type flip flop and the single track current-mode d type flip flop of the present invention and
Traditional static CMOS D master-slave flip-flops are compared under SMIC130nm standard technologies, and delay reduces 12.5% and 42% respectively,
Average total power consumption reduces 16.6% and 40% respectively, and power consumption-time delay integration does not reduce 27% and 50.2%.
In SMIC130nm standard technologies, incoming frequency be power control single track current-mode d type flip flop of the invention under 1.8GHz with
The performance comparision of single track current-mode d type flip flop and traditional static CMOS D master-slave flip-flops is as shown in table 5.
The performance of three kinds of d type flip flops during 5 1.8GHz of table
| Circuit types | It is delayed (ns) | Average total power consumption (μ W) | Power consumption-delay product (pJ) |
| Power control single track current-mode d type flip flop | 0.21 | 1.96 | 0.4116 |
| Single track current-mode d type flip flop | 0.24 | 2.35 | 0.5641 |
| Traditional static CMOS D master-slave flip-flops | 0.36 | 5.3 | 1.908 |
As can be drawn from Table 5：Power control single track current-mode d type flip flop and the single track current-mode d type flip flop of the present invention and
Traditional static CMOS D master-slave flip-flops are compared under SMIC130nm standard technologies, and delay reduces 12.5% and 42% respectively,
Average total power consumption reduces 16.5% and 63% respectively, and power consumption-time delay integration does not reduce 27% and 67.5%.
In SMIC130nm standard technologies, incoming frequency be power control single track current-mode d type flip flop of the invention under 1.8GHz with
The performance comparision of single track current-mode d type flip flop and traditional static CMOS D master-slave flip-flops is as shown in table 6.
The performance of three kinds of d type flip flops during 6 2GHz of table
| Circuit types | It is delayed (ns) | Average total power consumption (μ W) | Power consumption-delay product (pJ) |
| Power control single track current-mode d type flip flop | 0.21 | 1.96 | 0.4116 |
| Single track current-mode d type flip flop | 0.24 | 2.35 | 0.5641 |
| Traditional static CMOS D master-slave flip-flops | 0.36 | 5.8 | 2.088 |
As can be drawn from Table 6：As can be drawn from Table 6：The power control single track current-mode d type flip flop of the present invention and single track electricity
Stream mould d type flip flop and traditional static CMOS D master-slave flip-flops are compared under SMIC130nm standard technologies, and delay is reduced respectively
12.5% and 42%, average total power consumption reduces 16.5% and 66% respectively, power consumption-time delay integration do not reduce 27% and
80%.
From above-mentioned comparison data, on the premise of circuit performance is not influenceed, power control single track proposed by the invention
Current-mode d type flip flop has reduction electricity compared with both the above single track current-mode d type flip flop and traditional static CMOS D master-slave flip-flops
Power consumption is leaked on road, and small, the average total power consumption that is delayed is low and less advantage is accumulated in power consumption-delay.
Claims (4)
1. a kind of power control single track current-mode d type flip flop, it is characterised in that including main latch, from latch and power control module；
Described main latch include the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube,
4th NMOS tube and the 5th NMOS tube；The source electrode of the first described PMOS, the source electrode of the second described PMOS, described
The substrate of one PMOS and the substrate of the second described PMOS are connected and its connection end is the power end of described main latch,
The power end of described main latch accesses the first power supply, the draining of described the first PMOS, described the first NMOS tube
The grid of drain electrode, the drain electrode of the 3rd described NMOS tube and the 5th described NMOS tube is connected and its connection end is described main lock
The output end of storage, the draining of described the second PMOS, the grid of the 3rd described NMOS tube and the 5th described NMOS tube
Drain electrode connection, the drain electrode connection of the source electrode of described the first NMOS tube and the second described NMOS tube, the 3rd described NMOS
The drain electrode connection of the source electrode of pipe and the 4th described NMOS tube, the grid and the second described PMOS of described the first PMOS
Grid connection and its connection end be described main latch bias supply input, the source electrode of described the second NMOS tube,
The source electrode of the 4th described NMOS tube and the source electrode of the 5th described NMOS tube are connected and its connection end is described main latch
Control signal input, the grid of described the first NMOS tube is the input of described main latch, described second
The grid of NMOS tube is the clock signal terminal of described main latch, and the grid of the 4th described NMOS tube is described main latch
The complementary clock signal end of device；The substrate of the first described NMOS tube, the substrate of the second described NMOS tube, the described the 3rd
The substrate of the substrate of NMOS tube, the substrate of the 4th described NMOS tube and the 5th described NMOS tube is grounded；
It is described from latch include the 3rd PMOS, the 4th PMOS, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube,
9th NMOS tube and the tenth NMOS tube；The source electrode of the 3rd described PMOS, the source electrode of the 4th described PMOS, described
The substrate of three PMOSs and the substrate of the 4th described PMOS are connected and its connection end is the power end from latch,
The described power end from latch accesses second source, the grid of described the 3rd PMOS and the 4th described PMOS
Grid is connected and its connection end is the bias supply input from latch, the drain electrode of described the 3rd PMOS, institute
The grid connection of the draining of the 6th NMOS tube stated, the drain electrode of the 8th described NMOS tube and the tenth described NMOS tube and its connect
It is the output end from latch to connect end, the draining of described the 4th PMOS, the grid of the 8th described NMOS tube and
The drain electrode of the tenth described NMOS tube is connected and its connection end is the complementary output end from latch, the described the 6th
The drain electrode connection of the source electrode of NMOS tube and the 7th described NMOS tube, the source electrode and the described the 9th of described the 8th NMOS tube
The drain electrode connection of NMOS tube, the source electrode of described the 7th NMOS tube, the source electrode and the described the tenth of the 9th described NMOS tube
The source electrode connection of NMOS tube and its connection end is the control signal input from latch, described the 6th NMOS tube
Substrate, the substrate of the 7th described NMOS tube, the substrate of the 8th described NMOS tube, the substrate of the 9th described NMOS tube and institute
The substrate for the tenth NMOS tube stated is grounded, and the grid of the 6th described NMOS tube is the input from latch, institute
The grid for the 7th NMOS tube stated is the complementary clock end from latch, and the grid of the 9th described NMOS tube is described
The clock end from latch；
Described power control module includes the 5th PMOS, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube and the tenth
Four NMOS tubes；The draining of the 5th described PMOS, the drain of the 11st described NMOS tube, described the 12nd NMOS tube
Grid and the connection of the grid of the 13rd described NMOS tube, the source electrode and the 14th described NMOS tube of described the 5th PMOS
Grid connection and its connection end be described power control module bias supply input, the grid of described the 5th PMOS and
The grid of the 11st described NMOS tube is connected and its connection end is the power control signal input part of described power control module, described
The substrate access NMOS tube bias supply signal of 5th PMOS, the substrate of described the 11st NMOS tube, the described the 12nd
The substrate of NMOS tube, the substrate of the 13rd described NMOS tube, the substrate of the 14th described NMOS tube, the described the 11st
The source electrode of NMOS tube, the source electrode of the 12nd described NMOS tube, the source electrode and the described the 14th of the 13rd described NMOS tube
The source grounding of NMOS tube；The drain electrode of the 12nd described NMOS tube is the first output end of described power control module, described
The 13rd NMOS tube drain electrode and the drain electrode connection of described the 14th NMOS tube and its connection end is described power control module
The second output end；
The input of described main latch is the input of described power control single track current-mode d type flip flop, described from latch
The output end of device is the output end of described power control single track current-mode d type flip flop, described to be from the complementary output end of latch
The complementary output end of described power control single track current-mode d type flip flop, the output end of described main latch and described from latch
The input connection of device, the bias supply input and the bias supply input from latch of described main latch
Connect and its connection end is the pmos bias power input of described power control single track current-mode d type flip flop, described power control list
The pmos bias power input access PMOS bias supply signal of rail current-mode d type flip flop, described power control module it is inclined
Put the NMOS bias supply inputs that power input is described power control single track current-mode d type flip flop, described power control single track
The NMOS bias supplies input access NMOS tube bias supply signal of current-mode d type flip flop, the clock of described main latch
End and the clock end connection from latch and it is connected as the clock end of described power control single track current-mode d type flip flop,
The clock of described power control single track current-mode d type flip flop terminates the first clock signal into amplitude level counterlogic 1, described
The complementary clock end of main latch and the complementary clock end connection from latch and it is connected as described power control single track
The complementary clock end of current-mode d type flip flop, the clock of described power control single track current-mode d type flip flop is terminated into amplitude level correspondence
The phase difference 180 degree of the second clock signal of logic 1, described the first clock signal and described second clock signal；Institute
The power control signal input part for the power control module stated is the power control signal input part of described power control single track current-mode d type flip flop, institute
The power control signal input part access power control signal for the power control single track current-mode d type flip flop stated.
2. a kind of power control single track current-mode d type flip flop according to claim 1, it is characterised in that the first described power supply is
1.2V, described second source is 1V, and described PMOS bias supply signal and described NMOS tube bias supply signal are equal
Produced by current-mode biasing circuit.
3. a kind of power control single track current-mode d type flip flop according to claim 1, it is characterised in that the first described NMOS tube
Channel length, the channel length of described second NMOS tube, the channel length of the 3rd described NMOS tube, the described the 4th
It is the channel length of NMOS tube, the channel length of the 5th described NMOS tube, the channel length of the 6th described NMOS tube, described
The channel length of 7th NMOS tube, the channel length of the 8th described NMOS tube, the channel length of the 9th described NMOS tube, institute
The channel length for the tenth NMOS tube stated, the channel length of the 11st described NMOS tube, the ditch of the 12nd described NMOS tube
The channel length of road length, the channel length of the 13rd described NMOS tube and the 14th described NMOS tube is NMOS standards
1~1.2 times of minimum channel length under technique, the channel length of described the first PMOS, the ditch of the second described PMOS
Road length, the channel length of the 3rd described PMOS, the channel length of the 4th described PMOS and the 5th described PMOS
The channel length of pipe is 2~2.4 times of minimum channel length under PMOS standard technologies.
4. a kind of power control single track current-mode d type flip flop according to claim 1, it is characterised in that the first described NMOS tube
Threshold voltage, the threshold voltage of described second NMOS tube, the threshold voltage of the 3rd described NMOS tube, the described the 4th
It is the threshold voltage of NMOS tube, the threshold voltage of the 5th described NMOS tube, the threshold voltage of the 6th described NMOS tube, described
The threshold voltage of 7th NMOS tube, the threshold voltage of the 8th described NMOS tube, the threshold voltage of the 9th described NMOS tube, institute
The threshold voltage for the tenth NMOS tube stated and the threshold voltage of the 11st described NMOS tube are 0.1914V, and the described the tenth
The threshold voltage of two NMOS tubes and the threshold voltage of the 13rd described NMOS tube are 0.3100V, the 14th described NMOS tube
Threshold voltage be 0.3980V, the threshold voltage of described the first PMOS, the threshold voltage of the second described PMOS, institute
The threshold value electricity of the threshold voltage for the 3rd PMOS stated, the threshold voltage of the 4th described PMOS and the 5th described PMOS
Pressure is -0.2515V.
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| CN105141290A (en) | 2015-12-09 |
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