CN107196627B - Current mode D trigger based on FinFET device - Google Patents

Current mode D trigger based on FinFET device Download PDF

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CN107196627B
CN107196627B CN201710259231.8A CN201710259231A CN107196627B CN 107196627 B CN107196627 B CN 107196627B CN 201710259231 A CN201710259231 A CN 201710259231A CN 107196627 B CN107196627 B CN 107196627B
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type finfet
tube
type
finfet
flip
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CN107196627A (en
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胡建平
熊阳
柏文敬
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Ningbo University
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Ningbo University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Abstract

The invention discloses a current mode D trigger based on FinFET devices, which comprises a first P type FinFET tube, a second P type FinFET tube, a third P type FinFET tube, a fourth P type FinFET tube, a first N type FinFET tube, a second N type FinFET tube, a third N type FinFET tube, a fourth N type FinFET tube, a fifth N type FinFET tube, a sixth N type FinFET tube, a seventh N type FinFET tube and an eighth N type FinFET tube; the advantage is that circuit area, time delay, power consumption and power consumption delay product are all less.

Description

Current mode D trigger based on FinFET device
Technical Field
The present disclosure relates to current mode D flip-flops, and particularly to a current mode D flip-flop based on a FinFET device.
Background
As transistor dimensions continue to shrink, the space for the common CMOS transistor size reduction is greatly reduced due to short channel effects and current manufacturing process limitations. When the size of a common CMOS transistor is reduced to below 20nm, the leakage current of the device is increased sharply, and larger circuit leakage power consumption is caused. Moreover, the short channel effect of the circuit becomes more obvious, the device becomes quite unstable, and the improvement of the circuit performance is greatly limited. A FinFET (Fin-Field-Effect Transistor) is a new complementary metal-oxide-semiconductor (CMOS) Transistor, a new type of 3D Transistor, and is widely used in current circuit design. The channel of the FinFET tube is zero-doped or low-doped, and the channel is surrounded by three sides of the gate. The special three-dimensional structure enhances the control strength of the gate to the channel, greatly inhibits the short channel effect and inhibits the leakage current of the device. The FinFET has the advantages of low power consumption and small area, and gradually becomes one of excellent devices which take over the common CMOS devices and continue the Moore's law.
The flip-flop is widely used in large-scale integrated circuit design as a basic operation unit of a digital circuit system, and the performance of the flip-flop has a particularly important influence on the performance of the whole system in a microprocessor and a single chip microcomputer system with higher performance requirements. D flip-flop is a type of flip-flop that is commonly used in digital circuitry. At present, FinFET devices are applied to the design field of D triggers.
A circuit structure of a current mode D flip-flop based on a CMOS device is shown in fig. 1. The current mode D trigger consists of a master latch and a slave latch, wherein the master latch consists of two PMOS tubes (P1 and P2) and six NMOS tubes (N1, N2, N3, N4, N5 and N6), the PMOS tube P1 and the NMOS tube N1 form an inverter to generate a transfer signal Xb, the NMOS tube N2 and the NMOS tube N3 are connected in series to realize the AND logic of Xb and clkb, the NMOS tube N4 and the NMOS tube N5 are connected in series to realize the AND logic of D and clk, and the combined logic of the PMOS tube P1, the PMOS tube P2, the NMOS tube N1, the NMOS tube N2, the NMOS tube N3, the NMOS tube N4 and the NMOS tube N5 generates a complementary signal X of the transfer signal Xb; the slave latch is composed of two PMOS tubes (P3 and P4) and six NMOS tubes (N7, N8, N9, N10, N11 and N12), the PMOS tube P4 and the NMOS tube N11 form an inverter to generate an output signal Qb, the NMOS tube N7 and the NMOS tube N8 are connected in series to realize the AND logic of X and clkb, the NMOS tube N9 and the NMOS tube N10 are connected in series to realize the AND logic of Qb and clk, and the combinational logic of the PMOS tube P3, the PMOS tube P4, the NMOS tube N7, the NMOS tube N8, the NMOS tube N9, the NMOS tube N10 and the NMOS tube N11 generates an output signal Q to realize the function of a D trigger. However, the existing current mode D flip-flop has a large number of transistors and large delay and leakage power consumption, which results in large power consumption and large power consumption delay product.
Therefore, the design of the FinFET device-based current mode D trigger with small delay, power consumption and power consumption delay product is significant.
Disclosure of Invention
The invention aims to solve the technical problem of providing a current mode D trigger based on a FinFET device, which has small circuit area, time delay, power consumption and power consumption time delay product.
The technical scheme adopted by the invention for solving the technical problems is as follows: a current-mode D flip-flop based on FinFET device comprises a first P-type FinFET tube, a second P-type FinFET tube, a third P-type FinFET tube, a fourth P-type FinFET tube, a first N-type FinFET tube, a second N-type FinFET tube, a third N-type FinFET tube, a fourth N-type FinFET tube, a fifth N-type FinFET tube, a sixth N-type FinFET tube, a seventh N-type FinFET tube and an eighth N-type FinFET tube, wherein the first P-type FinFET tube, the second P-type FinFET tube, the third P-type FinFET tube and the fourth P-type FinFET tube are low-threshold P-type FinFET tubes, the first N-type FinFET tube, the sixth N-type FinFET tube, the seventh N-type FinFET tube and the eighth N-type FinFET tube are low-threshold N-type FinFET tubes, the second N-type FinFET tube, the third N-type FinFET tube, the fourth N-type FinFET tube and the fifth N-type FinFET tube are high-threshold P-type FinFET tubes, and the first P-type FinFET tube is a high-type FinFET tube, The source of the second P-type FinFET, the source of the third P-type FinFET and the source of the fourth P-type FinFET are all powered on, the front gate of the first P-type FinFET, the back gate of the first P-type FinFET, the front gate of the second P-type FinFET, the back gate of the second P-type FinFET, the front gate of the third P-type FinFET, the back gate of the third P-type FinFET, the front gate of the fourth P-type FinFET and the back gate of the fourth P-type FinFET are connected and the connection end is the first control end of the current mode D flip-flop, the drain of the second P-type FinFET, the front gate of the first N-type FinFET, the back gate of the first N-type FinFET, the drain of the second N-type FinFET, the drain of the third N-type FinFET and the front gate of the fourth N-type FinFET are connected, and the drain of the first P-type FinFET is connected to the drain of the first P-type FinFET, The drain of the first N-type FinFET transistor is connected to the front gate of the second N-type FinFET transistor, the drain of the third P-type FinFET transistor, the drain of the fourth N-type FinFET transistor, the drain of the fifth N-type FinFET transistor, the front gate of the sixth N-type FinFET transistor and the back gate of the sixth N-type FinFET transistor are connected at their ends to the output of the current-mode-D flip-flop, the drain of the fourth P-type FinFET transistor, the front gate of the fifth N-type FinFET transistor and the drain of the sixth N-type FinFET transistor are connected at their ends to the inverted output of the current-mode-D flip-flop, the source of the first N-type FinFET transistor, the source of the second N-type FinFET transistor, the source of the third N-type FinFET transistor and the drain of the seventh N-type FinFET transistor are connected, the source of the fourth N-type FinFET transistor, the source of the fifth N-type FinFET transistor, the drain of the fourth N-type FinFET transistor and, A source of the sixth N-type FinFET transistor is connected to a drain of the eighth N-type FinFET transistor, a front gate of the seventh N-type FinFET transistor, a back gate of the seventh N-type FinFET transistor, a front gate of the eighth N-type FinFET transistor, and a back gate of the eighth N-type FinFET transistor are connected to each other, and a connection end thereof is a second control end of the current mode D flip-flop, a source of the seventh N-type FinFET transistor and a source of the eighth N-type FinFET transistor are both grounded, a front gate of the third N-type FinFET transistor is an input end of the current mode D flip-flop and is used for receiving an input signal, a back gate of the third N-type FinFET transistor and a back gate of the fifth N-type FinFET transistor are connected to each other, and a connection end thereof is a clock end of the current mode D flip-flop and is an inverted clock end of the current mode D flip-flop, for accessing an inverted signal of the clock signal.
The threshold voltages of the first P-type FinFET tube, the second P-type FinFET tube, the third P-type FinFET tube and the fourth P-type FinFET tube are all 0.17V, the threshold voltages of the first N-type FinFET tube, the sixth N-type FinFET tube, the seventh N-type FinFET tube and the eighth N-type FinFET tube are all 0.33V, and the threshold voltages of the second N-type FinFET tube, the third N-type FinFET tube, the fourth N-type FinFET tube and the fifth N-type FinFET tube are all 0.70V.
The number of the first P-type FinFET tube fins is 1, the number of the second P-type FinFET tube fins is 1, the number of the third P-type FinFET tube fins is 1, the number of the fourth P-type FinFET tube fins is 1, the number of the first N-type FinFET tube fins is 1, the number of the second N-type FinFET tube fins is 2, the number of the third N-type FinFET tube fins is 2, the number of the fourth N-type FinFET tube fins is 2, the number of the fifth N-type FinFET tube fins is 2, the number of the sixth N-type FinFET tube fins is 1, the number of the seventh N-type FinFET tube fins is 5, and the number of the eighth N-type FinFET tube fins is 5.
Compared with the prior art, the invention has the advantages that the first P-type FinFET tube, the second P-type FinFET tube, the third P-type FinFET tube, the fourth P-type FinFET tube, the first N-type FinFET tube, the second N-type FinFET tube, the third N-type FinFET tube, the fourth N-type FinFET tube, the fifth N-type FinFET tube, the sixth N-type FinFET tube, the seventh N-type FinFET tube and the eighth N-type FinFET tube form a current mode D trigger, the first P-type FinFET tube, the second P-type FinFET tube, the third P-type FinFET tube and the fourth P-type FinFET tube form a pull-up resistance network, the seventh N-type FinFET tube and the eighth N-type FinFET tube are used as independent current sources, the second N-type FinFET tube, the third N-type FinFET tube, the fourth N-type FinFET tube and the fifth N-type FinFET tube realize an AND function, the first P-type FinFET tube, the second P-type FinFET tube, the first N-type FinFET tube, the second N-type FinFET tube, the third N-type FinFET tube and the seventh N-type FinFET tube form a, The fourth P type FinFET tube, the fourth N type FinFET tube, the fifth N type FinFET tube, the sixth N type FinFET tube and the eighth N type FinFET tube form a slave latch, so that the FinFET tubes and the single-rail current mode structure are combined to realize the D trigger, a pull-up resistor network and an independent current source structure are reserved, the circuit area is reduced, the circuit delay is reduced, the series connection of the FinFET tubes in the pull-down network is effectively avoided, and the circuit area, the delay, the power consumption and the power consumption delay product are small.
Drawings
FIG. 1 is a circuit diagram of a prior art CMOS device based current mode D flip-flop;
FIG. 2 is a circuit diagram of a current-mode D flip-flop of the present invention based on a FinFET device;
fig. 3 is a simulation waveform diagram of a current-mode D flip-flop based on a FinFET device of the present invention under the bsiimg standard process at a standard voltage (1 v).
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The first embodiment is as follows: as shown in fig. 2, a current mode D flip-flop based on a FinFET device includes a first P-type FinFET P1, a second P-type FinFET P2, a third P-type FinFET P3, a fourth P-type FinFET P4, a first N-type FinFET N1, a second N-type FinFET N2, a third N-type FinFET N3, a fourth N-type FinFET N4, a fifth N-type FinFET N5, a sixth N-type FinFET N6, a seventh N-type FinFET N7, and an eighth N-type FinFET N8, wherein the first P-type FinFET P1, the second P-type FinFET P2, the third P-type FinFET P3, and the fourth P-type FinFET P4 are low-threshold P-type finfets, the first N-type FinFET N1, the sixth N-type FinFET N2, the seventh N7, and the eighth P-type finfets N4 are respectively low-threshold P8658, high-threshold P8653, high-type FinFET N8653, and the fourth N8653 are respectively, The source of the second P-type FinFET tube P2, the source of the third P-type FinFET tube P3 and the source of the fourth P-type FinFET tube P4 are all connected to a power supply VDD, the front gate of the first P-type FinFET tube P1, the back gate of the first P-type FinFET tube P1, the front gate of the second P-type FinFET tube P2, the back gate of the second P-type FinFET tube P2, the front gate of the third P-type FinFET tube P3, the back gate of the third P-type FinFET tube P3, the front gate of the fourth P-type FinFET tube P4 and the back gate of the fourth P-type FinFET tube P4 are connected and the connection end is the first control end of the current mode D flip-flop, the first voltage control signal fp is connected, the drain of the second P-type FinFET tube P2, the drain of the first N-type FinFET tube N1, the back gate of the first N-type FinFET tube N1, the drain of the second N-type FinFET tube N2, the drain of the third N3, the drain of the fourth P-type FinFET tube P3527 and the drain of the first P-type FinFET tube P2 are connected, the drain of the third P-type FinFET P3, the drain of the fourth N-type FinFET N4, the drain of the fifth N-type FinFET N5, the front gate of the sixth N-type FinFET N6, and the back gate of the sixth N-type FinFET N6 are connected and the connection end is the output end of the current-mode D flip-flop for outputting the signal Q, the drain of the fourth P-type FinFET P4, the front gate of the fifth N-type FinFET N5, and the drain of the sixth N-type FinFET N6 are connected and the connection end is the inverting output end of the current-mode D flip-flop for outputting the inverting signal Qb of the signal Q, the source of the first N-type FinFET N1, the source of the second N-type FinFET N2, the source of the third N-type FinFET N3, and the drain of the seventh N7 are connected, the source of the fourth N-type FinFET N4, the source of the fifth N-type FinFET N5, the source of the sixth N-type FinFET N6, the source of the eighth N39 8, and the seventh N-type FinFET N3926 are connected and the seventh N7, The front gate of the eighth N-type FinFET N8 and the back gate of the eighth N-type FinFET N8 are connected, and the connection end thereof is the second control end of the current mode D flip-flop, the second voltage control signal Vrfn is connected, the source of the seventh N-type FinFET N7 and the source of the eighth N-type FinFET N8 are both grounded, the front gate of the third N-type FinFET N3 is the input end of the current mode D flip-flop and is used for accessing the input signal D, the back gate of the third N-type FinFET N3 and the back gate of the fifth N-type FinFET N5 are connected, and the connection end thereof is the clock end of the current mode D flip-flop and is used for accessing the clock signal clk, and the back gate of the second N-type FinFET N2 and the back gate of the fourth N4 are connected, and the connection end thereof is the inverted clock end of the current mode D flip-flop and is the inverted clock end of the clock signal clkb.
In this embodiment, the first voltage control signal Vrfp is generated by a bias circuit, and is usually 0.3V to 0.8V, the second voltage control signal Vrfn is usually implemented by a bias of a conventional current mirror, and the second voltage control signal Vrfn is 0.6V to 1V.
In this embodiment, the number of P1 fins of the first P-type FinFET tube is 1, the number of P2 fins of the second P-type FinFET tube is 1, the number of P3 fins of the third P-type FinFET tube is 1, the number of P4 fins of the fourth P-type FinFET tube is 1, the number of N1 fins of the first N-type FinFET tube is 1, the number of N2 fins of the second N-type FinFET tube is 2, the number of N3 fins of the third N-type FinFET tube is 2, the number of N4 fins of the fourth N-type FinFET tube is 2, the number of N5 fins of the fifth N-type FinFET tube is 2, the number of N6 fins of the sixth N-type FinFET tube is 1, the number of N7 fins of the seventh N-type FinFET tube is 5, and the number of N8 fins of the eighth N-type FinFET tube is 5.
Example two: as shown in fig. 2, a current mode D flip-flop based on a FinFET device includes a first P-type FinFET P1, a second P-type FinFET P2, a third P-type FinFET P3, a fourth P-type FinFET P4, a first N-type FinFET N1, a second N-type FinFET N2, a third N-type FinFET N3, a fourth N-type FinFET N4, a fifth N-type FinFET N5, a sixth N-type FinFET N6, a seventh N-type FinFET N7, and an eighth N-type FinFET N8, wherein the first P-type FinFET P1, the second P-type FinFET P2, the third P-type FinFET P3, and the fourth P-type FinFET P4 are low-threshold P-type finfets, the first N-type FinFET N1, the sixth N-type FinFET N2, the seventh N7, and the eighth P-type finfets N4 are respectively low-threshold P8658, high-threshold P8653, high-type FinFET N8653, and the fourth N8653 are respectively, The source of the second P-type FinFET tube P2, the source of the third P-type FinFET tube P3 and the source of the fourth P-type FinFET tube P4 are all connected to a power supply VDD, the front gate of the first P-type FinFET tube P1, the back gate of the first P-type FinFET tube P1, the front gate of the second P-type FinFET tube P2, the back gate of the second P-type FinFET tube P2, the front gate of the third P-type FinFET tube P3, the back gate of the third P-type FinFET tube P3, the front gate of the fourth P-type FinFET tube P4 and the back gate of the fourth P-type FinFET tube P4 are connected and the connection end is the first control end of the current mode D flip-flop, the first voltage control signal fp is connected, the drain of the second P-type FinFET tube P2, the drain of the first N-type FinFET tube N1, the back gate of the first N-type FinFET tube N1, the drain of the second N-type FinFET tube N2, the drain of the third N3, the drain of the fourth P-type FinFET tube P3527 and the drain of the first P-type FinFET tube P2 are connected, the drain of the third P-type FinFET P3, the drain of the fourth N-type FinFET N4, the drain of the fifth N-type FinFET N5, the front gate of the sixth N-type FinFET N6, and the back gate of the sixth N-type FinFET N6 are connected and the connection end is the output end of the current-mode D flip-flop for outputting the signal Q, the drain of the fourth P-type FinFET P4, the front gate of the fifth N-type FinFET N5, and the drain of the sixth N-type FinFET N6 are connected and the connection end is the inverting output end of the current-mode D flip-flop for outputting the inverting signal Qb of the signal Q, the source of the first N-type FinFET N1, the source of the second N-type FinFET N2, the source of the third N-type FinFET N3, and the drain of the seventh N7 are connected, the source of the fourth N-type FinFET N4, the source of the fifth N-type FinFET N5, the source of the sixth N-type FinFET N6, the source of the eighth N39 8, and the seventh N-type FinFET N3926 are connected and the seventh N7, The front gate of the eighth N-type FinFET N8 and the back gate of the eighth N-type FinFET N8 are connected, and the connection end thereof is the second control end of the current mode D flip-flop, the second voltage control signal Vrfn is connected, the source of the seventh N-type FinFET N7 and the source of the eighth N-type FinFET N8 are both grounded, the front gate of the third N-type FinFET N3 is the input end of the current mode D flip-flop and is used for accessing the input signal D, the back gate of the third N-type FinFET N3 and the back gate of the fifth N-type FinFET N5 are connected, and the connection end thereof is the clock end of the current mode D flip-flop and is used for accessing the clock signal clk, and the back gate of the second N-type FinFET N2 and the back gate of the fourth N4 are connected, and the connection end thereof is the inverted clock end of the current mode D flip-flop and is the inverted clock end of the clock signal clkb.
In this embodiment, the first voltage control signal Vrfp is generated by a bias circuit, and is usually 0.3V to 0.8V, the second voltage control signal Vrfn is usually implemented by a bias of a conventional current mirror, and the second voltage control signal Vrfn is 0.6V to 1V.
In this embodiment, the number of P1 fins of the first P-type FinFET tube is 1, the number of P2 fins of the second P-type FinFET tube is 1, the number of P3 fins of the third P-type FinFET tube is 1, the number of P4 fins of the fourth P-type FinFET tube is 1, the number of N1 fins of the first N-type FinFET tube is 1, the number of N2 fins of the second N-type FinFET tube is 2, the number of N3 fins of the third N-type FinFET tube is 2, the number of N4 fins of the fourth N-type FinFET tube is 2, the number of N5 fins of the fifth N-type FinFET tube is 2, the number of N6 fins of the sixth N-type FinFET tube is 1, the number of N7 fins of the seventh N-type FinFET tube is 5, and the number of N8 fins of the eighth N-type FinFET tube is 5.
In this embodiment, the threshold voltages of the first P-type FinFET transistor P1, the second P-type FinFET transistor P2, the third P-type FinFET transistor P3, and the fourth P-type FinFET transistor P4 are all 0.17V, the threshold voltages of the first N-type FinFET transistor N1, the sixth N-type FinFET transistor N6, the seventh N-type FinFET transistor N7, and the eighth N-type FinFET transistor N8 are all 0.33V, and the threshold voltages of the second N-type FinFET transistor N2, the third N-type FinFET transistor N3, the fourth N-type FinFET transistor N4, and the fifth N-type FinFET transistor N5 are all 0.70V.
In this embodiment, the number of P1 fins of the first P-type FinFET tube is 1, the number of P2 fins of the second P-type FinFET tube is 1, the number of P3 fins of the third P-type FinFET tube is 1, the number of P4 fins of the fourth P-type FinFET tube is 1, the number of N1 fins of the first N-type FinFET tube is 1, the number of N2 fins of the second N-type FinFET tube is 2, the number of N3 fins of the third N-type FinFET tube is 2, the number of N4 fins of the fourth N-type FinFET tube is 2, the number of N5 fins of the fifth N-type FinFET tube is 2, the number of N6 fins of the sixth N-type FinFET tube is 1, the number of N7 fins of the seventh N-type FinFET tube is 5, and the number of N8 fins of the eighth N-type FinFET tube is 5.
In order to verify the advantages of the current mode D trigger based on the FinFET device, under the BSIMG standard process, a circuit simulation tool HSPICE is used to perform simulation comparison analysis on the circuits of the two D triggers, namely the current mode D trigger based on the FinFET device and the current mode D trigger based on the CMOS device shown in the figure 1, under the condition that the input frequency of the circuit is 100MHz, 200MHz, 500MHz and 1GHz, and the corresponding power supply voltage of a BSIMG process library is 1V. A simulation waveform diagram of the current-mode D flip-flop based on the FinFET device of the present invention based on the bsiimg standard process at a standard voltage (1v) is shown in fig. 3.
The performance comparison table of the current mode D flip-flop based on the FinFET device of the present invention and the current mode D flip-flop based on the CMOS device shown in fig. 1 is shown in table 1, which is a simulation comparison under the condition of the bsiimg standard process and the input frequency of 100 MHz.
TABLE 1
Type of circuit Number of transistors Time delay (us) Power consumption (μ W) Power consumption time delay product (fJ)
D flip-flop of the invention 12 0.0415 54.359 2.2559
Existing D flip-flop 16 0.0506 61.241 3.0988
From table 1, it can be derived: compared with the existing current mode D trigger based on the CMOS device shown in figure 1, the current mode D trigger based on the FinFET device has the advantages that the number of transistors is reduced by 4, the delay is reduced by 17.98%, the power consumption is reduced by 11.24%, and the power consumption delay product is reduced by 27.20%.
The performance comparison table of the current mode D flip-flop based on the FinFET device of the present invention and the current mode D flip-flop based on the CMOS device shown in fig. 1 is shown in table 2, which is a simulation comparison performed under the condition of the bsiimg standard process and the input frequency of 200 MHz.
TABLE 2
Type of circuit Number of transistors Time delay (us) Power consumption (μ W) Power consumption time delay product (fJ)
D flip-flop of the invention 12 0.0415 54.825 2.2752
Existing D flip-flop 16 0.0506 61.623 3.1181
From table 2, it can be derived: compared with the existing current mode D trigger based on the CMOS device shown in figure 1, the current mode D trigger based on the FinFET device has the advantages that the number of transistors is reduced by 4, the delay is reduced by 17.98%, the power consumption is reduced by 11.03%, and the power consumption delay product is reduced by 27.03%.
The performance comparison table of the current mode D flip-flop based on the FinFET device of the present invention and the current mode D flip-flop based on the CMOS device shown in fig. 1 is shown in table 3, which is a simulation comparison performed under the condition of a bsiimmg standard process and an input frequency of 500 MHz.
TABLE 3
Type of circuit Number of transistors Time delay (us) Power consumption (μ W) Power consumption time delay product (fJ)
D flip-flop of the invention 12 0.0415 55.030 2.2837
Existing D flip-flop 16 0.0506 62.148 3.1447
From table 3, it can be derived: compared with the existing current mode D trigger based on the CMOS device shown in figure 1, the current mode D trigger based on the FinFET device has the advantages that the number of transistors is reduced by 4, the delay is reduced by 17.98%, the power consumption is reduced by 11.45%, and the power consumption delay product is reduced by 27.37%.
The performance comparison table of the current mode D flip-flop based on the FinFET device of the present invention and the current mode D flip-flop based on the CMOS device shown in fig. 1 is shown in table 4, which is a simulation comparison performed under the condition that the input frequency is 1GHz in the bsiimmg standard process.
TABLE 4
Type of circuit Number of transistors Time delay (us) Power consumption (μ W) Power consumption time delay product (fJ)
D flip-flop of the invention 12 0.0415 55.382 2.2983
Existing D flip-flop 16 0.0506 62.465 3.1607
From table 4, it can be derived: compared with the existing current mode D trigger based on the CMOS device shown in figure 1, the current mode D trigger based on the FinFET device has the advantages that the number of transistors is reduced by 4, the delay is reduced by 17.98%, the power consumption is reduced by 11.33%, and the power consumption delay product is reduced by 27.29%.

Claims (2)

1. A current-mode D flip-flop based on a FinFET device, comprising a first P-type FinFET tube, a second P-type FinFET tube, a third P-type FinFET tube, a fourth P-type FinFET tube, a first N-type FinFET tube, a second N-type FinFET tube, a third N-type FinFET tube, a fourth N-type FinFET tube, a fifth N-type FinFET tube, a sixth N-type FinFET tube, a seventh N-type FinFET tube, and an eighth N-type FinFET tube, wherein said first P-type FinFET tube, said second P-type FinFET tube, said third P-type FinFET tube, and said fourth P-type FinFET tube are low-threshold P-type FinFET tubes, respectively, said first N-type FinFET tube, said sixth N-type FinFET tube, said seventh N-type FinFET tube, and said eighth N-type FinFET tube are low-threshold N-type FinFET tubes, said second N-type FinFET tube, said third N-type FinFET tube, said fourth N-type FinFET tube, and said fifth N-type FinFET tube are high-type FinFET tubes, the source of the first P-type FinFET, the source of the second P-type FinFET, the source of the third P-type FinFET and the source of the fourth P-type FinFET are all powered on, the front gate of the first P-type FinFET, the back gate of the first P-type FinFET, the front gate of the second P-type FinFET, the back gate of the second P-type FinFET, the front gate of the third P-type FinFET, the back gate of the third P-type FinFET, the front gate of the fourth P-type FinFET and the back gate of the fourth P-type FinFET are connected and their connection end is the first control end of the current mode D flip-flop, the drain of the second P-type FinFET, the front gate of the first N-type FinFET, the back gate of the first N-type FinFET, the drain of the second N-type FinFET, the drain of the third N-type FinFET and the front gate of the fourth P-type FinFET are connected, the drain of the first P-type FinFET, the drain of the first N-type FinFET, the front gate of the second N-type FinFET, the front gate of the sixth N-type FinFET, the back gate of the sixth N-type FinFET, and the connecting ends thereof are the outputs of the current-modulo-D flip-flops, the drain of the fourth P-type FinFET, the front gate of the fifth N-type FinFET, and the drain of the sixth N-type FinFET, and the connecting ends thereof are the inverted outputs of the current-modulo-D flip-flops, the source of the first N-type FinFET, the source of the second N-type FinFET, the source of the third N-type FinFET, and the drain of the seventh N-type FinFET, the source of the fourth N-type FinFET, the drain of the fifth N-type FinFET, and the connecting ends thereof are the inverted outputs of the current-modulo-D flip-flop, and the sources of the first N-type FinFET, the second N-type FinFET, the drain of the third N-type FinFET, and the fifth N-type FinFET, and the, The source of the fifth N-type FinFET transistor, the source of the sixth N-type FinFET transistor, and the drain of the eighth N-type FinFET transistor are connected, the front gate of the seventh N-type FinFET transistor, the back gate of the seventh N-type FinFET transistor, the front gate of the eighth N-type FinFET transistor, and the back gate of the eighth N-type FinFET transistor are connected, and a connection end thereof is the second control end of the current mode D flip-flop, the source of the seventh N-type FinFET transistor, and the source of the eighth N-type FinFET transistor are both grounded, the front gate of the third N-type FinFET transistor is the input end of the current mode D flip-flop and is used for inputting an input signal, the back gate of the third N-type FinFET transistor, and the back gate of the fifth N-type FinFET transistor, and a connection end thereof is the clock end of the current mode D flip-flop, and is the back gate of the second N-type FinFET transistor, and the fourth N-type FinFET transistor, and a connection end thereof is the inverted clock end of the current mode D flip-flop, and is the back gate of the current mode D flip-flop The inverted signal is used for accessing the clock signal;
the threshold voltages of the first P-type FinFET tube, the second P-type FinFET tube, the third P-type FinFET tube and the fourth P-type FinFET tube are all 0.17V, the threshold voltages of the first N-type FinFET tube, the sixth N-type FinFET tube, the seventh N-type FinFET tube and the eighth N-type FinFET tube are all 0.33V, and the threshold voltages of the second N-type FinFET tube, the third N-type FinFET tube, the fourth N-type FinFET tube and the fifth N-type FinFET tube are all 0.70V.
2. The current-mode D flip-flop of claim 1, wherein the number of first P-type FinFET fins is 1, the number of second P-type FinFET fins is 1, the number of third P-type FinFET fins is 1, the number of fourth P-type FinFET fins is 1, the number of first N-type FinFET fins is 1, the number of second N-type FinFET fins is 2, the number of third N-type FinFET fins is 2, the number of fourth N-type FinFET fins is 2, the number of fifth N-type FinFET fins is 2, the number of sixth N-type FinFET fins is 1, the number of seventh N-type FinFET fins is 5, and the number of eighth N-type FinFET fins is 5.
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