CN108494386B - FinFET-based master-slave trigger - Google Patents
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- CN108494386B CN108494386B CN201810092762.7A CN201810092762A CN108494386B CN 108494386 B CN108494386 B CN 108494386B CN 201810092762 A CN201810092762 A CN 201810092762A CN 108494386 B CN108494386 B CN 108494386B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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Abstract
The invention discloses a FinFET-based master-slave flip-flop which comprises an input circuit, a master latch and a slave latch, wherein the input circuit comprises a first phase inverter, a second phase inverter and a third phase inverter; the slave latch comprises a fifth FinFET tube, a sixth FinFET tube, a seventh FinFET tube, an eighth FinFET tube, a fifth inverter and a sixth inverter; the flip-flop circuit has the advantages that on the basis of having correct working logic, the circuit structure is simple, the flip-flop function is realized by adopting a small number of transistors, when the flip-flop circuit is in a working state, the working current mainly comprises the current in the master latch and the current in the slave latch, the master latch and the slave latch work alternately, and the circuit area, the power consumption and the power consumption delay product are small under the condition of not influencing the circuit performance.
Description
Technical Field
The invention relates to a master-slave flip-flop, in particular to a FinFET-based master-slave flip-flop.
Background
In the field of digital electronics, sequential logic circuits are made up of memory circuits and combinational logic, with memory components used to maintain the logic state of the sequential logic circuit. The flip-flop, as a memory circuit, is one of the more basic circuits of digital circuits, and plays an important role in digital circuit systems.
With the continuous progress of the VISL technology, in a digital circuit system with low requirement on the running speed, the power consumption requirement of the digital circuit system is continuously improved, the requirement on the performance of the flip-flop is also more strict, and the flip-flop is required to have low power consumption and low power consumption delay product at the same time. The performance of the flip-flop, such as power consumption, power consumption delay product, and area, will directly affect the overall performance of the entire low-speed digital circuit system. At present, a circuit diagram of a conventional clocked D flip-flop widely used in low-speed digital circuitry is shown in fig. 1, and the clocked D flip-flop includes an input circuit, a master latch, and a slave latch, wherein the input circuit is composed of three inverters for receiving an input signal and a clock control signal, and the master latch and the slave latch are respectively composed of four two-input nand gates. In the clocked D flip-flop, the internal structure of each two-input nand Gate in the master latch and the slave latch at least includes four Fin Field Effect transistors (FinFET transistors), and the Fin Field Effect transistors included in each two-input nand Gate are all in a Common Gate (Common Multi-Gate) operating mode, so that although the overall structure of the clocked D flip-flop is simple, the clocked D flip-flop consumes a large number of FinFET transistors in the overall structure, has a large area, generates large power consumption, and has a large power consumption delay product, which is not favorable for the design of a low-power consumption circuit.
Disclosure of Invention
The invention aims to solve the technical problem of providing a FinFET-based master-slave flip-flop which is small in area, low in power consumption and small in power consumption delay product.
The technical scheme adopted by the invention for solving the technical problems is as follows: a FinFET-based master-slave flip-flop includes an input circuit, a master latch, and a slave latch, the input circuit comprises a first inverter, a second inverter and a third inverter, wherein the input end of the first inverter is the clock input end of the input circuit, the output end of the first inverter is connected with the input end of the second inverter, and the connection end of the first inverter is the inverted clock output end of the input circuit, the output end of the second inverter is the clock output end of the input circuit, the input end of the third inverter is the data input end of the master-slave flip-flop, the output end of the third inverter is the data output end of the input circuit, and the master latch comprises a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube and a fourth inverter; the first FinFET tube and the third FinFET tube are both P-type FinFET tubes, the second FinFET tube and the fourth FinFET tube are both N-type FinFET tubes, the number of fins of the first FinFET tube is 1, the number of fins of the second FinFET tube is 1, the number of fins of the third FinFET tube is 1, and the number of fins of the fourth FinFET tube is 1; the front gate of the first FinFET tube, the back gate of the first FinFET tube and the back gate of the fourth FinFET tube are connected and their connection ends are the clock input end of the master latch, the clock input end of the master latch is connected with the clock output end of the input circuit, the source of the first FinFET tube is connected with the front gate of the second FinFET tube and its connection end is the data input end of the master latch, the data input end of the master latch is connected with the data output end of the input circuit, the back gate of the second FinFET tube is the inverted clock input end of the master latch, the inverted clock input end of the master latch is connected with the inverted clock output end of the input circuit, the drain of the first FinFET tube, the input end of the fourth inverter, the drain of the third FinFET tube and the drain of the fourth FinFET tube are connected, the drain of the second FinFET tube, the output end of the fourth inverter, the front gate of the third FinFET tube, the back gate of the third FinFET tube and the front gate of the fourth FinFET tube are connected and the connection end is the data output end of the main latch, the source of the third FinFET tube is connected with a power supply, and the source of the second FinFET tube and the source of the fourth FinFET tube are both grounded; the slave latch comprises a fifth FinFET tube, a sixth FinFET tube, a seventh FinFET tube, an eighth FinFET tube, a fifth inverter and a sixth inverter; the fifth FinFET tube and the seventh FinFET tube are both P-type FinFET tubes, the sixth FinFET tube and the eighth FinFET tube are both N-type FinFET tubes, the number of fins of the fifth FinFET tube is 1, the number of fins of the sixth FinFET tube is 1, the number of fins of the seventh FinFET tube is 1, and the number of fins of the eighth FinFET tube is 1; the front gate of the fifth FinFET tube, the back gate of the fifth FinFET tube, and the back gate of the eighth FinFET tube are connected and their connection terminals are the inverted clock input terminal of the slave latch, the inverted clock input terminal of the slave latch is connected with the inverted clock output terminal of the input circuit, the source of the fifth FinFET tube is connected with the front gate of the sixth FinFET tube and its connection terminal is the data input terminal of the slave latch, the data input terminal of the slave latch is connected with the data output terminal of the master latch, the back gate of the sixth FinFET tube is the clock input terminal of the slave latch, the clock input terminal of the slave latch is connected with the clock output terminal of the input circuit, the drain of the fifth FinFET tube, the input terminal of the fifth inverter, the drain of the seventh FinFET tube is connected with the drain of the eighth FinFET tube, the drain of the sixth FinFET transistor, the output of the fifth inverter, the front gate of the seventh FinFET transistor, the back gate of the seventh FinFET transistor, the front gate of the eighth FinFET transistor, and the input of the sixth inverter are connected together, and the connection end is the inverted data output of the slave latch, the output of the sixth inverter is the data output of the slave latch, the source of the seventh FinFET transistor is connected to a power supply, and the source of the sixth FinFET transistor and the source of the eighth FinFET transistor are both grounded.
The first phase inverter comprises a ninth FinFET tube and a tenth FinFET tube, the ninth FinFET tube is a P-type FinFET tube, the tenth FinFET tube is an N-type FinFET tube, the number of fins of the ninth FinFET tube is 2, and the number of fins of the tenth FinFET tube is 1; the source of the ninth FinFET transistor is connected to a power supply, the front gate of the ninth FinFET transistor, the back gate of the ninth FinFET transistor, the front gate of the tenth FinFET transistor, and the back gate of the tenth FinFET transistor are connected together, and their connection ends are the input end of the first inverter, the drain of the ninth FinFET transistor is connected to the drain of the tenth FinFET transistor, and its connection end is the output end of the first inverter, the source of the tenth FinFET transistor is grounded, and the circuit structures of the second inverter, the third inverter, the fourth inverter, the fifth inverter, and the sixth inverter are all the same as the first inverter.
Compared with the prior art, the invention has the advantages that the clock control module is formed by the first phase inverter and the second phase inverter in the input circuit, the third phase inverter is used as a data input device, the fourth phase inverter, the first FinFET tube, the second FinFET tube, the third FinFET tube and the fourth FinFET tube form a master latch, and the fifth phase inverter, the fifth FinFET tube, the sixth FinFET tube, the seventh FinFET tube and the eighth FinFET tube form a slave latch; the operating state of the master latch being controlled by an external clock signal CAnd LK is controlled, when CLK is equal to 0, the input data D is written into the main latch through the third inverter and the first FinFET tube, the second FinFET tube works at the same time, the input data D written into the main latch is corrected at the data output end of the main latch to compensate the transmission threshold loss of the first FinFET tube, and the third FinFET tube, the fourth FinFET tube and the fourth inverter are combined into an inverter ring, so that the data output end f of the main latch1The data D can be kept, the connection between the data output end of the master latch and the data input end of the slave latch is cut off by the cut-off of the fifth FinFET tube and the sixth FinFET tube, the trigger signal Q at the data output end of the slave latch is kept, the working state of the slave latch is controlled by the inverted clock signal CLKb, when CLKb is 0, the first FinFET tube and the second FinFET tube are disconnected, the master latch is in a high impedance state, the external input data D is cut off, at the moment, the fifth FinFET tube and the sixth FinFET tube in the slave latch work, and the data output end f of the master latch is1The stored data D is transmitted into the slave latch and is output to the data output end of the slave latch through the sixth inverter, so that the data output is realized, the master-slave trigger based on the FinFET device is insensitive to clock overlapping, and the working current of the master-slave trigger is mainly composed of the current in the master latch and the current in the slave latch in the working state; when CLK is 1, the master latch does not work, the slave latch outputs data, the working current of the whole circuit is the current of the slave latch, when CLK is 0, the master latch works, the slave latch does not work, the working current of the whole circuit is the current of the master latch, therefore, the master-slave flip-flop of the invention has simple circuit structure on the basis of having correct working logic, adopts a small number of transistors to realize the flip-flop function, and the master latch and the slave latch work alternately, and under the condition of not influencing the circuit performance, the circuit area, the power consumption and the power consumption delay product are all small.
Drawings
FIG. 1 is a circuit diagram of a conventional master-slave flip-flop;
FIG. 2 is a circuit diagram of a FinFET-based master-slave flip-flop of the present invention;
FIG. 3(a) is a circuit diagram of a first inverter of a FinFET-based master-slave flip-flop of the present invention;
FIG. 3(b) is a symbolic diagram of a first inverter of a FinFET-based master-slave flip-flop of the present invention;
FIG. 4 is a simulated waveform diagram of a FinFET-based master-slave flip-flop of the present invention under BSIMIMIMG standard process at standard voltage (1V);
FIG. 5 is a waveform diagram of a simulation of a FinFET-based master-slave flip-flop of the present invention at a super-threshold voltage (0.8V) in the BSIMIMG standard process.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The first embodiment is as follows: as shown in FIG. 2, a FinFET-based master-slave flip-flop comprises an input circuit, a master latch and a slave latch, wherein the input circuit comprises a first inverter F1, a second inverter F2 and a third inverter F3, the input end of the first inverter F1 is the clock input end of the input circuit and is used for accessing a clock control signal CLK, the output end of the first inverter F1 is connected with the input end of the second inverter F2, the connecting end of the first inverter F2 is the inverted clock output end of the input circuit and is used for outputting an inverted signal CLKb of the clock control signal CLK, the output end of the second inverter F2 is the clock output end of the input circuit, the input end of the third inverter F3 is the data input end of the master-slave flip-flop and is used for accessing external data D, the output end of the third inverter F3 is the data output end of the input circuit, and the master latch comprises a first FinFET M1, a second FinFET M2, a third, A fourth FinFET transistor M4 and a fourth inverter F4; the first FinFET tube M1 and the third FinFET tube M3 are both P-type FinFET tubes, the second FinFET tube M2 and the fourth FinFET tube M4 are both N-type FinFET tubes, the number of fins of the first FinFET tube M1 is 1, the number of fins of the second FinFET tube M2 is 1, the number of fins of the third FinFET tube M3 is 1, and the number of fins of the fourth FinFET tube M4 is 1; the front gate of the first FinFET M1, the back gate of the first FinFET M1, and the back gate of the fourth FinFET M4 are connected and their connection terminals are the clock input terminal of the master latch, the clock input terminal of the master latch is connected to the clock output terminal of the input circuit, the source of the first FinFET M1 and the front gate of the second FinFET M2 are connected and their connection terminals are the data input terminal of the master latch, the data input terminal of the master latch is connected to the data output terminal of the input circuit, the back gate of the second FinFET M2 is the inverted clock input terminal of the master latch, the inverted clock input terminal of the master latch is connected to the inverted clock output terminal of the input circuit, the drain of the first FinFET M1, the input terminal of the fourth inverter F4, the drain of the third FinFET M3, and the drain of the fourth FinFET M4, the drain of the second FinFET M2, the output terminal of the fourth inverter F4, the front gate of the third FinFET M3, the back gate of the third FinFET M3, and the back gate of the fourth FinFET M4 are connected to the data output terminal of the master latch, the source electrode of the third FinFET M3 is connected to a power supply VDD, and the source electrode of the second FinFET M2 and the source electrode of the fourth FinFET M4 are both grounded; the slave latch comprises a fifth FinFET tube M5, a sixth FinFET tube M6, a seventh FinFET tube M7, an eighth FinFET tube M8, a fifth inverter F5 and a sixth inverter F6; the fifth FinFET tube M5 and the seventh FinFET tube M7 are both P-type FinFET tubes, the sixth FinFET tube M6 and the eighth FinFET tube M8 are both N-type FinFET tubes, the number of fins of the fifth FinFET tube M5 is 1, the number of fins of the sixth FinFET tube M6 is 1, the number of fins of the seventh FinFET tube M7 is 1, and the number of fins of the eighth FinFET tube M8 is 1; the front gate of the fifth FinFET M5, the back gate of the fifth FinFET M5, and the back gate of the eighth FinFET M8 are connected together, and their connection terminals are the inverted clock input terminal of the slave latch, the inverted clock input terminal of the slave latch is connected to the inverted clock output terminal of the input circuit, the source of the fifth FinFET M5 is connected to the front gate of the sixth FinFET M6, and its connection terminal is the data input terminal of the slave latch, the data input terminal of the slave latch is connected to the data output terminal of the master latch, the back gate of the sixth FinFET M6 is the clock input terminal of the slave latch, the clock input terminal of the slave latch is connected to the clock output terminal of the input circuit, the drain of the fifth FinFET M5, the input terminal of the fifth inverter F5, the drain of the seventh FinFET M7, and the drain of the eighth FinFET M8, the drain of the sixth FinFET M6, the output terminal of the fifth inverter F5, the front gate of the seventh FinFET M7, the back gate of the seventh FinFET M7, and their connection terminals are, The front gate of the eighth FinFET transistor M8 is connected to the input of the sixth inverter F6, and its connection terminal is the inverted data output terminal of the slave latch, which outputs the inverted trigger signal Q, the output of the sixth inverter F6 is the data output terminal of the slave latch, which outputs the trigger signal Q, the source of the seventh FinFET transistor M7 is connected to the power supply VDD, and the source of the sixth FinFET transistor M6 and the source of the eighth FinFET transistor M8 are both grounded.
Example two: the present embodiment is substantially the same as the first embodiment, except that in the present embodiment, the first inverter F1 includes a ninth FinFET M9 and a tenth FinFET M10, the ninth FinFET M9 is a P-type FinFET, the tenth FinFET M10 is an N-type FinFET, the number of fins of the ninth FinFET M9 is 2, and the number of fins of the tenth FinFET M10 is 1; the source of the ninth FinFET M9 is connected to the power supply VDD, the front gate of the ninth FinFET M9, the back gate of the ninth FinFET M9, the front gate of the tenth FinFET M10 and the back gate of the tenth FinFET M10 are connected, and the connection end thereof is the input end of the first inverter F1, the drain of the ninth FinFET M9 and the drain of the tenth FinFET M10 are connected, and the connection end thereof is the output end of the first inverter F1, the source of the tenth FinFET M10 is grounded, and the circuit structures of the second inverter F2, the third inverter F3, the fourth inverter F4, the fifth inverter F5 and the sixth inverter F6 are all the same as that of the first inverter F1. The first inverter F1 has a circuit diagram shown in fig. 3(a) and a symbol diagram shown in fig. 3 (b).
In order to verify the advantages of the FinFET-based master-slave flip-flop, under the BSIMG standard process and under the condition that the input frequency of a circuit is 100MHz, 400MHz, 800MHz and 1GHz, a circuit simulation tool HSPICE is used for carrying out simulation comparison on the performances of the FinFET-based master-slave flip-flop and the traditional master-slave flip-flop shown in the figure 1, wherein the power supply voltage VDD corresponding to a BSIMG process library is 1V, inverters in the traditional master-slave flip-flop are all realized by two FinFET tubes, and a two-input NAND gate is realized by four FinFET tubes. The simulation waveform diagram of the FinFET-based master-slave trigger under the BSIMIMIMG standard process at the standard voltage (1V) is shown in FIG. 4; at a super-threshold voltage (0.8V), a simulation waveform diagram of the FinFET-based master-slave flip-flop under the BSIMIMG standard process is shown in FIG. 5. As can be seen from an analysis of fig. 4 and 5, the FinFET-based master-slave flip-flop of the present invention has the correct operating logic.
Table 1 shows the comparison result of the performance of the FinFET-based master-slave flip-flop of the present invention and the conventional master-slave flip-flop when the input frequency is 100MHz in the bsiimg standard process.
TABLE 1
The analysis in Table 1 shows that: compared with the traditional master-slave flip-flop, although the delay is increased by 19.34%, the number of transistors is reduced by 18, the total power consumption is reduced by 21.63%, the power consumption delay product is reduced by 6.47%, and the overall performance is remarkably improved.
Table 2 shows the comparison result of the performance of the FinFET-based master-slave flip-flop of the present invention and the conventional master-slave flip-flop when the input frequency is 400MHz in the bsiimg standard process.
TABLE 2
The analysis in Table 2 reveals that: compared with the traditional master-slave flip-flop, although the delay is increased by 20.32%, the total power consumption of the flip-flop is reduced by 18 transistors, the total power consumption is reduced by 23.80%, the power consumption delay product is reduced by 8.32%, and the overall performance is remarkably improved.
Table 3 shows the comparison result of the performance of the FinFET-based master-slave flip-flop of the present invention and the conventional master-slave flip-flop when the input frequency is 800MHz in the bsiimg standard process.
TABLE 3
Analysis in Table 3 reveals that: : compared with the traditional master-slave flip-flop, although the delay is increased by 19.85%, the number of transistors is reduced by 18, the total power consumption is reduced by 25.68%, the power consumption delay product is reduced by 10.93%, and the overall performance is remarkably improved.
Table 4 shows the comparison result of the performance of the FinFET-based master-slave flip-flop of the present invention and the conventional master-slave flip-flop when the input frequency is 1G in the bsiimg standard process.
TABLE 4
Analysis in Table 4 reveals that: : compared with the traditional master-slave flip-flop, although the delay is increased by 19.28%, the number of transistors is reduced by 18, the total power consumption is reduced by 26.35%, the power consumption delay product is reduced by 12.15%, and the overall performance is remarkably improved.
In summary, on the premise of not affecting circuit performance, compared with the conventional master-slave flip-flop, the FinFET-based master-slave flip-flop of the present invention has the advantages of reduced number of transistors, and greatly optimized power consumption and power consumption delay product.
Claims (2)
1. A FinFET-based master-slave flip-flop includes an input circuit, a master latch, and a slave latch, the input circuit comprises a first inverter, a second inverter and a third inverter, wherein the input end of the first inverter is the clock input end of the input circuit, the output end of the first inverter is connected with the input end of the second inverter, and the connection end of the first inverter is the inverted clock output end of the input circuit, the output end of the second inverter is the clock output end of the input circuit, the input end of the third inverter is the data input end of the master-slave flip-flop, the output end of the third inverter is the data output end of the input circuit, wherein said master latch comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor, and a fourth inverter; the first FinFET tube and the third FinFET tube are both P-type FinFET tubes, the second FinFET tube and the fourth FinFET tube are both N-type FinFET tubes, the number of fins of the first FinFET tube is 1, the number of fins of the second FinFET tube is 1, the number of fins of the third FinFET tube is 1, and the number of fins of the fourth FinFET tube is 1; the front gate of the first FinFET tube, the back gate of the first FinFET tube and the back gate of the fourth FinFET tube are connected and their connection ends are the clock input end of the master latch, the clock input end of the master latch is connected with the clock output end of the input circuit, the source of the first FinFET tube is connected with the front gate of the second FinFET tube and its connection end is the data input end of the master latch, the data input end of the master latch is connected with the data output end of the input circuit, the back gate of the second FinFET tube is the inverted clock input end of the master latch, the inverted clock input end of the master latch is connected with the inverted clock output end of the input circuit, the drain of the first FinFET tube, the input end of the fourth inverter, the drain of the third FinFET tube and the drain of the fourth FinFET tube are connected, the drain of the second FinFET tube, the output of the fourth inverter, the front gate of the third FinFET tube, the back gate of the third FinFET tube and the front gate of the fourth FinFET tube are connected, and the connection end of the front gate of the third FinFET tube and the back gate of the fourth FinFET tube is the data output end of the main latch;
the slave latch comprises a fifth FinFET tube, a sixth FinFET tube, a seventh FinFET tube, an eighth FinFET tube, a fifth inverter and a sixth inverter; the fifth FinFET tube and the seventh FinFET tube are both P-type FinFET tubes, the sixth FinFET tube and the eighth FinFET tube are both N-type FinFET tubes, the number of fins of the fifth FinFET tube is 1, the number of fins of the sixth FinFET tube is 1, the number of fins of the seventh FinFET tube is 1, and the number of fins of the eighth FinFET tube is 1; the front gate of the fifth FinFET tube, the back gate of the fifth FinFET tube, and the back gate of the eighth FinFET tube are connected and their connection terminals are the inverted clock input terminal of the slave latch, the inverted clock input terminal of the slave latch is connected with the inverted clock output terminal of the input circuit, the source of the fifth FinFET tube is connected with the front gate of the sixth FinFET tube and its connection terminal is the data input terminal of the slave latch, the data input terminal of the slave latch is connected with the data output terminal of the master latch, the back gate of the sixth FinFET tube is the clock input terminal of the slave latch, the clock input terminal of the slave latch is connected with the clock output terminal of the input circuit, the drain of the fifth FinFET tube, the input terminal of the fifth inverter, the drain of the seventh FinFET tube is connected with the drain of the eighth FinFET tube, the drain of the sixth FinFET transistor, the output of the fifth inverter, the front gate of the seventh FinFET transistor, the back gate of the seventh FinFET transistor, the front gate of the eighth FinFET transistor, and the input of the sixth inverter are connected together, and the connection end is the inverted data output of the slave latch, the output of the sixth inverter is the data output of the slave latch, the source of the seventh FinFET transistor is connected to a power supply, and the source of the sixth FinFET transistor and the source of the eighth FinFET transistor are both grounded.
2. The FinFET-based master-slave flip-flop of claim 1, wherein said first inverter comprises a ninth FinFET tube and a tenth FinFET tube, said ninth FinFET tube being a P-type FinFET tube, said tenth FinFET tube being an N-type FinFET tube, said ninth FinFET tube having a number of fins of 2, said tenth FinFET tube having a number of fins of 1; the source of the ninth FinFET transistor is connected to a power supply, the front gate of the ninth FinFET transistor, the back gate of the ninth FinFET transistor, the front gate of the tenth FinFET transistor, and the back gate of the tenth FinFET transistor are connected together, and their connection ends are the input end of the first inverter, the drain of the ninth FinFET transistor is connected to the drain of the tenth FinFET transistor, and its connection end is the output end of the first inverter, the source of the tenth FinFET transistor is grounded, and the circuit structures of the second inverter, the third inverter, the fourth inverter, the fifth inverter, and the sixth inverter are all the same as the first inverter.
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