CN108494386A - A kind of master-slave flip-flop based on FinFET - Google Patents
A kind of master-slave flip-flop based on FinFET Download PDFInfo
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- CN108494386A CN108494386A CN201810092762.7A CN201810092762A CN108494386A CN 108494386 A CN108494386 A CN 108494386A CN 201810092762 A CN201810092762 A CN 201810092762A CN 108494386 A CN108494386 A CN 108494386A
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- latch
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- 230000005611 electricity Effects 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
- H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
Abstract
The invention discloses a kind of master-slave flip-flops based on FinFET, including input circuit, main latch and from latch, input circuit includes the first phase inverter, the second phase inverter and third phase inverter, and main latch includes the first FinFET pipes, the 2nd FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes and the 4th phase inverter；Include the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, the 8th FinFET pipes, the 5th phase inverter and hex inverter from latch；Advantage is on the basis of with correct work-based logic, circuit structure is simple, trigger function is realized using the transistor of negligible amounts, in working condition, its operating current mainly by main latch electric current and form from the electric current in latch, main latch and from latch work alternatively, in the case where not influencing circuit performance, circuit area, power consumption and power-consumption design are smaller.
Description
Technical field
The present invention relates to a kind of master-slave flip-flops, more particularly, to a kind of master-slave flip-flop based on FinFET.
Background technology
In Digital Electronic Technique field, sequential logical circuit is made of storage circuit and combinational logic, and storage unit is used for
Keep the logic state of sequential logical circuit.Trigger belongs to circuit of the digital circuit compared with based on as a kind of storage circuit
One of, it plays an important role in digital circuitry.
With being constantly progressive for VISL technologies, in the digital circuitry of less demanding to the speed of service, power consumption is wanted
Continuous improvement is asked, the requirement to trigger performance is also harsher, it is desirable that trigger should have low-power consumption and low-power consumption simultaneously
Delay product.The performance of power consumption, power-consumption design and the area of trigger etc. will directly influence entire low-speed digital circuit system
The overall performance of system.Currently, circuit diagram such as Fig. 1 of extensive traditional clock d type flip flop is used in low-speed digital circuit system
Shown, which includes input circuit, main latch and from latch, and wherein input circuit is by three phase inverter structures
At, for accessing input signal and clock control signal, main latch and from latch respectively by four two input nand gate groups
At.In the clock d type flip flop, main latch and from being included at least in the internal structure of each two input nand gate in latch
Four fin field-effect transistors (FinFET is managed, Fin Field-Effect Transistor) wrap in each two input nand gate
The fin field-effect transistor contained is all under total grid (Common Multi-Gate) operating mode, although clock D is touched as a result,
Send out that device overall structure is relatively simple, but the FinFET pipe quantity consumed in its overall structure is more, area is larger, have compared with
Big power consumption generates, and power-consumption design is also larger, this is unfavorable for the design of low consumption circuit.
Invention content
Technical problem to be solved by the invention is to provide a kind of area is smaller, power consumption is relatively low, and power-consumption design is smaller
The master-slave flip-flop based on FinFET.
Technical solution is used by the present invention solves above-mentioned technical problem：A kind of master-slave flip-flop based on FinFET,
Including input circuit, main latch and from latch, the input circuit includes the first phase inverter, the second phase inverter and third
Phase inverter, the input terminal of first phase inverter are the input end of clock of the input circuit, are controlled for incoming clock
Signal, the output end of first phase inverter is connected with the input terminal of second phase inverter and its connecting pin is described
The output end of the inversion clock output end of input circuit, second phase inverter is the clock output of the input circuit
End, the input terminal of the third phase inverter are the data input pin of the master-slave flip-flop, the third phase inverter
Output end is the data output end of the input circuit, and the main latch includes the first FinFET pipes, the 2nd FinFET
Pipe, the 3rd FinFET pipes, the 4th FinFET pipes and the 4th phase inverter；The first FinFET pipes and the 3rd FinFET
Pipe is p-type FinFET pipes, and the 2nd FinFET pipes and the 4th FinFET pipes are N-type FinFET pipes, described
The quantity of the first FinFET pipe fins be 1, the quantity of the 2nd FinFET pipe fins is 1, the 3rd FinFET pipe fins
Quantity be 1, the quantity of the 4th FinFET pipe fins is 1；The front gate of the first FinFET pipes, described first
The backgate of FinFET pipes and the back-gate connection of the 4th FinFET pipes and the clock that its connecting pin is the main latch
Input terminal, the input end of clock of the main latch are connected with the output terminal of clock of the input circuit, and described first
The data that the source electrode of FinFET pipes is connected with the front gate of the 2nd FinFET pipes and its connecting pin is the main latch
Input terminal, the data input pin of the main latch are connected with the data output end of the input circuit, and described second
The backgate of FinFET pipes is the inversion clock input terminal of the main latch, the inversion clock input terminal of the main latch
It is connected with the inversion clock output end of the input circuit, the draining of the first FinFET pipes, the 4th reverse phase
The drain electrode of the input terminal of device, the 3rd FinFET pipes is connected with the drain electrode of the 4th FinFET pipes, and described second
The draining of FinFET pipes, front gate, the third of the output end of the 4th phase inverter, the 3rd FinFET pipes
The backgate of FinFET pipes connects connection with the front gate of the 4th FinFET pipes and its connecting pin is the main latch
Data output end, the source electrodes of the 3rd FinFET pipes access power supply, the source electrode of the 2nd FinFET pipes and described
The source grounding of 4th FinFET pipes；The slave latch includes the 5th FinFET pipes, the 6th FinFET pipes, the 7th
FinFET pipes, the 8th FinFET pipes, the 5th phase inverter and hex inverter；The 5th FinFET pipes and the described the 7th
FinFET pipes are p-type FinFET pipes, and the 6th FinFET pipes and the 8th FinFET pipes are N-type FinFET
The quantity of pipe, the 5th FinFET pipe fins is 1, and the quantity of the 6th FinFET pipe fins is the 1, the described the 7th
The quantity of FinFET pipe fins is 1, and the quantity of the 8th FinFET pipe fins is 1；The front gate of the 5th FinFET pipes, institute
The backgate for the 5th FinFET pipes stated, the back-gate connection of the 8th FinFET pipes and its connecting pin are described from latch
Inversion clock input terminal, the inversion clock output of the inversion clock input terminal from latch and the input circuit
End connection, the source electrode of the 5th FinFET pipes is connected with the front gate of the 6th FinFET pipes and its connecting pin is described
Slave latch data input pin, the data output end of the data input pin and the main latch from latch
Connection, the backgates of the 6th FinFET pipes are the input end of clock from latch, it is described from latch when
Clock input terminal is connected with the output terminal of clock of the input circuit, the draining of the 5th FinFET pipes, the described the 5th
The drain electrode of the input terminal of phase inverter, the 7th FinFET pipes is connected with the drain electrode of the 8th FinFET pipes, described
The draining of 6th FinFET pipes, the front gate of the output end of the 5th phase inverter, the 7th FinFET pipes, described
The backgate of seven FinFET pipes, the front gate of the 8th FinFET pipes are connected with the input terminal of the hex inverter and it connects
It is the oppisite phase data output end from latch to connect end, and the output end of the hex inverter is described from latch
Data output end, the source electrodes of the 7th FinFET pipes accesses power supply, the source electrode of the 6th FinFET pipes and described
The 8th FinFET pipes source grounding.
First phase inverter includes the 9th FinFET pipes and the tenth FinFET pipes, and the 9th FinFET pipes are P
Type FinFET pipes, the tenth FinFET pipes are N-type FinFET pipes, and the quantity of the 9th FinFET pipe fins is 2, described
The tenth FinFET pipe fins quantity be 1；The source electrode of the 9th FinFET pipes accesses power supply, the 9th FinFET pipes
Front gate, the backgate of the 9th FinFET pipes, the front gate of the tenth FinFET pipes and the tenth FinFET pipe
Back-gate connection and input terminal that its connecting pin is first phase inverter, the drain electrode of the 9th FinFET pipes and described
The tenth FinFET pipes drain electrode connection and its connecting pin be first phase inverter output end, the tenth FinFET
The source electrode of pipe is grounded, and second phase inverter, the third phase inverter, the 4th phase inverter, the described the 5th are instead
The circuit structure of phase device and the hex inverter is identical as first phase inverter.
Compared with the prior art, the advantages of the present invention are as follows pass through the first phase inverter and the second phase inverter in input circuit
Clock control module is constituted, third phase inverter is as data inserter, the 4th phase inverter, the first FinFET pipes, the 2nd FinFET
Pipe, the 3rd FinFET pipes and the 4th FinFET pipes constitute main latch, the 5th phase inverter, the 5th FinFET pipes, the 6th FinFET
Pipe, the 7th FinFET pipes and the 8th FinFET pipes are constituted from latch；The working condition of main latch is by external timing signal CLK
Control, as CLK=0, main latch, while second is written through third phase inverter and the first FinFET pipes in input data D
FinFET pipes work, and are modified to the input data D that main latch is written at the data output end of main latch, with compensation
The propagation threshold of first FinFET pipes loses, and the 3rd FinFET pipes, the 4th FinFET pipes and the 4th phase inverter are combined into reverse phase
Device ring so that the data output end f of main latch1Data D can be kept, and the 5th FinFET pipes and the 6th FinFET pipes end
It has cut off the data output end of main latch and from the contact between the data input pin of latch, has been exported from the data of latch
The trigger signal Q at end is kept, and is controlled from the working condition of latch by reversed clock signal clk b, as CLKb=0, first
FinFET is managed and the 2nd FinFET pipes disconnect, and main latch is in high impedance status, outer input data D cut-offs, at this time from lock
The 5th FinFET pipes in storage and the work of the 6th FinFET pipes, the data output end f of main latch1The data D of storage is passed
Enter from latch and the data output end from latch is output to by hex inverter, realizes the output of data, it is of the invention
Based on the master-slave flip-flop of FinFET to clock overlapping be insensitive, in working condition, operating current mainly by
Electric current in main latch and from the electric current composition in latch；As CLK=1, main latch does not work, and will be counted from latch
According to output, the operating current of entire circuit is the electric current from latch at this time, as CLK=0, main latch work, from lock
Storage does not work, and the operating current of entire circuit is the electric current of main latch at this time, and thus master-slave flip-flop of the invention exists
On the basis of correct work-based logic, circuit structure is simple, and trigger function is realized using the transistor of negligible amounts,
And main latch and from latch work alternatively, in the case where not influencing circuit performance, circuit area, power consumption and power consumption are prolonged
Shi Jijun is smaller.
Description of the drawings
Fig. 1 is the circuit diagram of traditional master-slave flip-flop；
Fig. 2 is the circuit diagram of the master-slave flip-flop based on FinFET of the present invention；
Fig. 3 (a) is the circuit diagram of the first phase inverter of the master-slave flip-flop based on FinFET of the present invention；
Fig. 3 (b) is the graphical diagram of the first phase inverter of the master-slave flip-flop based on FinFET of the present invention；
Fig. 4 be normal voltage (1V) under, it is of the invention based on the master-slave flip-flop of FinFET under BSIMIMG standard technologies
Simulation waveform；
Fig. 5 be superthreshold threshold voltage (0.8V) under, it is of the invention based on the master-slave flip-flop of FinFET in BSIMIMG standard works
Simulation waveform under skill is such as.
Specific implementation mode
Below in conjunction with attached drawing embodiment, present invention is further described in detail.
Embodiment one：As shown in Fig. 2, a kind of master-slave flip-flop based on FinFET, including input circuit, main latch and
From latch, input circuit includes the first phase inverter F1, the second phase inverter F2 and third phase inverter F3, and the first phase inverter F1's is defeated
Enter the input end of clock that end is input circuit, signal CLK, the output end and second of the first phase inverter F1 are controlled for incoming clock
The inversion clock output end that the input terminal of phase inverter F2 connects and its connecting pin is input circuit, for exporting clock control signal
The output end of the inversion signal CLKb, the second phase inverter F2 of CLK are the output terminal of clock of input circuit, and third phase inverter F3's is defeated
Enter the data input pin that end is master-slave flip-flop, for accessing external data D, the output end of third phase inverter F3 is input circuit
Data output end, main latch include the first FinFET pipes M1, the 2nd FinFET pipes M2, the 3rd FinFET pipes M3, the 4th
FinFET pipes M4 and the 4th phase inverter F4；First FinFET pipes M1 and the 3rd FinFET pipes M3 is that p-type FinFET is managed, and second
FinFET pipes M2 and the 4th FinFET pipes M4 is N-type FinFET pipes, and the quantity of the first FinFET pipe M1 fins is 1, second
The quantity of FinFET pipe M2 fins is 1, and the quantity of the 3rd FinFET pipe M3 fins is 1, and the quantity of the 4th FinFET pipe M4 fins is 1；The
Front gate, the backgate of the first FinFET pipes M1 and the back-gate connection of the 4th FinFET pipes M4 of one FinFET pipes M1 and its connecting pin is
The input end of clock of main latch, the input end of clock of main latch are connected with the output terminal of clock of input circuit, and first
The data input pin that the front gate of the source electrode of FinFET pipes M1 and the 2nd FinFET pipes M2 connect and its connecting pin is main latch, it is main
The data input pin of latch is connected with the data output end of input circuit, and the backgate of the 2nd FinFET pipes M2 is main latch
Inversion clock input terminal, the inversion clock input terminal of main latch are connected with the inversion clock output end of input circuit, and first
The drain electrode of FinFET pipes M1, the input terminal of the 4th phase inverter F4, the drain electrode of the 3rd FinFET pipes M3 and the 4th FinFET pipes M4
Drain electrode connection, the drain electrode of the 2nd FinFET pipes M2, the output end of the 4th phase inverter F4, the 3rd FinFET pipes M3 front gate, third
The data that the backgate of FinFET pipes M3 connects connection with the front gate of the 4th FinFET pipes M4 and its connecting pin is main latch export
The source electrode at end, the 3rd FinFET pipes M3 accesses power vd D, the source electrode of the source electrode and the 4th FinFET pipes M4 of the 2nd FinFET pipes M2
It is grounded；Include the 5th FinFET pipes M5, the 6th FinFET pipes M6, the 7th FinFET pipes M7, the 8th FinFET pipes from latch
M8, the 5th phase inverter F5 and hex inverter F6；5th FinFET pipes M5 and the 7th FinFET pipes M7 is p-type FinFET pipes,
6th FinFET pipes M6 and the 8th FinFET pipes M8 is N-type FinFET pipes, and the quantity of the 5th FinFET pipe M5 fins is the 1, the 6th
The quantity of FinFET pipe M6 fins is 1, and the quantity of the 7th FinFET pipe M7 fins is 1, and the quantity of the 8th FinFET pipe M8 fins is 1；The
Front gate, the backgate of the 5th FinFET pipes M5, the back-gate connection of the 8th FinFET pipes M8 and its connecting pin of five FinFET pipes M5 is
From the inversion clock input terminal of latch, the inversion clock output end of inversion clock input terminal and input circuit from latch connects
It connects, the front gate connection of the source electrode of the 5th FinFET pipes M5 and the 6th FinFET pipes M6 and its connecting pin are defeated from the data of latch
Enter end, the data output end of data input pin and main latch from latch connect, the backgate of the 6th FinFET pipes M6 for from
The output terminal of clock of the input end of clock of latch, input end of clock and input circuit from latch connects, the 5th FinFET
The drain electrode of pipe M5, the input terminal of the 5th phase inverter F5, the drain electrode of the 7th FinFET pipes M7 and the drain electrode of the 8th FinFET pipes M8 connect
It connects, the drain electrode of the 6th FinFET pipes M6, the output end of the 5th phase inverter F5, the front gate of the 7th FinFET pipes M7, the 7th FinFET
The backgate of pipe M7, the front gate of the 8th FinFET pipes M8 are connected with the input terminal of hex inverter F6 and its connecting pin is from latch
Oppisite phase data output end, the output end of output reverse phase trigger signal Q, hex inverter F6 is to be exported from the data of latch
The source electrode at end, output trigger signal Q, the 7th FinFET pipes M7 accesses power vd D, the source electrode and the 8th of the 6th FinFET pipes M6
The source grounding of FinFET pipes M8.
Embodiment two：The present embodiment and embodiment one are essentially identical, differ only in the present embodiment, the first phase inverter F1
It is p-type FinFET pipes, the tenth FinFET pipes including the 9th FinFET pipes M9 and the tenth FinFET pipe M10, the 9th FinFET pipes M9
M10 is N-type FinFET pipes, and the quantity of the 9th FinFET pipe M9 fins is 2, and the quantity of the tenth FinFET pipe M10 fins is 1；9th
The source electrode of FinFET pipes M9 accesses power vd D, the front gate of the 9th FinFET pipes M9, the backgate of the 9th FinFET pipes M9, the tenth
The front gate of FinFET pipes M10 and the back-gate connection of the tenth FinFET pipes M10 and the input terminal that its connecting pin is the first phase inverter F1,
The drain electrode of 9th FinFET pipes M9 and the drain electrode connection of the tenth FinFET pipes M10 and the output that its connecting pin is the first phase inverter F1
End, the source electrode ground connection of the tenth FinFET pipes M10, the second phase inverter F2, third phase inverter F3, the 4th phase inverter F4, the 5th reverse phase
The circuit structure of device F5 and hex inverter F6 are identical as the first phase inverter F1.Circuit diagram such as Fig. 3 (a) of first phase inverter F1
It is shown, shown in graphical diagram such as Fig. 3 (b).
In order to verify the excellent benefit of the master-slave flip-flop based on FinFET of the invention, under BSIMIMG standard technologies, electricity
The input frequency on road be 100MHz, 400MHz, 800MHz and 1GHz under conditions of, using circuit simulation tools HSPICE to this hair
The performance of the bright master-slave flip-flop and traditional two kinds of circuits of master-slave flip-flop shown in FIG. 1 based on FinFET carries out emulation pair
It is 1V than, wherein the corresponding supply voltage VDD of BSIMIMG technology libraries, phase inverter is all made of two in traditional master-slave flip-flop
FinFET pipes realize that two input nand gates are realized using four FinFET pipes.Under normal voltage (1V), it is of the invention based on
Simulation waveform of the master-slave flip-flop of FinFET under BSIMIMG standard technologies is as shown in Figure 4；Superthreshold threshold voltage (0.8V)
Under, it is of the invention as shown in Figure 5 based on simulation waveform of the master-slave flip-flop of FinFET under BSIMIMG standard technologies.Point
Fig. 4 and Fig. 5 is analysed it is found that the master-slave flip-flop based on FinFET of the present invention has correct work-based logic.
Table 1 be under BSIMIMG standard technologies, input frequency be 100MHz when, the principal and subordinate of the invention based on FinFET
The performance comparison result of trigger and traditional two kinds of circuits of master-slave flip-flop.
Table 1
Known in analytical table 1：The present invention's is compared based on the master-slave flip-flop of FinFET with traditional master-slave flip-flop, though
So delay increases 19.34%, but number of transistors reduces 18, and total power consumption reduces by 21.63%, and power-consumption design reduces
6.47%, overall performance is significantly improved.
Table 2 be under BSIMIMG standard technologies, input frequency be 400MHz when, the principal and subordinate of the invention based on FinFET
The performance comparison result of trigger and traditional two kinds of circuits of master-slave flip-flop.
Table 2
Known in analytical table 2：The present invention's is compared based on the master-slave flip-flop of FinFET with traditional master-slave flip-flop, though
So delay increases 20.32%, but number of transistors reduces by 18 total power consumptions and reduces by 23.80%, and power-consumption design reduces
8.32%, overall performance is significantly improved.
Table 3 be under BSIMIMG standard technologies, input frequency be 800MHz when, the principal and subordinate of the invention based on FinFET
The performance comparison result of trigger and traditional two kinds of circuits of master-slave flip-flop.
Table 3
Known in analytical table 3：：The present invention's is compared based on the master-slave flip-flop of FinFET with traditional master-slave flip-flop,
Although delay increases 19.85%, number of transistors reduces 18, and total power consumption reduces by 25.68%, and power-consumption design reduces
10.93%, overall performance is significantly improved.
Table 4 is under BSIMIMG standard technologies, and when input frequency is 1G, the principal and subordinate of the invention based on FinFET triggers
The performance comparison result of device and traditional two kinds of circuits of master-slave flip-flop.
Table 4
Known in analytical table 4：：The present invention's is compared based on the master-slave flip-flop of FinFET with traditional master-slave flip-flop,
Although delay increases 19.28%, number of transistors reduces 18, and total power consumption reduces by 26.35%, and power-consumption design reduces
12.15%, overall performance is significantly improved.
In conclusion under the premise of not influencing circuit performance, master-slave flip-flop and biography of the invention based on FinFET
The master-slave flip-flop of system is compared, and the quantity of transistor reduces, and power consumption and power-consumption design have obtained larger optimization.
Claims (2)
1. a kind of master-slave flip-flop based on FinFET, including input circuit, main latch and from latch, input electricity
Road includes the first phase inverter, the second phase inverter and third phase inverter, and the input terminal of first phase inverter is the input
The input end of clock of circuit controls signal for incoming clock, and the output end of first phase inverter and described second is instead
The inversion clock output end that the input terminal of phase device connects and its connecting pin is the input circuit, second phase inverter
Output end is the output terminal of clock of the input circuit, and the input terminal of the third phase inverter is the master-slave flip-flop
Data input pin, the output end of the third phase inverter is the data output end of the input circuit, it is characterised in that
The main latch includes that the first FinFET pipes, the 2nd FinFET pipes, the 3rd FinFET pipes, the 4th FinFET pipes and the 4th are anti-
Phase device；The first FinFET pipes and the 3rd FinFET pipes are p-type FinFET pipes, the 2nd FinFET pipes
It is N-type FinFET pipes with the 4th FinFET pipes, the quantity of the first FinFET pipe fins is 1, described second
The quantity of FinFET pipe fins is 1, and the quantity of the 3rd FinFET pipe fins is 1, the quantity of the 4th FinFET pipe fins
It is 1；The back of the body of the front gate of the first FinFET pipes, the backgate and the 4th FinFET pipes of the first FinFET pipes
The input end of clock that grid connect and its connecting pin is the main latch, the input end of clock of the main latch and described
Input circuit output terminal of clock connection, the front gate of the source electrode and the 2nd FinFET pipes of the first FinFET pipes
Connection and the data input pin that its connecting pin is the main latch, the data input pin of the main latch and described
The data output end of input circuit connects, and the backgate of the 2nd FinFET pipes is defeated for the inversion clock of the main latch
Enter end, the inversion clock input terminal of the main latch is connected with the inversion clock output end of the input circuit, described
The draining of the first FinFET pipes, the drain electrode of the input terminal of the 4th phase inverter, the 3rd FinFET pipes and described
The 4th FinFET pipes drain electrode connection, the draining of the 2nd FinFET pipes, the output end of the 4th phase inverter, institute
The front gate for the 3rd FinFET pipes stated, the backgate of the 3rd FinFET pipes are connected with the front gate of the 4th FinFET pipes
Connection and the data output end that its connecting pin is the main latch, the source electrode of the 3rd FinFET pipes access power supply,
The source grounding of the source electrode and the 4th FinFET pipes of the 2nd FinFET pipes；
The slave latch includes the 5th FinFET pipes, the 6th FinFET pipes, the 7th FinFET pipes, the 8th FinFET pipes, the
Five phase inverters and hex inverter；The 5th FinFET pipes and the 7th FinFET pipes are p-type FinFET pipes, institute
The 6th FinFET pipes stated and the 8th FinFET pipes are N-type FinFET pipes, the number of the 5th FinFET pipe fins
Amount is 1, and the quantity of the 6th FinFET pipe fins is 1, and the quantity of the 7th FinFET pipe fins is the 1, the described the 8th
The quantity of FinFET pipe fins is 1；It is the front gate of the 5th FinFET pipes, the backgate of the 5th FinFET pipes, described
The back-gate connections of 8th FinFET pipes and its connecting pin are the inversion clock input terminal from latch, described from latch
The inversion clock input terminal of device is connected with the inversion clock output end of the input circuit, the source of the 5th FinFET pipes
Pole is connected with the front gate of the 6th FinFET pipes and its connecting pin is the data input pin from latch, described
It is connected from the data input pin of latch with the data output end of the main latch, the backgate of the 6th FinFET pipes
For the input end of clock from latch, the clock of the input end of clock and the input circuit from latch
Output end connects, the draining of the 5th FinFET pipes, the input terminal of the 5th phase inverter, the 7th FinFET
The drain electrode of pipe is connected with the drain electrode of the 8th FinFET pipes, the draining of the 6th FinFET pipes, the described the 5th anti-
The output end of phase device, the front gate of the 7th FinFET pipes, the backgate of the 7th FinFET pipes, the described the 8th
The front gate of FinFET pipes is connected with the input terminal of the hex inverter and its connecting pin is the reverse phase from latch
Data output end, the output end of the hex inverter are the data output end from latch, the described the 7th
The source electrode of FinFET pipes accesses power supply, and the source electrode of the 6th FinFET pipes and the source electrode of the 8th FinFET pipes connect
Ground.
2. a kind of master-slave flip-flop based on FinFET according to claim 1, it is characterised in that first reverse phase
Device is managed including the 9th FinFET and the tenth FinFET pipes, and the 9th FinFET pipes are managed for p-type FinFET, and the described the tenth
FinFET pipes are N-type FinFET pipes, and the quantity of the 9th FinFET pipe fins is 2, the number of the tenth FinFET pipe fins
Amount is 1；The source electrode of the 9th FinFET pipes accesses power supply, the front gate of the 9th FinFET pipes, the described the 9th
The backgate of FinFET pipes, the back-gate connection of the front gate of the tenth FinFET pipes and the tenth FinFET pipes and its connection
End is the input terminal of first phase inverter, the drain electrode of the 9th FinFET pipes and the leakage of the tenth FinFET pipes
The output end that pole connects and its connecting pin is first phase inverter, the source electrode ground connection of the tenth FinFET pipes are described
The second phase inverter, the third phase inverter, the 4th phase inverter, the 5th phase inverter and the described the 6th anti-
The circuit structure of phase device is identical as first phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810092762.7A CN108494386B (en) | 2018-01-31 | 2018-01-31 | FinFET-based master-slave trigger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810092762.7A CN108494386B (en) | 2018-01-31 | 2018-01-31 | FinFET-based master-slave trigger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108494386A true CN108494386A (en) | 2018-09-04 |
| CN108494386B CN108494386B (en) | 2021-06-15 |
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| CN201810092762.7A Active CN108494386B (en) | 2018-01-31 | 2018-01-31 | FinFET-based master-slave trigger |
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