CN102916687B - Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology - Google Patents
Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology Download PDFInfo
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Abstract
The invention relates to design of a CMOS (complementary metal oxide semiconductor) of a ternary clock generator. As known to all, a ternary clock has the characteristic of multiple trigger edges and is favorable for reducing system power consumption when used for a digital circuit; but the survey found that the ternary clock is generated only by means of simulation through a signal source by simulation software at present, and no simple and practical circuits for generating the ternary clock exist domestic and overseas. The invention also relates to an encoding method which includes of taking a binary clock output from a quartz crystal oscillator as an input signal to encode the ternary clock of an output signal, then designing the ternary clock generator according to an encoding scheme and the transmission voltage switching theory, thereby filling the gap in the circuits for generating the ternary clock and improving practicality of the ternary clock. As simulation test proved, the ternary clock generator has correct functions. According to analysis results, the ternary clock generator is simple in structure, high in performance, favorable for improving practicability of the digital circuit, and capable of generating high-quality of ternary clock serving as the clock signal of a digital system so as to reduce power consumption of the system.
Description
Technical field
The invention belongs to the design field of the ternary clock generator of integrated circuit.The present invention is the ternary clock generator based on CMOS technology, and the high two-value clock of the frequency stability utilizing quartz oscillator to produce designs the ternary clock generator meeting real requirement as input signal.This ternary clock generator can be applicable to digital circuitry, and its ternary clock signal exported is as the clock drive signals of sequential logical circuit.Because ternary clock has more triggering edge in one-period, therefore digital circuitry is when adopting ternary clock while maintenance data processing speed is constant, can reduce the clock frequency of system, and then be conducive to the power consumption of reduction system.
Background technology
Because what ternary (digital) signal carried contains much information, so three volued digital system has plurality of advantages compared to bi-level digital system.As, for certain logic function, the signal transmssion line that the area of its integrated circuit is less and required is less; For certain data volume, its memory cell needed is less [1] also.In addition, in three-valued logic, a lot of logic and arithmetical operation can be carried out faster, just can complete [2] by less operating procedure.Similarly, ternary clock signal also has hopping edge more more than traditional two-value clock within a clock cycle.Utilize this feature and the three value dual-edge triggers based on ternary clock that design, there is the features [3] such as circuit structure is simple and low in energy consumption.And the d type flip flop with triggering edge control that document [4] proposes is also using ternary clock as clock drive signals.In document [5], be also used as the clock of trigger because ternary clock contains the amount of information more than two-value clock and put several control signals.As can be seen from above-mentioned research, ternary clock signal has obtained practicable application and has shown its superiority in digital circuit.But above-mentioned research has a common feature, the ternary clock be namely used to is all produce with simulation software simulation, but not is produced by the circuit of reality.Make a general survey of Research Literature both domestic and external to find, there is no Research Literature at present and mention the Method and circuits producing ternary clock, also, the ternary clock generator of a simple and stable practicality is also a vacancy at present.And clock is most important signal in digital system, the effect in sequence circuit controls and coordinate whole digital system normally to work.Two-value clock signal can produce [6] by quartz crystal multivibrator, and ternary clock can only be produced by simulation software simulation at present.This is by the practical application of restriction based on the digital system of ternary clock.For solving the problem in this practical application, the high two-value clock of the frequency stability that the present invention utilizes quartz oscillator to produce is as input signal, application transport voltage switch theory [7] designs ternary clock generator from switching stage, circuit in the hope of design is simple, stability and high efficiency and practicality, to solve the problem lacking ternary clock generator at present.
List of references
[1]Dhande，A.P.，and Ingole，V.T.：Design of 3-Valued R-S & D flip-flops based onsimple ternary gates，International journal of software engineering & knowledgeengineering，2005，15，(2)，pp.411-417
[2]Moaiyeri，M.H.，Doostaregan，A.，Navi，K.：Design of energy-efficient androbust ternary circuits for nanotechnology，IET Circuits，Devices & Systems，2011，5，(4)，pp.285-296
[3] Hu Junfeng, Shen Jizhong, Yao Maoqun etc. Design of low power multivalued double-edge-triggered flip-flop [J]. journal of Zhejiang university (engineering version), 2005,39 (11): 1699-1702.
[4]E.Sipos，C.Miron：Master-Slave Ternary D Flip-Flap-Flops with TriggeredEdges Control.IEEE International Conference on Automation Quality andTesting Robotics(AQTR)，Cluj-Napoca，Romania，May 2010，Vol.2，pp.1-6
[5]WU Xun-wei，SHEN Ji-zhong，CHEN Xie-xiong.CMOS multivalued flip-flopsbased on new presetting scheme and transmission function theory[J].Proc.IWST，Beijing，1994：74～77.
[6]
D.M.：Nonlinear analysis of a quartz multivibrator with acomplementary switch，IEE Proceedings G Electronic Circuits and Systems，1985，132，(2)，pp.33-38
[7]Wu，X.，Prosser，F.：Design of ternary CMOS circuits based on transmissionfunction theory，International Journal of Electronics，1988，65，(5)，pp.891-905
Summary of the invention
The object of the invention is invention one and can produce the simple efficient work of structure and the ternary clock generator meeting real requirement.This ternary clock generator will meet following 5 requirements:
1) ternary clock exported meets the principle making full use of ternary (digital) signal;
2) circuit structure simply, easily realizes, and circuit working is stable and efficient;
3) ternary clock signal meets the requirement about clock signal, namely should have high frequency and range stability;
4) the ternary clock signal meeting high frequency environment for use and require can be produced;
5) the ternary clock signal produced can meet the actual power requirement used.
For invention has the ternary clock generator of above feature, the technical scheme of its design comprises following five steps:
A, to define by the waveform of principle to ternary clock making full use of ternary (digital) signal;
B, according to the definition of ternary clock, binary-coding is carried out to the logical value of ternary clock;
C, the binary-coding of all ternary clocks to be analyzed, the feasibility realized by coding, find out practical coding;
D, by transmission voltage switching theorem, the encoding scheme of above-mentioned practicality is set up to the Mathematical Modeling of ternary clock generator;
E, according to the Mathematical Modeling set up, the CMOS technology that application transport voltage switch is theoretical and ripe, designs ternary clock generator.
Accompanying drawing explanation
Fig. 1 is ternary clock three kinds of typical waveforms.The two-value clock that Fig. 2 utilizes quartz oscillator to produce as input signal to produce the cmos circuit figure of ternary clock, i.e. ternary clock generator cmos circuit figure.Fig. 3 is the ternary clock transient waveform figure that ternary clock generator produces.Fig. 4 is the design flow diagram of the ternary clock generator based on CMOS technology.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described further.
The definition of 1 ternary clock waveform
Because ternary clock (TCLK) has three kinds of level, namely { 0,1,2}, its typical waveform is just like three kinds of forms shown in Fig. 1 (a), (b) He (c) for TCLK ∈.As can be seen from three kinds of clock waveforms, in the one-period of ternary clock, all there is ascent stage and the decline stage of clock level.In the ternary clock waveform shown in Fig. 1 (a), its decline stage directly jumps to 0 by 2; And in Fig. 1 (b), the ascent stage of ternary clock directly jumps to 2 by 0.In fact, both of these case all still belongs to the feature of two-value clock in clock signal, does not also make full use of the feature that ternary (digital) signal contains much information.And in the waveform shown in Fig. 1 (c), the ascent stage of clock and decline stage are all three values, this takes full advantage of the advantage contained much information of ternary (digital) signal.In the ternary clock shown in Fig. 1 (c), saltus step and twice time saltus step on twice in the clock cycle, is had to have four edges.When clock frequency is identical, its edge number is than many one times of two-value clock.Therefore, the present invention design ternary clock generator with the ternary clock signal shown in output map 1 (c) for design object.Specifically, the duration of 0 level in ternary clock, 1 level of ascent stage, 2 level and 1 level of decline stage respectively accounted for for 1/4th cycles.
Three kinds of logical values of 2 pairs of ternary clocks carry out binary coding
Nearly all produced by quartz oscillator as the two-value clock signal controlling bi-level digital circuit working and provide at present.This is because the distinctive physical property of quartz crystal, it can produce the high periodic signal of frequency stability.In order to the high ternary clock of frequency stability can be obtained, this characteristic of quartz crystal also must be utilized.Therefore the present invention will utilize quartz oscillator to design ternary clock generator, and namely with two-value clock CLK ∈, { 0,2} designs ternary clock generator as input signal.
As can be seen from the waveform shown in Fig. 1 (c), ternary clock has one of four states in one cycle, here in order to the convenience of problem analysis, 1 level of ascent stage and 1 level of decline stage are regarded as two different states, be labeled as+1 and-1 respectively.Owing to mentioning above, the input signal of the present invention using two-value clock as ternary clock generator, therefore can be the one of four states coding of output signal with binary signal, this one of four states be respectively 0 ,+1,2 and-1.Because status number is 4, so need to encode to this one of four states with 2 binary signal BA.In theory, 2 binary signal BA, 4 states of encoding have 24 kinds of encoding schemes.But consider that output signal is the periodic signal that an order is fixed as 0 →+1 → 2 →-1 → 0, input signal is a two-value clock square wave, the ternary clock that the circuit of design will be simple and easy to realize and export does not have the requirements such as burr (burr is caused by the transition state in circuit), therefore, have 4 kinds to the practicable scheme of these 4 output state codings with 2 binary signal BA, specific coding scheme is as shown in table 1.
The binary coding of three kinds of logical values of table 1 ternary clock
3 set up the Mathematical Modeling of ternary clock generator by encoding scheme
Four kinds of encoding schemes of table 1 can be used for designing ternary clock generator, and the ternary clock generator of design all has similar structure.The concrete ins and outs of ternary clock Generator Design are described for the scheme 0 of table 1 here.
As can be seen from the scheme 0 of table 1, the output of ternary clock logical zero is controlled by BA=02, so just need by the operating characteristic of metal-oxide-semiconductor one exports high level control signal in BA=02 situation, so just can control with a metal-oxide-semiconductor logical zero exporting ternary clock, its advantage exports internal resistance to reach minimum, only has the conducting resistance of a metal-oxide-semiconductor.According to above description, the switching stage function expression of the signal OUT0 of the control output logic 0 formed by two input signal BA can be listed, shown in (1).Ternary clock logical one is controlled to export by BA=20 or 00, and namely ternary clock logical one is controlled to export by A=0.If also control output logic 1 by a NMOS tube, so the switching stage function expression of this control signal OUT1 is such as formula shown in (2).And ternary clock logic 2 is controlled to export by BA=22, if control output logic 2 by a PMOS, this just needs the control signal OUT2 of an output low level, and the switching stage logical function expression formula of this control signal OUT2 is such as formula shown in (3).According to formula (1), (2) and (3) and transmission voltage switching theorem, the switching stage function expression of ternary clock TCLK can be exported, shown in (4).Here have any to pay special attention to, formula (1), (2) and (3) are the function expressions of the switching stage based on two-value.And formula (4) is the function expression of the switching stage of three values.These four switching stage function expressions are exactly the Mathematical Modeling of ternary clock generator.
OUT0＝A*B
0.5#0*
0.5B (1)
OUT1＝1*A
0.5#0*
0.5A (2)
TCLK＝0*
1.5(OUT0)#1*
1.5(OUT1)#2*(OUT2)
0.5(4)
4 design ternary clock generator according to the application of mathematical model correlation theory
Realize the Mathematical Modeling of ternary clock generator, first will realize 2 binary codings in table 1, this needs the binary signal BA of 2.Because existing input signal A is a two-value clock signal exported by quartz oscillator, therefore, also need the binary signal B of acquisition the 2nd.Two-value clock signal A is that a level value occurs that order is the periodic square wave of 0 → 2 → 0.As can be seen from the encoding scheme of table 1, signal B is also a periodic square wave, and its frequency is the half of signal A, therefore can carry out two divided-frequency to signal A and can obtain signal B.Again according to Mathematical Modeling and the transmission voltage switching theorem of ternary clock generator, namely can realize ternary clock generator with metal-oxide-semiconductor, the cmos circuit figure of ternary clock generator as shown in Figure 2.In fig. 2, frequency-halving circuit module can be formed with a conventional d type flip flop.The circuit of formation control signal OUT0, OUT1 and OUT2 is formed with common metal-oxide-semiconductor.Form ternary clock signal TCLK to need to adopt the metal-oxide-semiconductor with multistage unlatching threshold value, but according to the characteristic of metal-oxide-semiconductor transmission voltage, the metal-oxide-semiconductor of the two-stage threshold value for ternary circuit can not be adopted here, and adopt common metal-oxide-semiconductor.Specifically, the logical zero of ternary clock and 1 is controlled to export by common NMOS tube, and logic 2 is controlled to export by common PMOS.Concrete cmos circuit figure as shown in Figure 2.Adopt common metal-oxide-semiconductor to mainly contain two large advantages to realize ternary clock generator: the first, the manufacturing process of integrated circuit can reduce greatly, saves manufacturing cost; The second, owing to have employed the metal-oxide-semiconductor of single threshold value, reduce the threshold value of part metal-oxide-semiconductor, the switching speed of circuit can greatly improve, and therefore the frequency response of circuit also can be improved greatly.
In a word, be connected by the input signal A of the cmos circuit shown in clock signal CLK and Fig. 2 of quartz crystal multivibrator, can form ternary clock generator, its output signal is exactly the ternary clock signal meeting designing requirement.
Experimental verification and analysis:
1 based on the simulation result of the ternary clock generator of CMOS technology and analysis
Below the work behavior of ternary clock generator is analyzed.Because the triggering edge of the d type flip flop forming frequency divider in Fig. 2 is determined, namely trailing edge triggers, therefore, the state transitions behavior of two binary signals that the output signal B of frequency divider and two-value clock CLK=A forms also will be determined, namely 00 → 02 → 20 → 22 → 00, be the circuit of the output periodically logical value of error-free state energy self-starting.Like this, the scheme 0 periodically by table 1 also exports and these states ternary clock logical value one to one by ternary clock generator, can obtain the periodic ternary clock signal as shown in Fig. 1 (c) like this.
For the correctness of the work of simulation ternary clock generator, adopt the CMOS technology parameter of HSPICE software and TSMC180nm to simulate ternary clock generator below, during simulation, the output loading of ternary clock generator is 30fF.As shown in Figure 3, the CLK in figure, i.e. A, be the two-value clock that simulation quartz crystal multivibrator exports, B is the output waveform after clock CLK two divided-frequency to the transient waveform of simulation gained, and TCLK is the ternary clock that ternary clock generator exports.Transient waveform is as shown in Figure 3 known, and ternary clock generator can produce the periodic ternary clock meeting designing requirement, and its frequency is the half of input two-value clock frequency.The analog result of Fig. 3 shows, the ternary clock generator of the present invention's design has correct logic function, can reliablely and stablely work.Although it is noted that the frequency of the ternary clock exported is only the half of two-value clock, the triggering edge with the trigger sensitivity of two-value clock equal number can be provided within the identical time.Because the quartz crystal with various resonance frequency has been made into the product of standardization and seriation, so the ternary clock generator proposed according to the present invention, the ternary clock of various different frequency all can obtain easily.
The amplitude of ternary clock produced ternary clock generator below and frequency stability are analyzed, and whether meet its instructions for use as clock signal using the clear and definite ternary clock that it produces.The requirement of clock signal should have high range stability also will have high frequency stability.Switching stage circuit is as shown in Figure 2 known, because the logical value of the ternary clock exported is that ternary (digital) signal source directly exports formation through the metal-oxide-semiconductor of a conducting, output level is more stable and output internal resistance is also minimum, so the stability of its amplitude is higher, and can provide larger power output.Frequency of oscillation due to quartz crystal has high frequency stability, and the frequency of ternary clock depends on the frequency of the two-value clock of input, so the same almost with quartz crystal multivibrator of the frequency stability of ternary clock, there is high frequency stability.As can be seen here, the ternary clock generator of the present invention's design meets the instructions for use of clock signal in fixed ampllitude and frequency stabilization two completely, and can provide larger power output.
2 sum up
The advantage that the present invention contains much information by making full use of ternary (digital) signal, determines the waveform morphology of ternary clock, proposes a kind of design producing ternary clock, and then has carried out the design of switching stage according to transmission voltage switching theorem to it.The ternary clock generator architecture of the present invention's design is simple, and except in order to realize except the d type flip flop of divide-by-two function in circuit, remaining circuit part employs 11 common metal-oxide-semiconductors altogether.According to HSPICE analog result, ternary clock generator has correct logic function, circuit stable and reliable operation.The ternary clock exported meets clock signal and has high amplitude and the requirement of frequency stability, and its frequency is the same with the frequency of two-value clock, has controllability and accuracy.In addition, the saltus step of the saltus step of the ternary clock of generation and the two-value clock of input has clear and definite corresponding relation, and this is the basis of synchronously providing convenience between ternary clock with two-value clock.The service condition of ternary clock generator of the present invention's design is low, outsidely only needs to provide a conventional quartz oscillator and ternary (digital) signal source, very easily carries out practical application.The design of the generation ternary clock that the present invention proposes also can be used for two-value clock to be converted to ternary clock.Last it is noted that the ternary clock of other forms, as Fig. 1 (a) and the waveform of (b), the method for designing that the present invention also can be used to propose produces.
Claims (1)
1., based on the ternary clock generator of CMOS technology, the two-value clock CLK utilizing to input produces the ternary clock TCLK that in the clock cycle of output, logical value switching sequence is 0-1-2-1, and it is characterized in that, it at least comprises:
1. the two-value clock CLK of input is used as binary signal A, the frequency-halving circuit utilizing the d type flip flop triggered by trailing edge to form carries out two divided-frequency to a-signal, obtains binary signal B and the inverted signal thereof of frequency-halving circuit output
2. two-value clock CLK and binary signal B and inverted signal thereof is utilized
produce binary signal OUT0, namely realize switching stage expression formula OUT0=A*B with common metal-oxide-semiconductor
0.5#0*
0.5b obtains signal OUT0, binary signal OUT0 is connected to the grid that a source electrode connects the NMOS tube of logical value 0;
3. use CMOS inverter to produce binary signal OUT1 to the two-value clock CLK negate of input, binary signal OUT1 is connected to the grid that a source electrode connects the NMOS tube of logical value 1;
4. the inverted signal of two-value clock CLK and inverted signal and signal B is utilized
produce binary signal OUT2, namely realize switching stage expression formula with common metal-oxide-semiconductor
obtain signal OUT2, binary signal OUT2 is connected to the grid that a source electrode connects the PMOS of logical value 2;
5. the drain electrode that described three grids connect the metal-oxide-semiconductor of signal OUT0, OUT1 and OUT2 is linked together as the output of ternary clock TCLK, so just obtain the described ternary clock generator based on CMOS technology, producing output level logic value switching sequence within a clock cycle at its output is the ternary clock TCLK of 0-1-2-1.
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| CN104639110B (en) * | 2015-03-04 | 2017-10-03 | 浙江水利水电学院 | A kind of QCG units being made up of RSFF |
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