CN104333365A - Three-segment time digital converter (TDC) circuit - Google Patents
Three-segment time digital converter (TDC) circuit Download PDFInfo
- Publication number
- CN104333365A CN104333365A CN201410536431.XA CN201410536431A CN104333365A CN 104333365 A CN104333365 A CN 104333365A CN 201410536431 A CN201410536431 A CN 201410536431A CN 104333365 A CN104333365 A CN 104333365A
- Authority
- CN
- China
- Prior art keywords
- signal
- time
- clk
- circuit
- rising edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a three-segment time digital converter (TDC) circuit. Time interval measurement is completed through high-segment quantization, middle-segment quantization and low-segment quantization. A high-segment TDC adopts a linear feedback shift register (LFSR) structure to realize wide-range measurement. A middle-segment TDC adopts a ring oscillator structure, searches the position of the rising edge of a high-frequency clock through uniform phase resolution, triggers a latch signal and a middle-segment counting signal, and completes middle-segment measurement with a synchronous counter. A low-segment ring oscillator TDC completes finer measurement of quantization error, adopts the same structure as the middle segment, and adopts a mode of decoding before transmission. All data is output sequentially and serially in binary form through a logic control circuit. Compared with a traditional three-segment TDC, the TDCs of the invention can realize delay unit multiplexing to obtain a better architecture design and a smaller layout area. Under the same detection accuracy, the system power consumption generated is reduced significantly. Therefore, the three-segment time digital converter (TDC) circuit can be applied to a high-speed and high-precision time measurement system.
Description
Technical field
The present invention relates to a kind of syllogic time-to-digital conversion circuit, can be used in high-speed, high precision time measurement system.
Background technology
Time-to-digit converter (Time Digital Converter, TDC) is a kind of common circuit of time measurement, and it is that the time interval is converted into high-precision digital value, and realizes numeral output.Be widely used in electronic applications at present, as in all-digital phase-locked loop ADPLL, improve the time response of its test component and signal.In recent years, TDC of greatest concern was the structure using high speed CMOS digital circuit, and main cause is that signal-under-test can realize higher time precision.TDC accuracy is studied, will application and the quality assurance of TDC be conducive to.
Along with the longitudinal directionization of split-second precision quantification technique develops, in analog IC field, occur that a collection of take time-to-digit converter as the high-performance analog devices of core, for example high-speed low-power-consumption analog-digital converter and all-digital phase-locked loop etc., overcome a series of because process restriction and the design challenges of insurmountable analog circuit, the design for analog IC opens brand-new design approach.Therefore, time-to-digit converter, by becoming a bridge of contact simulation continuous time signal amount and digital discrete signal amount, becomes a uncharted field of hybrid digital-analog integrated circuit design.
Summary of the invention
Goal of the invention: for above-mentioned prior art, proposes a kind of syllogic time-to-digital conversion circuit, compares traditional syllogic TDC structure, while realizing wide region, high-acruracy survey, simplifies circuit structure, reduces the area of system and power consumption.
Summary of the invention: a kind of syllogic time-to-digital conversion circuit, comprises high section linear feedback shift register, first phase adjustment circuit, delay matching circuit, stage casing bit time digital conversion circuit, adjacent signals extraction unit, low section time-to-digital conversion circuit, two binary synchronous counters, decoding unit, direct decoding latch cicuit and serial data output circuits; Wherein:
The initial signal EN input just phase adjustment circuit of high frequency clock CLK_H and time quantization, when described initial signal EN is high level, described just phase adjustment circuit produces EN0 signal at the next rising edge place of high frequency clock CLK_H and is sent to high section linear feedback shift register;
The described high section linear feedback shift register of finish time Stop signal input, described high section linear feedback shift register is used for quantizing the time interval of the rising edge that described EN0 signal and high frequency clock CLK_H are close to after Stop signal rising edge, obtains high section quantized value kT
clk, wherein T
clkfor the cycle of high frequency clock CLK_H, k is the count value of high section linear feedback shift register; High section quantized value is input to serial data output circuit by described high section linear feedback shift register;
Described delay matching circuit is used for carrying out delay disposal according to described Stop signal to described high frequency clock CLK_H, the rising edge delayed Stop signal t that high frequency clock CLK_H is close to after Stop signal rising edge
dFF+ANDtime, obtain the CLK_M signal after postponing, wherein t
dFF+ANDfor the inherent delay of the described EN0 signal backward high frequency clock CLK_H signal that described just phase adjustment circuit generates;
Described CLK_M signal is input to respectively stage casing bit time digital conversion circuit and low section time-to-digital conversion circuit; Described stage casing bit time digital conversion circuit is annular TDC, comprises the first voltage-controlled ring be made up of level Four delay cell and to shake unit, and the described first voltage-controlled ring unit that shakes produces rising edge and described Stop signal alignment according to outside voltage control signal and the cycle is t
m=t
clkthe periodic signal of/4, and be input to adjacent signals extraction unit; It is t in the cycle that described adjacent signals extraction unit scans described CLK_M signal rising edge
m=t
clkthe interval at place in the periodic signal of/4, thus produce latch signal LOCK;
Described two binary synchronous counters are used for carrying out measures of quantization to the time interval between described Stop signal and latch signal LOCK rising edge, obtain middle section quantized value T
counter=nt
m, wherein n is the count value of two binary synchronous counters; Middle section quantized value is inputted direct decoding latch cicuit by described binary synchronous counter;
Described low section time-to-digital conversion circuit is annular TDC, comprises the second voltage-controlled ring be made up of level Four delay cell and to shake unit, and it is t that outside voltage control signal controls shake ring cycle of shaking of unit of described second voltage-controlled ring
ldescribed CLK_M signal rising edge quantizes gate-control signal as low section, described second voltage-controlled ring shake unit form eight phase node states carry out after decoding through described decoding unit, when arriving when latch signal LOCK rising edge, the decoding value m that described direct decoding latch cicuit exports for latching now described decoding unit, obtains low section quantized value (m/8) t
l;
Described direct decoding latch cicuit comprises d type flip flop and either-or switch, for middle section quantized value and low section quantized value are latched in d type flip flop, and after being directly decoded into corresponding decimal value, controlled latches data in serial data output circuit by either-or switch;
Described serial data output circuit is used for the high section quantized value to input, middle section quantized value and low section quantized value Serial output successively, and the overall expression formula obtaining the time interval of the initial signal EN0 after first phase adjustment and finish time Stop signal is T=kT
clk-nt
m+ (m/8) t
l.
Further, shake the second voltage-controlled ring of unit and low section time-to-digital conversion circuit of the first voltage-controlled ring of described stage casing bit time digital conversion circuit shakes the unit multiplexed delay chain be made up of the delay cell of the voltage-controlled inverter of current-steering.
Further, described decoding unit is the NOR gate circuit adopting Gray code decoded mode.
Beneficial effect: syllogic time-to-digital conversion circuit of the present invention, is divided into high section, stage casing and low section of three one count, and wherein high section TDC adopts linear feedback shift register (LFSR), adopts counter to quantize to realize the time measurement of wide region; Stage casing TDC adopts ring to shake structure, and this annular oscillation circuit is made up of level Four voltage-controlled delay unit, and using end signal Stop as gate-control signal, the frequency of generation provides counting clock signal to binary synchronous counter; Low section TDC adopts the ring identical with middle section to shake structure, and using the high frequency clock signal CLK_M of delayed shaping as gate-control signal, ring shakes inner phase place node state after decoding as low section data output.
In, low section all adopts annular TDC, its closed loop delay line all adopts the delay cell of the voltage-controlled inverter of current-steering, by external setting-up, the voltage control signal with fixed voltage value controls, two voltage-controlled rings are shaken, and frequency that unit exports has higher stability.Simultaneously, shake the second voltage-controlled ring of unit and low section time-to-digital conversion circuit of first voltage-controlled ring of stage casing bit time digital conversion circuit shakes the unit multiplexed delay chain be made up of the delay cell of the voltage-controlled inverter of current-steering, two TDC adopt different gate-control signals to control, in realization, while low section of quantization function, reduce area and the power consumption of circuit.
Due to the rising edge t that the backward high frequency clock CLK_H of EN0 signal in first phase adjustment circuit is close to after Stop signal rising edge
dFF+ANDtime, this t
dFF+ANDtime is the d type flip flop in first phase adjustment circuit and the inherent delay sum with door.Delay matching circuit is adopted before middle section TDC, this delay matching circuit is by d type flip flop, form with door and inverter, according to Stop signal, delay disposal is carried out to high frequency clock CLK_H, the rising edge delayed Stop signal t that high frequency clock CLK_H is close to after Stop signal rising edge
dFF+ANDtime, obtain the CLK_M signal after postponing, thus make the overall measurement time interval constant, achieve the delay matching of high section and middle section.
The decoding unit connecting low section TDC is the NOR gate circuit adopting Gray code decoded mode, adopts Gray code decoded mode, greatly reduces logic and obscure, reduce the output frequency of lowest weightings position, the error rate is reduced greatly.Adopt identical decoding circuit structure to carry out decoding to shake eight phase node states of unit of voltage-controlled ring in low section TDC, achieve delay matching and symmetrical configuration.
Syllogic time-to-digital conversion circuit can be operated in counting and transfer of data two kinds of patterns, and these two kinds of patterns use high-frequency count clock and low-frequency transmission clock control respectively, and enumeration data is with binary data form successively Serial output.
Relative to traditional two-part time-to-digit converter, the syllogic time-to-digital conversion circuit in the present invention can take into account the performance requirement of certainty of measurement and dynamic range well, realizes time measurement more accurately.The time interval of adjacent segment adopts different method of measurement to carry out areal survey by intersegmental adjacent signals extractive technique, thus can multiplexing delay chain in each section of TDC, and acreage reduction simplifies circuit structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of syllogic time-to-digital conversion circuit;
Fig. 2 is low section of TDC time measurement principle sequential chart in syllogic time-to-digital conversion circuit;
Fig. 3 is low section of TDC circuit structure diagram in syllogic time-to-digital conversion circuit;
Fig. 4 is that the high section of syllogic time-to-digital conversion circuit counts/transmit double mode LFSR structure;
Fig. 5 is that in syllogic time-to-digital conversion circuit, low section of TDC5 bit data latches and transmission structure figure;
Fig. 6 is the voltage-controlled delay cellular construction figure of low section of TDC in syllogic time-to-digital conversion circuit;
Fig. 7 is the sequential chart of syllogic time-to-digital conversion circuit.
Embodiment
By reference to the accompanying drawings the present invention is further described.
As shown in Figure 1, a kind of syllogic time-to-digital conversion circuit, comprises high section linear feedback shift register, first phase adjustment circuit, delay matching circuit, stage casing bit time digital conversion circuit, adjacent signals extraction unit, low section time-to-digital conversion circuit, two binary synchronous counters, decoding unit, direct decoding latch cicuit and serial data output circuits.
Wherein, the initial signal EN input just phase adjustment circuit of high frequency clock CLK_H and time quantization, when initial signal EN is high level, first phase adjustment circuit produces EN0 signal at the next rising edge place of high frequency clock CLK_H and is sent to high section linear feedback shift register.
Finish time Stop signal inputs high section linear feedback shift register, the time interval of high section linear feedback shift register to the rising edge that EN0 signal and high frequency clock CLK_H are close to after Stop signal rising edge quantizes, and obtains high section quantized value kT
clk, wherein T
clkfor the cycle of high frequency clock CLK_H, k is the count value of high section linear feedback shift register.High section quantized value is input to serial data output circuit by high section linear feedback shift register.
Because EN0 signal falls behind high frequency clock CLK_H signal fixed delay t
dFF+AND, cause that EN0 signal is relative with the time interval of Stop signal to be reduced.Delay matching circuit carries out delay disposal according to Stop signal to high frequency clock CLK_H, the rising edge delayed Stop signal t that high frequency clock CLK_H is close to after Stop signal rising edge
dFF+ANDtime, obtain the CLK_M signal after postponing, wherein t
dFF+ANDfor the inherent delay of the backward CLK_H signal of described EN0 signal that first phase adjustment circuit generates.Be illustrated in figure 2 low section of TDC time measurement principle sequential chart in syllogic TDC, CLK_M be through delay matching, be positioned at high frequency clock signal after finish time Stop signal rising edge.Without any in delay situation, CLK_M should with the rising edge alignment of Stop signal, postpone t owing to existing
dFF+AND, CLK_M signal rising edge arrive time postpone backward, CLK_M should and Stop signal between maximum delay be no more than a high frequency clock cycles T
clk.Adding delay matching circuit makes CLK_M signal fall behind Stop signal t equally
dFF+ANDfixed delay, thus realize delay matching, the overall measurement time interval remained unchanged.
CLK_M signal is input to respectively stage casing bit time digital conversion circuit and low section time-to-digital conversion circuit, stage casing bit time digital conversion circuit is annular TDC, comprises the first voltage-controlled ring be made up of level Four delay cell and to shake unit.The first voltage-controlled ring unit that shakes produces rising edge and Stop signal alignment according to outside voltage control signal and the cycle is t
m=t
clkperiodic signal S0 ~ the S3 of/4, and be input to adjacent signals extraction unit.Adjacent signals extraction unit scanning CLK_M signal rising edge is t in the cycle
m=t
clkthe interval at place in the periodic signal of/4, thus produce latch signal LOCK.Because the sweep signal cycle is t
m=t
clk/ 4, and the time interval of Stop signal and CLK_M signal rising edge is less than T
clk, then CLK_M signal rising edge is necessarily within the scope of S0 ~ S3 signal spacing.If CLK_M signal rising edge is within the scope of S0 ~ S3 signal spacing between two adjacent signals rising edges, then by the rising edge triggered latch signal LOCK of a rear signal.Stop signal rising edge is middle section TDC quantized value T to the time interval of latch signal LOCK rising edge
counter, and T
counter4t must be no more than
m, therefore, the value of the count signal Count that section produces must be not more than 4, then can complete counting with two binary synchronous counters.By this coincidence counter, measures of quantization is carried out to the time interval between Stop signal and latch signal LOCK rising edge, obtain middle section quantized value T
counter=nt
m, wherein n is the count value of two binary synchronous counters.Then, middle section quantized value is inputted direct decoding latch cicuit by binary synchronous counter.
CLK_M rising edge is low section ring to time interval of LOCK rising edge and shakes TDC Measuring Time surplus t
r.Low section time-to-digital conversion circuit is annular TDC, comprises the second voltage-controlled ring be made up of level Four delay cell and to shake unit, and it is t that outside voltage control signal controls shake ring cycle of shaking of unit of the second voltage-controlled ring
lcLK_M signal rising edge quantizes triggering signal as low section, second voltage-controlled ring shake unit form eight phase node states carry out after decoding through decoding unit, when arriving when latch signal LOCK rising edge, the decimal system decoding value m of direct decoding latch circuit latches now decoding unit output, obtains low section quantized value t
r=(m/8) t
l.The expression formula of low section of time measurement is then:
T
M＝T
Counter-t
R＝n·t
M-t
R＝n·t
M-(m/8)·t
L(1)
Direct decoding latch cicuit comprises d type flip flop and either-or switch, for middle section quantized value and low section quantized value are latched in d type flip flop, and after being directly decoded into corresponding decimal value, controlled latches data in serial data output circuit by either-or switch.
Serial data output circuit is used for the high section quantized value to input, middle section quantized value and low section quantized value Serial output successively, and the overall expression formula obtaining the time interval of the initial signal EN0 after first phase adjustment and finish time Stop signal is:
T＝k·T
clkT
M＝k·T
clkn·t
M+(m/8·)t
L(2)
In above-mentioned syllogic time-to-digital conversion circuit, shake the second voltage-controlled ring of single and low section time-to-digital conversion circuit of the first voltage-controlled ring of stage casing bit time digital conversion circuit shakes single multiplexing delay chain be made up of the delay cell of the voltage-controlled inverter of current-steering.
Low section of TDC circuit structure diagram in being illustrated in figure 3, the left side be delay matching circuit by d type flip flop, the logical circuit that forms with door and inverter.With Stop be in gate-control signal section annular oscillation circuit produce the cycle be t
m=t
clkthe periodic signal of/4, S0, S1, S2, S3 signal namely in Fig. 2, for scanning the interval at CLK_M signal rising edge place.If CLK_M rising edge is between two adjacent signals rising edges, then produce latch signal LOCK by the rising edge triggered D flip flop of a rear signal, the ring simultaneously recorded between Stop signal and LOCK signal shakes the number of periodic signal, triggers Count count signal.Eight the phase node state informations taking CLK_M as the low section annular oscillation circuit generation of gate-control signal, through LOCK signal sampling, produce low section three bit data Q0, Q1, Q2 through the decoding circuit be made up of XOR gate.The delay match of the either-or switch in this annular oscillation circuit and the delay of inverter and three delay cells, avoids because path exists the edge error code problem that delay mismatches causes.Decoding circuit adopts Gray code decoded mode, these eight phase node states are decoded into three bit data to export, make the frequency of low section TDC lowest weightings bit data have larger decline, avoid the d type flip flop error code that straight binary decoding circuit causes because lowest order frequency is too high.The shake Gray code decoding table of TDC phase state of low section ring is as shown in table 1, and the expression formula of the decoding carry-out bit of Q0, Q1, Q2 is respectively:
Table 1
High section TDC adopts and counts/transmit double mode 7bit LFSR structure, and circuit as shown in Figure 4.EN0 is the control signal after first phase adjustment, works as EN, and when EN0 is all high level, either-or switch gating 1 port, is controlled count and latch by CLK_H clock signal.Work as EN, when EN0 is all low level, enter by the Serial output stage of low-frequency transmission clock CLK_L signal controlling, the 7 bit data Q5-Q11 of high section TDC are successively from Q11 port Serial output.In low section of TDC low 5 bit data by either-or switch from the circuit left side flow to the right, follow closely high section data serial export.In the present embodiment, the CLK_H clock signal being input to 7bit LFSR structure first carries out preliminary treatment, and by high-frequency signal H_CK and signal SH by being input to the input of the clock signal of 7bit LFSR structure with door, its high frequency signal H_CK is cycle T
clkclock signal, signal SH is the inversion signal generated by CLK_M signal as shown in Figure 3, and this structure plays a part to turn off CLK_H signal.Because needs measure Stop signal rising edge and the next CLK_H rising time interval of next-door neighbour, so must turn off high-frequency count clock after getting the time interval, avoid high section TDC miscount, its sequential chart as shown in Figure 7.
The low 5 bit data latch cicuits of low section of TDC in being illustrated in figure 5, this circuit is made up of two binary synchronous counters, five either-or switch and low section latches data d type flip flop.Section counting and transmission during the first two either-or switch is controlled respectively by selected middle section Count count signal and low-frequency transmission signal CLK_L, rear three either-or switch and d type flip flop latch and transmit low section data.When EN is high level, either-or switch gating 1 port, allows latch signal LOCK directly to latch low section three bit data, and simultaneously, section count signal Count triggers two binary synchronous counters and starts counting, produces stage casing bit data Q3, Q4.When EN is low level, latch and counting all stop, and open mode of serial transmission.In final, 5 bit data of low section are from rightmost successively Serial output paramount section TDC transmission circuit, form 12 Bits Serial and export binary code.
In, low section TDC adopts voltage-controlled inverting delay cells, as shown in Figure 6, a pair voltage-controlled current source is connected between inverter by it, by the control of complementary voltage, can effectively control by the propagation delay being input to output.Along with control voltage OE increases, controlled metal-oxide-semiconductor conducting resistance reduces, and the discharging current of inverter increases, and time of delay reduces.Meanwhile, when delay cell is input as high level, Nixie tube forms negative feedback in the source of control valve, reduces the susceptibility of electric current to control voltage, enhances the stability in delay cell transmission time.
Syllogic time-to-digital conversion circuit of the present invention, achieves the time measurement of high measurement accuracy and wide region, and it occupies less area, consumes lower power consumption, can be applicable to the time measurement system of high-speed, high precision.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (3)
1. a syllogic time-to-digital conversion circuit, is characterized in that: comprise high section linear feedback shift register, first phase adjustment circuit, delay matching circuit, stage casing bit time digital conversion circuit, adjacent signals extraction unit, low section time-to-digital conversion circuit, two binary synchronous counters, decoding unit, direct decoding latch cicuit and serial data output circuits; Wherein:
The initial signal EN input just phase adjustment circuit of high frequency clock CLK_H and time quantization, when described initial signal EN is high level, described just phase adjustment circuit produces EN0 signal at the next rising edge place of high frequency clock CLK_H and is sent to high section linear feedback shift register;
The described high section linear feedback shift register of finish time Stop signal input, described high section linear feedback shift register is used for quantizing the time interval of the rising edge that described EN0 signal and high frequency clock CLK_H are close to after Stop signal rising edge, obtains high section quantized value kT
clk, wherein T
clkfor the cycle of high frequency clock CLK_H, k is the count value of high section linear feedback shift register; High section quantized value is input to serial data output circuit by described high section linear feedback shift register;
Described delay matching circuit is used for carrying out delay disposal according to described Stop signal to described high frequency clock CLK_H, the rising edge delayed Stop signal t that high frequency clock CLK_H is close to after Stop signal rising edge
dFF+ANDtime, obtain the CLK_M signal after postponing, wherein t
dFF+ANDfor the inherent delay of the described EN0 signal backward high frequency clock CLK_H signal that described just phase adjustment circuit generates;
Described CLK_M signal is input to respectively stage casing bit time digital conversion circuit and low section time-to-digital conversion circuit; Described stage casing bit time digital conversion circuit is annular TDC, comprises the first voltage-controlled ring be made up of level Four delay cell and to shake unit, and the described first voltage-controlled ring unit that shakes produces rising edge and described Stop signal alignment according to outside voltage control signal and the cycle is t
m=t
clkthe periodic signal of/4, and be input to adjacent signals extraction unit; It is t in the cycle that described adjacent signals extraction unit scans described CLK_M signal rising edge
m=t
clkthe interval at place in the periodic signal of/4, thus produce latch signal LOCK;
Described two binary synchronous counters are used for carrying out measures of quantization to the time interval between described Stop signal and latch signal LOCK rising edge, obtain middle section quantized value T
counter=nt
m, wherein n is the count value of two binary synchronous counters; Middle section quantized value is inputted direct decoding latch cicuit by described binary synchronous counter;
Described low section time-to-digital conversion circuit is annular TDC, comprises the second voltage-controlled ring be made up of level Four delay cell and to shake unit, and it is t that outside voltage control signal controls shake ring cycle of shaking of unit of described second voltage-controlled ring
ldescribed CLK_M signal rising edge quantizes gate-control signal as low section, described second voltage-controlled ring shake unit form eight phase node states carry out after decoding through described decoding unit, when arriving when latch signal LOCK rising edge, the decoding value m that described direct decoding latch cicuit exports for latching now described decoding unit, obtains low section quantized value (m/8) tL;
Described direct decoding latch cicuit comprises d type flip flop and either-or switch, for middle section quantized value and low section quantized value are latched in d type flip flop, and after being directly decoded into corresponding decimal value, controlled latches data in serial data output circuit by either-or switch;
Described serial data output circuit is used for the high section quantized value to input, middle section quantized value and low section quantized value Serial output successively, and the overall expression formula obtaining the time interval of the initial signal EN0 after first phase adjustment and finish time Stop signal is T=kT
clk-nt
m+ (m/8) t
l.
2. a kind of syllogic time-to-digital conversion circuit according to claim 1, is characterized in that: shake the second voltage-controlled ring of unit and low section time-to-digital conversion circuit of the first voltage-controlled ring of described stage casing bit time digital conversion circuit shakes the unit multiplexed delay chain be made up of the delay cell of the voltage-controlled inverter of current-steering.
3. a kind of syllogic time-to-digital conversion circuit according to claim 1, is characterized in that: described decoding unit is the NOR gate circuit adopting Gray code decoded mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410536431.XA CN104333365B (en) | 2014-10-11 | 2014-10-11 | A kind of three-stage time-to-digital conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410536431.XA CN104333365B (en) | 2014-10-11 | 2014-10-11 | A kind of three-stage time-to-digital conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104333365A true CN104333365A (en) | 2015-02-04 |
| CN104333365B CN104333365B (en) | 2017-06-09 |
Family
ID=52408031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410536431.XA Active CN104333365B (en) | 2014-10-11 | 2014-10-11 | A kind of three-stage time-to-digital conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104333365B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105353600A (en) * | 2015-10-14 | 2016-02-24 | 东南大学 | High-accuracy low-power three-segment type TDC circuit used for array system |
| CN105871371A (en) * | 2016-03-25 | 2016-08-17 | 东南大学 | Three-segment time-to-digital conversion circuit based on phase-locked loop |
| CN108761431A (en) * | 2018-04-20 | 2018-11-06 | 广州民航职业技术学院 | A kind of digital delay system and its implementation for sonar system test |
| CN109814367A (en) * | 2018-12-29 | 2019-05-28 | 西安电子科技大学 | A kind of time-to-digit converter with gate ena-bung function |
| CN113206668A (en) * | 2021-05-11 | 2021-08-03 | 中国科学技术大学 | Two-stage interpolation time digital converter circuit |
| CN113271097A (en) * | 2015-11-09 | 2021-08-17 | 爱思开海力士有限公司 | Latch circuit, double data rate ring counter and related device |
| CN113376999A (en) * | 2021-06-08 | 2021-09-10 | 西安电子科技大学 | Special adder for high time resolution time-to-digital converter |
| CN114050827A (en) * | 2021-11-17 | 2022-02-15 | 东南大学 | Digital calibration method applied to capacitance three-section successive approximation type analog-to-digital converter |
| CN114114211A (en) * | 2021-12-03 | 2022-03-01 | 武汉市聚芯微电子有限责任公司 | TDC unit, TDC array and ranging system |
| CN114815570A (en) * | 2022-05-05 | 2022-07-29 | 陕西科技大学 | Time-to-digital converter based on differential delay loop |
| CN114935886A (en) * | 2022-04-21 | 2022-08-23 | 中国科学院上海微系统与信息技术研究所 | Two-section type superconducting time-to-digital converter and superconducting detector imaging system |
| CN114995092A (en) * | 2022-06-15 | 2022-09-02 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
| CN116153362A (en) * | 2023-04-20 | 2023-05-23 | 浙江力积存储科技有限公司 | Delay feedback method and delay feedback storage structure for read latency counter |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080315928A1 (en) * | 2007-06-22 | 2008-12-25 | Khurram Waheed | Digital phase locked loop with dithering |
| CN101373973A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科微电子（上海）有限公司 | Time-to-digital conversion circuit and method |
| CN102651685A (en) * | 2011-02-24 | 2012-08-29 | 爱立信(中国)通信有限公司 | Signal delay device and method |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| US20140077841A1 (en) * | 2012-09-14 | 2014-03-20 | Wenyan Jia | Phase frequency detector |
-
2014
- 2014-10-11 CN CN201410536431.XA patent/CN104333365B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080315928A1 (en) * | 2007-06-22 | 2008-12-25 | Khurram Waheed | Digital phase locked loop with dithering |
| CN101373973A (en) * | 2007-08-24 | 2009-02-25 | 锐迪科微电子（上海）有限公司 | Time-to-digital conversion circuit and method |
| CN102651685A (en) * | 2011-02-24 | 2012-08-29 | 爱立信(中国)通信有限公司 | Signal delay device and method |
| US20140077841A1 (en) * | 2012-09-14 | 2014-03-20 | Wenyan Jia | Phase frequency detector |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
Non-Patent Citations (1)
| Title |
|---|
| 李根: "基于延迟锁定环的TDC的设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105353600A (en) * | 2015-10-14 | 2016-02-24 | 东南大学 | High-accuracy low-power three-segment type TDC circuit used for array system |
| CN113271097A (en) * | 2015-11-09 | 2021-08-17 | 爱思开海力士有限公司 | Latch circuit, double data rate ring counter and related device |
| CN113271097B (en) * | 2015-11-09 | 2024-06-07 | 爱思开海力士有限公司 | Latch circuit, double data rate ring counter and related devices |
| CN105871371A (en) * | 2016-03-25 | 2016-08-17 | 东南大学 | Three-segment time-to-digital conversion circuit based on phase-locked loop |
| CN105871371B (en) * | 2016-03-25 | 2018-08-10 | 东南大学 | A kind of three-stage time-to-digital conversion circuit based on phaselocked loop |
| CN108761431A (en) * | 2018-04-20 | 2018-11-06 | 广州民航职业技术学院 | A kind of digital delay system and its implementation for sonar system test |
| CN109814367A (en) * | 2018-12-29 | 2019-05-28 | 西安电子科技大学 | A kind of time-to-digit converter with gate ena-bung function |
| CN113206668B (en) * | 2021-05-11 | 2022-10-28 | 中国科学技术大学 | Two-stage interpolation time digital converter circuit |
| CN113206668A (en) * | 2021-05-11 | 2021-08-03 | 中国科学技术大学 | Two-stage interpolation time digital converter circuit |
| CN113376999B (en) * | 2021-06-08 | 2023-01-06 | 西安电子科技大学 | Special adder for high time resolution time-to-digital converter |
| CN113376999A (en) * | 2021-06-08 | 2021-09-10 | 西安电子科技大学 | Special adder for high time resolution time-to-digital converter |
| CN114050827A (en) * | 2021-11-17 | 2022-02-15 | 东南大学 | Digital calibration method applied to capacitance three-section successive approximation type analog-to-digital converter |
| CN114050827B (en) * | 2021-11-17 | 2024-03-19 | 东南大学 | Digital calibration method applied to capacitor three-section successive approximation analog-to-digital converter |
| CN114114211B (en) * | 2021-12-03 | 2022-09-06 | 武汉市聚芯微电子有限责任公司 | TDC unit, TDC array and ranging system |
| CN114114211A (en) * | 2021-12-03 | 2022-03-01 | 武汉市聚芯微电子有限责任公司 | TDC unit, TDC array and ranging system |
| CN114935886A (en) * | 2022-04-21 | 2022-08-23 | 中国科学院上海微系统与信息技术研究所 | Two-section type superconducting time-to-digital converter and superconducting detector imaging system |
| CN114815570A (en) * | 2022-05-05 | 2022-07-29 | 陕西科技大学 | Time-to-digital converter based on differential delay loop |
| CN114815570B (en) * | 2022-05-05 | 2024-02-13 | 陕西科技大学 | Time-to-digital converter based on differential delay loop |
| CN114995092A (en) * | 2022-06-15 | 2022-09-02 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
| CN114995092B (en) * | 2022-06-15 | 2024-02-23 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
| CN116153362A (en) * | 2023-04-20 | 2023-05-23 | 浙江力积存储科技有限公司 | Delay feedback method and delay feedback storage structure for read latency counter |
| CN116153362B (en) * | 2023-04-20 | 2023-08-25 | 浙江力积存储科技有限公司 | Delay feedback method and delay feedback storage structure for read latency counter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104333365B (en) | 2017-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104333365A (en) | Three-segment time digital converter (TDC) circuit | |
| CN109143832B (en) | High-precision multichannel time-to-digital converter | |
| CN103208994A (en) | Two-stage time digital convert (TDC) circuit | |
| US8736327B2 (en) | Time-to-digital converter | |
| US8325076B2 (en) | Time-to-digital converter | |
| CN106527098B (en) | Low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO | |
| CN105353600B (en) | A kind of high-precision low-power consumption three-stage TDC circuits for being applied to array system | |
| CN102916687B (en) | Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology | |
| CN107643674A (en) | A kind of Vernier type TDC circuits based on FPGA carry chains | |
| CN104320130A (en) | Dual-loop DLL-based three-segment type high-precision time-to-digital conversion method and circuit | |
| CN105718404A (en) | Square-wave generator and generating method based on FPGA | |
| US20100085220A1 (en) | Low-power asynchronous counter and method | |
| CN202166844U (en) | High precision time measurement circuit | |
| US6396312B1 (en) | Gate transition counter | |
| CN112838851A (en) | Residual time sampling circuit based on differential sampling and time-to-digital converter | |
| CN109274376B (en) | Vernier ring-shaped time-to-digital converter capable of compressing maximum conversion time | |
| US9306576B2 (en) | Modular gray code counter | |
| Kwiatkowski et al. | A brief review of wave union TDCs | |
| Yao | Time to Digital Converter used in ALL digital PLL | |
| CN114967411B (en) | Multi-stage time-to-digital converter with automatic reset mechanism | |
| CN106354001A (en) | Time-to-digital conversion circuit | |
| CN214480526U (en) | Residual time sampling circuit based on differential sampling and time-to-digital converter | |
| CN113206668B (en) | Two-stage interpolation time digital converter circuit | |
| Deng et al. | A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA | |
| CN109104168B (en) | Circuit for measuring fine time |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |