CN113376999B - Special adder for high time resolution time-to-digital converter - Google Patents
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Abstract
The invention provides a design method and a circuit implementation of a special adder for a time-to-digital converter (TDC) with large dynamic measurement range and high resolution performance, which mainly comprise a Gray code and binary code conversion module (1), a self-calibration module (2) and an internal logic module (3). The special adder provided by the invention is mainly used for realizing addition and combination of the count values of the integer part and the fraction part in the time-to-digital converter, not only can sum the cycle integer part numerical values and the fraction part numerical values of different systems generated by the ring oscillator circuit in the TDC and convert the cycle integer part numerical values and the fraction part numerical values into standard binary codes, but also has certain error correction capability in time sequence, and can ensure the correctness of the TDC in the whole time measurement to numerical value conversion.
Description
Technical Field
The invention provides a circuit of a special adder for a high-time-resolution time-to-digital converter (TDC), and relates to the technical field of digital integrated circuits.
Background
A time-to-digital converter, which is a device for converting analog quantity to digital quantity in a time domain, has characteristics very similar to an analog-to-digital converter (ADC). The TDC is a device mainly used to perform time measurement, has high measurement resolution, and is widely used in various application fields requiring conversion of an amount of time into a numerical amount. The application of TDC in the above-mentioned field has a high requirement on its time measurement resolution, which has prompted the students in this research field to continuously pursue a TDC circuit architecture for realizing a higher time measurement resolution, so that the circuit structure of the TDC is also changed from the original simple delay chain type to the recently proposed two-stage conversion type (such as coarse-fine type TDC), and the time measurement resolution of the TDC can break through 1ps at present and is developing towards a smaller measurement resolution.
Although the time measurement resolution of the TDC is greatly improved in recent years, and the performance of the related system equipment applied to the characteristic of the TDC is also greatly improved, the same benefits are not brought to the system equipment which pays more attention to the dynamic measurement range of the TDC relative to the measurement resolution. This is because as the resolution of TDC measurements increases, their corresponding dynamic measurement range does not increase as well, often at the expense of dynamic measurement range. For example, for the current TDC with the measurement resolution of about 1ps, the dynamic measurement range is often only ten nanoseconds or even several nanoseconds, which is far from sufficient for the TDC applied to the laser radar ranging.
In order to realize a TDC with a large measurement dynamic range and a high time measurement resolution applicable to laser radar ranging, it is now common that a cycle integral multiple count value and a fraction integral multiple count value generated by a Ring Oscillator (RO) in the TDC are summed and converted into a standard binary value. However, because the counting results of the integer part and the fractional part are different in the adopted system, the two counting results cannot be directly added; due to the existence of the time delay of the device, the jump is added to the integer part and the zero clearing of the fraction part is not completely synchronous, so that the measured value has serious deviation, and the accuracy of time measurement is influenced.
Disclosure of Invention
In order to solve the above problems, the present invention provides a circuit scheme of a special adder which is applied to a TDC with a large measurement dynamic range and a high time measurement resolution, can perform addition between different system input values, and has an error correction function at the same time. The input of the special adder for the high-time-resolution time-to-digital converter comprises a 16-bit gray code counting RESULT A of a coarse counter in the time-to-digital converter, a 6-bit binary code counting RESULT C of a fine counter decoder in the time-to-digital converter and a binary frequency division signal of a counting clock, and the output is a 24-bit binary value RESULT representing the measurement duration; characterized in that the special adder comprises: the device comprises a Gray code and binary code conversion module 1, a self-calibration module 2 and an internal logic module 3;
the gray code and binary code conversion module 1 is used for converting a 16-bit gray code counting result A of a coarse counter in the time-to-digital converter into a corresponding binary system for subsequent operation;
the self-calibration module 2 self-calibrates the conversion result B of the binary code corresponding to the gray code conversion of 16 bits by the binary code C of the decoder and the binary frequency division signal of the counting clock according to the counting result A of the gray code of 16 bits of the coarse counter, so as to ensure that a correct result can be still given when a non-ideal condition caused by circuit time delay occurs, and improve the accuracy and reliability of data;
the internal logic module 3 is used for processing the 16-bit calibrated binary code result E, converting the result according to specific logic, and then adding the result and the 6-bit binary code C of the decoder to solve the problem that the least significant bit corresponds to the decimal number 63 and cannot be expressed by binary.
The self-calibration module 2 comprises a self-adding one module, an alternative selector module and a selector logic judgment module; wherein: the input of the self-adding module is a conversion result B of converting the gray code and the 16-bit gray code output by the binary code conversion module into the corresponding binary code, and the output is a 16-bit self-adding result D after the gray code and the binary code are added by one; the input of the alternative selector module is a conversion result B of converting gray codes and 16-bit gray codes output by the binary code conversion module into corresponding binary codes, a 16-bit self-adding result D output by the self-adding one module and a selector control signal SEL output by the selector logic judgment module; controlling the one-out-of-two selector module to output a 16-bit calibrated binary code result E through a selector control signal; the selector logic judgment module performs combinational logic operation according to the highest bit of the 6-bit binary code counting result C of the input decoder, the lowest bit of the 16-bit gray code counting result A of the coarse counter and the binary frequency division signal of the counting clock according to a specific relation, and outputs a selector control signal SEL.
The internal logic module (3) comprises a normal binary code conversion and a normal adder which are carried out according to a specific rule; the decoder comprises a 6-bit binary code counting result C of the decoder and a 16-bit calibrated binary code result (E) output by a self-calibration module; and performing standard binary code conversion according to a specific rule, shifting the 16-bit binary code RESULT output by the self-calibration module by 6 bits integrally to the left, subtracting the value of the RESULT to obtain a binary code RESULT F in the true sense, and directly adding the binary code RESULT F and the 6-bit binary code to obtain a binary code value RESULT of which the 24 bits represent the measurement duration.
Compared with the prior art, the invention has the following advantages:
1. the coarse and fine counting results are not required to be output to external equipment for storage and operation, and can be output to a register in a TDC circuit for storage after passing through the special adder, so that the external equipment can directly obtain the results;
2. the coarse counting result and the fine counting result do not need to be output respectively, so that the problem that direct combination and addition cannot be realized due to different systems of the coarse counting result and the fine counting result is solved;
3. the self-calibration function ensures that a correct result can be given when non-ideal conditions caused by circuit time delay occur, and the accuracy and the reliability of data are improved.
Drawings
FIG. 1 is a block diagram of an implementation of a special adder according to the present invention;
FIG. 2 is a functional block diagram of the modules of the special adder of the present invention;
FIG. 3 is a block diagram of a core structure of a special adder applied to TDC according to the present invention.
Detailed Description
In order to make the technical features, circuit configurations, functions, and usage scenarios of the present invention intuitive and understandable, the present invention will be further described below with reference to the drawings, and in the following description, the terms "VDD", "GND" and "connection" should be understood in a broad sense unless otherwise specified.
Referring to fig. 1 and 2, the special adder of the present invention includes 3 inputs, which are respectively the counting result a of 16-bit gray code of the coarse counter in the time-to-digital converter, the counting result C of 6-bit binary code of the fine counter decoder in the time-to-digital converter, and the halved frequency signal of the counting clock; the output is a binary value RESULT representing the duration of the measurement in 24 bits. The special adder according to the function comprises a Gray code and binary code conversion module 1, a self-calibration module 2 and an internal logic module 3;
the gray code and binary code conversion module 1 has an input of a counting result A of 16-bit gray codes of the coarse counter and an output of a conversion result B of converting the 16-bit gray codes into corresponding binary codes. Because the Gray code only has one bit per jump, the application of the Gray code in circuit design has the characteristics of reducing power consumption and improving data transmission accuracy, and in order to ensure that the time required by adding one bit in the coarse counter every time is approximately equal, the coarse counting value of the TDC adopts Gray code for counting. The fine count value representing the fractional part normally uses binary system, so the gray code count result of the coarse counter is firstly converted into corresponding binary system for subsequent operation.
The self-calibration module is provided with 4 inputs, namely a counting result A of 16-bit gray codes of the coarse counter, a conversion result B of the 16-bit gray codes into corresponding binary codes, a counting result C of 6-bit binary codes of a fine counter decoder in the time-to-digital converter and a halved frequency signal of a counting clock; the output is a 16-bit calibrated binary code result E. Ideally, when the ring oscillator completes just one oscillation cycle, the count value of the coarse counter is incremented while the input of the sample latch returns to the initial state, and the output of the decoder "00_0000" will always be earlier or later than the incrementing process of the coarse counter due to the device delay, so that the measured value is severely biased. The design of the self-calibration block ensures that it gives correct results in the event of non-idealities due to circuit delays. The method is characterized in that: the system comprises a self-adding module, an alternative selector module and a selector logic judgment module, wherein:
the self-adding module inputs the 16-bit gray code output by the gray code and binary code conversion module into a conversion result B of the corresponding binary code, and outputs a 16-bit self-adding result D after the gray code and the binary code are added by one;
the input of the two-choice selector module is gray code and a conversion result B of converting the 16-bit gray code output by the binary code conversion module into the corresponding binary code, the 16-bit self-adding result D output by the self-adding one module, a selector control signal SEL output by the selector logic judgment module and the two-choice selector module are controlled by the selector control signal to output a 16-bit calibrated binary code result E;
the selector logic judgment module performs combinational logic operation according to the highest bit of the input 6-bit binary code counting result C of the decoder, the lowest bit of the 16-bit gray code counting result A of the coarse counter and the binary frequency division signal of the counting clock according to a specific relation, and outputs a selector control signal SEL.
The internal logic block has 2 inputs, 16-bit calibrated binary result E and 6-bit binary C from the decoder. The least significant bit in a 16-bit gray code corresponds to the decimal number 63, which cannot be expressed by 2n, n > =1. Therefore, the 6-bit binary code cannot be directly added or shift-added, and therefore, it is necessary to perform addition after conversion according to a specific logic. The method is characterized in that: and carrying out standard binary code conversion according to a specific rule, shifting the 16-bit binary code RESULT output by the self-calibration module by 6 bits integrally, subtracting the value of the RESULT to obtain a binary code RESULT F in the true sense, and directly adding the binary code RESULT F with the 6-bit binary code to obtain a binary code value RESULT of which the 24 bits represent the measuring time length.
Fig. 3 is a block diagram of a core structure of a special adder according to the present invention applied to a TDC circuit with a large dynamic range for measurement and a high resolution of measurement time, which includes a ring oscillator RO formed by delay cells represented by 63 inverters, 63 sampling latches and a fine counter, a coarse counter and the special adder according to the present invention corresponding thereto. When the rising edge of the Start measurement signal "Start" comes, the RO starts running while the coarse counter is enabled. The coarse counter starts incrementing by one each time a rising edge arrives at the clock input of the coarse counter. It is worth noting that to ensure that the time required for the coarse counter to increment by one at a time is approximately equal, the form of gray code counting is used here. When the rising edge of the Stop signal Stop comes, the Stop signal Stop latches the count value in the coarse counter and then sends the count value to the adder; on the other hand, the RO will be in this caseThe voltage value of each inverter output terminal is sampled and a 6-bit binary code is obtained through a fine counter. The least significant bit of the 6-bit binary code determines the measurement time resolution of the TDC, which is equal to the propagation delay of two inverters, i.e. LSB =2 τ In which τ is>0 is the propagation delay of a single inverter. It can be seen that the count value in the coarse counter represents the integer number of cycles the ring oscillator oscillates, while the 6-bit binary number output by the sample latch and the fine counter represents a fractional count value less than one oscillation cycle. The count value that collectively represents the time difference between the rising edges of the "Start" and "Stop" signals should be the count value in the coarse counter plus the output of the fine counter.
The invention discloses a special adder for a high-time-resolution time-to-digital converter, which has the following internal logic operation flow:
(1) The gray code and binary code conversion module converts the 16-bit gray code counting result A of the TDC coarse counter into a corresponding binary system B, and inputs the binary system B into the self-calibration module. The conversion rule of Gray code to binary code is to reserve the most significant bit of Gray code as the most significant bit of binary code, and the second most significant binary code is the exclusive OR value of the first most significant binary code and the second most significant Gray code. By analogy, all binary codes to be output currently are exclusive or outputs of the binary codes with one higher bit and the gray codes with the current bit.
The conversion rule from gray code to binary code can be summarized as the following expression:
wherein n is more than or equal to 1, i is more than or equal to 1 and less than or equal to n, G n-1 G n-2 ...G 1 G 0 Representing Gray code to be converted, B n-1 B n-2 ...B 1 B 0 Representing the converted binary code.
(2) The self-calibration module inputs a conversion result B of a binary code after 16-bit conversion and a 16-bit self-adding result D after self-adding into the one-out-of-two selector, the selector logic judgment module performs combinational logic operation according to the highest bit of a 6-bit binary code counting result C of an input decoder, the lowest bit of a 16-bit gray code counting result A of a coarse counter and a binary frequency division signal of a counting clock according to a specific relation, a selector control signal SEL is generated, and the result output of the one-out-of-two selector is controlled. And correctly judging whether the binary code which is not added with one after conversion or the binary code which is added with one after conversion is sent to the next-stage module circuit for processing. A selector control signal SEL is the output of the judging logic circuit and is also the selection control signal of an alternative selector, and when SEL =0, binary codes obtained by direct conversion of Gray codes are selected and output; when SEL =1, a binary code output from "1" added is selected. SEL may be represented by a logical expression as follows:
wherein, fake _ bind [0]Is the lowest bit of the pseudo binary code into which the 16-bit gray code is directly converted; div _2 is a halved frequency signal of the counting clock, and jumps when the falling edge of the counting clock arrives; decoder [5]]Is the most significant signal of the count result of the 6-bit fine counter. As known from the output signal characteristic (Gray code) of the coarse counter, the false _ binary [0] is obtained before and after the coarse count is increased by "1", i.e. before and after each ring oscillator rotates for 2 weeks]
div _2 is always 1, and the selection control signal SEL is mainly determined by the most significant decoder [5] of the count result of the fine counter]。
(3) The internal logic module shifts the 16-bit binary code RESULT E output by the 16-bit self-calibration module to the left by 6 bits integrally, subtracts the value of the 16-bit binary code RESULT E to obtain a binary code RESULT F in the true sense, and then directly adds the binary code RESULT F with the 6-bit binary code C of the decoder to obtain a 24-bit binary code value RESULT representing the measuring time length finally.
Thus, the explanation of the entire circuit of the present invention from the circuit block configuration, the operation principle of each block, and the processing of data by each block has been completed.
The above embodiments are only typical examples of the present invention, the present invention is not limited to the embodiments, obviously, various modifications, changes and variations can be made under the concept of the present invention, so the description and the drawings are illustrative and not restrictive, and any modifications and changes made to the above embodiments according to the essence of the present invention shall fall within the protection scope of the present invention.
Claims (1)
1. A special adder for a high time resolution time-to-digital converter is disclosed, wherein the input of the special adder comprises a 16-bit gray code counting RESULT A of a coarse counter in the time-to-digital converter, a 6-bit binary code counting RESULT C of a fine counter decoder in the time-to-digital converter, a halved frequency signal of a counting clock, and a binary value RESULT of 24 bits representing a measuring time length;
characterized in that the special adder comprises: the device comprises a Gray code and binary code conversion module (1), a self-calibration module (2) and an internal logic module (3);
the gray code and binary code conversion module (1) is used for converting a 16-bit gray code counting result A of a coarse counter in a time-to-digital converter into a corresponding binary system for subsequent operation;
the self-calibration module (2) performs self-calibration on a conversion result B of binary codes corresponding to Gray code conversion 16 according to a 16-bit Gray code counting result A of the coarse counter, a 6-bit binary code C of the decoder and a binary frequency division signal of the counting clock, so that a correct result can be still given when a non-ideal condition caused by circuit time delay occurs, and the accuracy and reliability of data are improved;
the self-calibration module (2) comprises a self-adding one module, an alternative selector module and a selector logic judgment module; wherein: the input of the self-adding module is a conversion result B of converting the gray codes and the 16-bit gray codes output by the binary code conversion module into corresponding binary codes, and the output is a 16-bit self-adding result D obtained by adding one gray code and the binary codes; the input of the alternative selector module is a conversion result B of converting gray codes and 16-bit gray codes output by the binary code conversion module into corresponding binary codes, a 16-bit self-adding result D output by the self-adding one module and a selector control signal SEL output by the selector logic judgment module; controlling the alternative selector module to output a 16-bit calibrated binary code result E through a selector control signal; the selector control signal SEL output by the selector logic decision module may be represented by a logic expression as follows:
wherein, the fake _ bind [0] is the lowest bit of the 16-bit gray code counting result A of the coarse counter, the div _2 is a halved frequency division signal of the counting clock, and the decoder [5] is the highest bit of the 6-bit binary code counting result C of the decoder;
the internal logic module (3) is used for processing the 16-bit calibrated binary code RESULT E, shifting the 16-bit binary code RESULT E to the left by 6 bits integrally, subtracting the value of the RESULT to obtain a real binary code RESULT F, and directly adding the real binary code RESULT F and the 6-bit binary code to obtain a 24-bit binary code value RESULT representing the measuring time length so as to solve the problem that the lowest effective bit corresponds to the decimal number 63 and cannot be expressed by the binary code.
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