CN108445735B - Method for correcting hierarchical TDC (time-to-digital converter) by adopting delay chain structure - Google Patents
Method for correcting hierarchical TDC (time-to-digital converter) by adopting delay chain structure Download PDFInfo
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Abstract
A method for correcting a hierarchical TDC (time-to-digital converter) by adopting a delay chain structure relates to the technical field of time-to-digital conversion. The invention aims to solve the problem that in a digital delay chain TDC, the rising edge position relation of an external input signal is uncertain, so that a DFF can generate error output codes. The invention relates to a method for correcting a hierarchical TDC adopting a delay chain structure, which corrects TDC measurement errors caused by the fact that DFF establishment time and retention time are not satisfied by comparing the relative positions of edges of a DFF sampling signal and edges of a sampled signal and a time interval between two signals obtained by delay chain measurement.
Description
Technical Field
The invention belongs to the technical field of time-digital conversion, and particularly relates to a correction method of a hierarchical time-digital converter (TDC).
Background
A TDC is a circuit which is currently very widely used, and functions to convert the time interval between two signals into a digital quantity, and its general operation principle is based on a delay chain. Fig. 2 is a basic structure diagram of a typical digital delay chain TDC, which is formed by combining a delay chain formed by connecting N delay cells (buffers) in series and a flip-flop (DFF) for sampling the output of each delay cell. Assuming that each buffer delays the input signal by a time t, the output digital code Q of the TDC is known from the signal waveforms of Start and Stop in fig. 1N-1...Q2Q1Q0Is in the form of 0 … 01 … 1. If the number of low-order outputs "1" is N, the time interval between the rising edges of Start and Stop of the TDC measurement can be represented as Δ ═ N × t.
The sampling waveform of the flip-flop DFF in fig. 2 is as shown in fig. 3, Stop samples the Start signal, and the rising edge of the Stop signal is located on the left side of the rising edge of the Start signal in the left diagram, where the output of the DFF is "0"; the Stop signal rising edge is to the right of the Start signal rising edge in the right graph, where the DFF output is "1". However, in an actual circuit, if the rising edge of the Stop signal is close to the rising edge of the Start signal (whether on the left side or the right side) or even coincides with the rising edge of the Start signal, the output result of the DFF may be erroneous due to the delay of devices in the DFF circuit, noise and other factors. This is a well-known design principle that needs to be satisfied in digital circuits: the DFF can only guarantee the output of correct results if both the sampled and sampled signals meet the requirements of the setup time and hold time of the DFF.
However, as can be seen from the digital delay chain TDC principle shown in fig. 2, the position relationship between the rising edge of the Start signal and the rising edge of the Stop signal, which are external inputs, and the rising edge of the clock CLK is uncertain, and the rising edges may be closely spaced or even overlapped. Therefore, some of the DFFs have wrong output codes, for example, the correct output is 0 … 0111, and the output becomes 0 … 0101 when the DFF corresponding to Q1 has a mistake.
Disclosure of Invention
The invention provides a method for correcting a hierarchical TDC by using a delay chain structure, which aims to solve the problem that a DFF (digital delay chain) generates an error output code due to uncertain rising edge position relation of an external input signal in the digital delay chain TDC.
A method for correcting a hierarchical TDC using a delay chain structure, the method comprising:
when the Start signal Start arrives, the reference clock counter counts the reference clock CLK, and at the same time, the Start signal Start is fed into the delay chain and the time interval X of the Start signal Start and the reference clock CLK is obtained, 0 ≦ X ≦ T, where T represents the time of one cycle of the reference clock CLK,
when the Stop signal Stop comes, the reference clock counter stops counting and obtains the number N of the reference clock cycles between the Start signal Start and the Stop signal Stop, meanwhile, the Stop signal Stop is sent into the delay chain and obtains the time interval Y between the Stop signal Stop and the reference clock CLK, Y is more than or equal to 0 and less than or equal to T,
the correction method comprises the step of correcting the reference clock period number N, and the method comprises the following steps:
the intermediate judgment value Z is set to satisfy 0< Z < T,
the method comprises the following steps: if the rising edge of the Start signal Start is located on the left side of the rising edge of the reference clock CLK and X < Z, then N-1, and then step two is performed;
if the rising edge of the Start signal Start is located on the right side of the rising edge of the reference clock CLK and X > Z, N is equal to N +1, and then step two is performed;
if the rising edge of the Start signal Start is located on the right side of the rising edge of the reference clock CLK and X < Z, the rising edge of the Start signal Start is located on the left side of the rising edge of the reference clock CLK and X > Z, or X ═ Z, then N is equal to N, and then step two is executed;
step two: if the rising edge of the Stop signal Stop is located on the left side of the rising edge of the reference clock CLK and Y < Z, N is N +1, completing the correction of N;
if the rising edge of the Stop signal Stop is located on the right side of the rising edge of the reference clock CLK and Y > Z, N is N-1, and N is corrected;
if the rising edge of the Stop signal Stop is located on the left side of the rising edge of the reference clock CLK and Y > Z, and the rising edge of the Stop signal Stop is located on the right side of the rising edge of the reference clock CLK and Y < Z, or Y ═ Z, N is equal to N, and the correction of N is completed.
The correction method further comprises the correction of the time interval between the Start signal Start and the end signal Stop, and the method comprises the following steps: substituting the corrected N in the second step into the following formula:
Δ＝N·T-X+Y
the time interval Δ between the corrected Start signal Start and end signal Stop is obtained.
The optimal value of Z is
The most convenient selection is carried out in practical application.
The time interval Δ between the Start signal Start and the end signal Stop is:
the time interval between a Start rising edge and a Stop rising edge, the time interval between a Start falling edge and a Stop falling edge, the time interval between a Start falling edge and a Stop rising edge, or the time interval between a Start rising edge and a Stop falling edge.
The invention provides a method for correcting a hierarchical TDC adopting a delay chain structure. The method corrects TDC measurement errors caused by not meeting DFF setup and hold times by comparing the relative positions of the edges of the DFF sampling signal and the sampled signal and the time interval between the two signals measured by the delay chain. The invention solves the problem that the measurement of the hierarchical TDC output result adopting the delay chain structure is wrong under a specific condition.
Drawings
FIG. 1 is a schematic diagram illustrating a schematic concept of a hierarchical TDC measurement using a delay chain structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a basic structure of a digital delay chain TDC in the prior art;
fig. 3 is a sampling waveform diagram of the DFF of fig. 2.
Detailed Description
The first embodiment is as follows: referring to fig. 1, the embodiment, a method for correcting a hierarchical TDC using a delay chain structure according to the embodiment,
when the Start signal Start arrives, the reference clock counter counts the reference clock CLK, and at the same time, the Start signal Start is fed into the delay chain and the time interval X of the Start signal Start and the reference clock CLK is obtained, 0 ≦ X ≦ T, where T represents the time of one cycle of the reference clock CLK,
when the Stop signal Stop comes, the reference clock counter stops counting and obtains the number N of the reference clock cycles between the Start signal Start and the Stop signal Stop, meanwhile, the Stop signal Stop is sent into the delay chain and obtains the time interval Y between the Stop signal Stop and the reference clock CLK, wherein Y is more than or equal to 0 and less than or equal to T.
The reference clock cycle number N is corrected,
if the intermediate judgment value Z satisfies
The rising edge of the Start signal Start is located to the right of the rising edge of the reference clock CLK and X > Z, then N +1,
the rising edge of the Stop signal Stop is located to the right of the rising edge of the reference clock CLK and Y > Z, then N-1,
through the correction of the N in the two steps, the value of the N can be finally determined to be unchanged.
Substituting the corrected N into the following formula:
Δ＝N·T-X+Y
the time interval Δ between the rising edge of the corrected Start signal Start and the rising edge of the end signal Stop is obtained.
Claims (4)
1. A method for correcting a hierarchical TDC using a delay chain structure, the method comprising:
when the Start signal Start arrives, the reference clock counter counts the reference clock CLK, and at the same time, the Start signal Start is fed into the delay chain and the time interval X of the Start signal Start and the reference clock CLK is obtained, 0 ≦ X ≦ T, where T represents the time of one cycle of the reference clock CLK,
when the Stop signal Stop comes, the reference clock counter stops counting and obtains the number N of the reference clock cycles between the Start signal Start and the Stop signal Stop, meanwhile, the Stop signal Stop is sent into the delay chain and obtains the time interval Y between the Stop signal Stop and the reference clock CLK, Y is more than or equal to 0 and less than or equal to T,
the correction method is characterized by correcting the reference clock period number N, and comprises the following steps:
the intermediate judgment value Z is set to satisfy 0< Z < T,
the method comprises the following steps: if the rising edge of the Start signal Start is located on the left side of the rising edge of the reference clock CLK and X < Z, then N-1, and then step two is performed;
if the rising edge of the Start signal Start is located on the right side of the rising edge of the reference clock CLK and X > Z, N is equal to N +1, and then step two is performed;
if the rising edge of the Start signal Start is located on the right side of the rising edge of the reference clock CLK and X < Z, the rising edge of the Start signal Start is located on the left side of the rising edge of the reference clock CLK and X > Z, or X ═ Z, then N is equal to N, and then step two is executed; step two: if the rising edge of the Stop signal Stop is located on the left side of the rising edge of the reference clock CLK and Y < Z, N is N +1, completing the correction of N;
if the rising edge of the Stop signal Stop is located on the right side of the rising edge of the reference clock CLK and Y > Z, N is N-1, and N is corrected;
if the rising edge of the Stop signal Stop is located on the left side of the rising edge of the reference clock CLK and Y > Z, and the rising edge of the Stop signal Stop is located on the right side of the rising edge of the reference clock CLK and Y < Z, or Y ═ Z, N is equal to N, and the correction of N is completed.
2. The method of claim 1, wherein the method further comprises correcting the time interval between the Start signal Start and the end signal Stop, and the method comprises: substituting the corrected N in the second step into the following formula:
Δ＝N·T-X+Y
the time interval Δ between the corrected Start signal Start and end signal Stop is obtained.
3. The method as claimed in claim 1 or 2, wherein the delay chain structure comprises a plurality of delay chain structures,
4. the method of claim 2, wherein a time interval Δ between the Start signal Start and the end signal Stop is:
the time interval between a Start rising edge and a Stop rising edge, the time interval between a Start falling edge and a Stop falling edge, the time interval between a Start falling edge and a Stop rising edge, or the time interval between a Start rising edge and a Stop falling edge.
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| CN109444856B (en) * | 2018-08-31 | 2020-07-31 | 西安电子科技大学 | Integer period measuring circuit applied to high-resolution time-to-digital converter |
| CN109116717B (en) * | 2018-09-28 | 2019-09-03 | 东北大学 | A kind of time interval measurement method based on multiple repairing weld |
| CN110045592B (en) * | 2019-05-17 | 2021-02-19 | 湖北京邦科技有限公司 | Time correction method, device, system and computer storage medium |
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| CN105871371B (en) * | 2016-03-25 | 2018-08-10 | 东南大学 | A kind of three-stage time-to-digital conversion circuit based on phaselocked loop |
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