CN109143832B - High-precision multichannel time-to-digital converter - Google Patents
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Abstract
The invention discloses a high-precision multichannel Time-to-Digital Converter (TDC), which adopts a two-stage structure; the first-stage structure adopts a pulse counting type time-to-digital converter based on a carry look-ahead adder and is used for realizing high working frequency and large dynamic range; the second-stage structure adopts a multi-channel time-to-digital converter based on a voltage-controlled differential delay unit and a true single-phase clock trigger, and is used for improving the measurement precision and reducing the measurement error. The product utilizes the principle of two-stage measurement, and gives consideration to the dynamic range and the resolution ratio. A voltage-controlled differential inverter and a True single-phase clock Trigger (TSPC) are used in the second-stage TDC, so that good linearity and low error rate of the system are guaranteed, meanwhile, the whole framework adopts a three-channel structure, the length of a single delay chain is reduced by 2/3, the uncertainty is reduced by 43%, and the performance of the system is effectively improved.
Description
Technical Field
The invention relates to the field of integrated circuit design and time mode signal processing technology application, in particular to a high-precision multi-channel time-to-digital converter.
Background
In recent years, as the line width of the integrated circuit manufacturing process is becoming smaller, the analog integrated circuit is susceptible to noise in a low voltage process with a line width of less than 100nm, and it is difficult to achieve the desired performance. With the reduction of the process size, the digital integrated circuit has obviously improved switching speed, area and noise suppression capability. The digital integrated circuit can fully play the advantages of advanced technology when processing time domain signals, but cannot directly process signals in an amplitude domain. In order to apply the excellent characteristics of Digital integrated circuits in advanced processes to the design of analog integrated circuits and mixed signal circuits, how to convert continuous voltage signals in the analog domain into continuous Time signals has become a research focus in recent years, and Time-to-Digital converters (TDCs) capable of converting continuous Time signals into discrete Digital signals have been proposed. In addition, in the fields of high-energy physics, laser ranging, particle physics, laser three-dimensional imaging and the like, a digital converter (TDC) is also a core unit of a high-precision time interval measurement system. Therefore, the research of digital converters (TDCs) is of great significance to both integrated circuit design and high precision time measurement.
The performance of a TDC is usually measured by parameters such as time resolution, dynamic range, and measurement error. Which respectively represent the minimum time interval that the TDC can measure, the maximum time interval, and the probability of measurement error. At present, the following three common TDCs are mainly available: 1. the pulse counting type TDC can adjust the digit of a counter to realize a high dynamic range, but has low resolution and is limited by the frequency of a system clock; 2. the resolution of the TDC based on gate delay is the delay value of a single logic gate, and is limited by the current process, the dynamic range of the TDC depends on the number of the logic gates on a delay line, but the increase of the length of the delay line leads to the sharp increase of the area of a chip, meanwhile, the uncertainty of a time interval is increased, and a larger measurement error is introduced, so the dynamic range of the TDC is generally smaller; 3. the typical representation of this kind of TDCs is a vernier TDC, which can achieve very high accuracy by adjusting the delay time difference of the delay units in the two delay chains, but when the dynamic range is large, the length of the delay chain will be long, and at this time, the measurement error of the TDC will be large, which reduces the effective accuracy.
In summary, it is a difficult task to reduce the measurement error as small as possible while achieving a large dynamic range and high resolution.
Disclosure of Invention
In order to overcome the contradiction between the dynamic range, the resolution and the measurement error of the traditional time-to-digital converter, the invention provides a time-to-digital converter with a two-stage structure, wherein the first stage adopts a pulse counting type TDC based on a carry-ahead adder to realize high working frequency and large dynamic range; the second stage adopts a multi-channel TDC based on a voltage-controlled differential delay unit and a True single-phase clock Trigger (TSPC), which is essentially a TDC based on gate delay to improve measurement accuracy and reduce measurement error, as described in detail below:
a high-precision multi-channel time-to-digital converter adopts a two-stage structure;
the first-stage structure adopts a pulse counting type time-to-digital converter based on a carry look-ahead adder and is used for realizing high working frequency and large dynamic range;
the second-stage structure adopts a multi-channel time-to-digital converter based on a voltage-controlled differential delay unit and a true single-phase clock trigger, and is used for improving the measurement precision and reducing the measurement error.
Further, the true single phase clock flip-flop is used to ensure that the flip-flop has a small setup hold time.
Preferably, the second-stage structure adopts a 3-channel structure.
Wherein, the 3-channel structure specifically comprises:
the output of the first delay element in the first channel is connected to the data input of the first TSPC register for resolving the size t1The time interval of (c);
the output of the first delay cell in the second channel is connected to the data input of the second TSPC register for resolving the size t2＝2·t1The time interval of (c);
the output of the first delay unit in the third channel is connected to the data input end of the third TSPC register for distinguishing the value t3＝3·t1The time interval of (c);
then the output of the second delay unit in the first channel is connected to the data input end of the fourth TSPC register for distinguishing the size t3+t1The time intervals of (c), and so on.
Preferably, the length of the delay chain in each channel is L/3, and L is the length under the same dynamic range.
Preferably, the uncertainty of the time interval is 57% of the conventional uncertainty.
The technical scheme provided by the invention has the beneficial effects that:
1. in the first-stage TDC, the synchronous counter uses a carry-ahead adder to replace a traditional travelling wave carry adder in the implementation process, so that the long conversion time caused by the increase of the number of counting digits is effectively avoided, the working frequency of the circuit is improved, and the dynamic range is expanded.
2. In the second stage TDC: the delay unit adopts a Voltage-controlled differential inverter, and the delay value of the delay unit is controlled by the Voltage, so that the problem of mismatching of the delay unit caused by factors such as Process, Voltage, Temperature (PVT) and the like is effectively solved, and the measurement error is reduced.
Since the TSPC trigger has a small setup hold time, the measurement error of the TDC can be reduced. Meanwhile, the integral framework of the second-stage TDC is a three-channel structure, under the same dynamic range, the length of a single delay chain is only 1/3, and the uncertainty of a time interval is reduced to about 57% of the original length, so that the performance parameters of the TDC are obviously improved.
3. The time-to-digital converter designed by the invention is realized based on a standard CMOS process, and can realize the integration of a high-performance time-to-digital converter, a signal coding module and an arithmetic operation module on the same chip, thereby reducing the cost of devices and enhancing the fusion of functions.
Drawings
FIG. 1 is a block diagram of a TDC system design according to the present invention;
FIG. 2 is a detailed structural schematic diagram of the interior of the TDC circuit;
FIG. 3 is a schematic diagram of a measurement principle of a TDC module;
FIG. 4 is a schematic of the logic structure of the first stage TDC;
FIG. 5 is a schematic diagram of a conventional TDC circuit based on a delay unit;
figure 6 is a circuit diagram of a three channel TDC with edge calibration and delay compensation modules;
FIG. 7 is a schematic diagram of a voltage-controlled differential delay unit;
wherein, (a) is a structural schematic diagram of the voltage-controlled differential delay unit; (b) is a circuit diagram of a voltage-controlled differential delay unit.
Fig. 8 is a circuit diagram of a TSPC flip-flop.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.
Example 1
A high-precision multi-channel time-to-digital converter, referring to fig. 1, the time-to-digital converter (i.e. TDC system) mainly comprises: TDC circuit, encoder (2) and arithmetic unit three parts.
The TDC circuit quantizes the time interval between the input STRAT signal and STOP signal by clock signal CLK, and respectively outputs code word T1、t2And t3Wherein T is1Is a binary code representing the time interval between the START signal and the STOP signal which is an integer multiple of the CLK period, t2And t3The temperature code represents the time interval between the rising edge of the START signal and the rising edge of the STOP signal and the nearest next cycle clock respectively. T is1Directly into an arithmetic unit, t2And t3Respectively input into a temperature code-binary code encoder to be converted into a binary code T2And T3Then input into an arithmetic unit, together with T1And participating in calculation to output a final time interval T, and finishing the whole measuring process.
Example 2
The scheme of example 1 is further described below with reference to specific calculation formulas and fig. 2-8, and is described in detail below:
fig. 2 is a detailed structure of the inside of the TDC circuit, which is described in conjunction with the measurement principle of fig. 3. The TDC circuit has a two-stage structure.
Wherein a synchronous counter (first stage TDC) is used to measure integer multiples of the CLK period in the time interval to be measured, A1(as shown in FIG. 3), outputting binary code T1. Two identical fine TDCs (second-stage TDCs) for A less than one clock cycle2And A3(as shown in FIG. 3) and outputs a temperature code t2And t3And converted into binary code T by encoder2And T3。
Then, T is calculated by an arithmetic operation unit1+T2-T3The time interval T between the START and STOP signals is obtained. An edge calibration module in a TDC circuit for generating differential signals required for a fine TDC without error, a delay calibration unit for compensating for edges between CLK, START and STOP signalsAnd calibrating the delay error introduced by the module.
Fig. 4 is a logic structure of the first stage TDC, and the computation logic using the carry-look-ahead full adder as the synchronous counter is a special case of the adder: one addend of each bit full adder is 0, and the other is the output S of the previous time of the current bitiCarry of lowest order C0During the first stage TDC operation, 1 is constant, and the carry C of the rest bitsiIs a logic expression of the addend on all the previous bits (the logic relation is not shown in the figure). Output S of ith bit of ordinary full adderiAnd carry out CiThe logical expression of (a) is:
Si＝Ai⊕Bi⊕Ci-1(1)
Ci＝AiBi+(Ai+Bi)Ci-1＝Gi+PiCi-1(2)
wherein G isi＝AiBiFor carry generation functions, Pi＝Ai+BiIs a carry transfer function. According to the formulas (1) and (2), G in the present designi＝0,Pi＝AiSo that S of each bit adderiAnd CiRespectively as follows:
Si＝Ai⊕Ci-1(3)
Ci＝AiCi-1(4)
thus, the carry output C of the 6-bit adderiCan be respectively expressed as:
the output expression of each bit adder can be obtained from equation (3). It follows that each bit output and carry output of the adder is a logical representation of the input signal, which are generated in parallel.
Since the first stage TDC requires recording the number of clock cycles involved between the START and STOP signals, START and STOP are the control signals for the counter. The control logic is as follows: when START is 1, SWhen TOP is also 1, C00; in the rest cases, C0From this, it is known that C can be obtained by nand operation of the START signal and the STOP signal0I.e. C0＝！(START&STOP). The START signal also serves as a reset signal of the synchronous counter, and when the START signal is at a high level, the counter is cleared and STARTs counting, and when a rising edge of the STOP signal arrives, the value of the current counter is latched and the count result is output.
Fig. 5 is a conventional structure of a fine TDC (second-stage TDC). The START signal propagates along the above delay chain, where each delay cell has a delay of t and the STOP signal is connected to the clock terminal of the D flip-flop, each delayed START signal is sampled, the output of the D flip-flop is 1 before the STOP signal catches up with the START signal, and the output of the D flip-flop becomes 0 as soon as the STOP signal catches up with or leads the START signal. If the initial phase difference between the START signal and the STOP signal is TinAnd the last 1 in the temperature code appears in the nth stage, then:
n·t≤Tin<(n+1)·t (6)
due to the influence of noise, each stage of delay unit has a certain delay deviation. Let us assume that the delay deviation of the i-th stage delay unit is mui(this value can be positive or negative), the delay t of the i-th stage delay unitres,iThe correction can be as follows:
tres,i＝t+μi(7)
thus, the time interval TinCan be expressed as:
wherein mu is the sum of the delay deviations of all delay units on the whole delay chain.
Since the environment of each stage of delay unit is the same, the standard deviation of the delay value of each stage of delay unit is the same, i.e. std (t)res,i)＝std(μi) Std (mu), uncertainty std (T) of time interval after n stages of delay unitsin) Comprises the following steps:
it follows that the uncertainty std (T) of the time intervalin) In relation to the length n of the delay chain, the longer the delay chain length, the greater the uncertainty of the measured time interval.
Fig. 6 is a structure of a fine TDC in the embodiment of the present invention. Its essence is a TDC based on gate delay, where: a voltage-controlled differential inverter is used as a delay unit, so that good matching degree between the delay units is ensured; the TSPC trigger is used for replacing a common D trigger to judge the precedence relationship of the start signal phase and the stop signal phase, so that the trigger is ensured to have as short as possible establishment holding time; meanwhile, in order to reduce the uncertainty of measurement, the second-stage TDC adopts a novel 3-channel structure.
Wherein the START signal propagates in three channels respectively, and the delay size of the first delay unit in each channel is related to t2＝2·t1，t3＝3·t1The delay sizes of the other residual delay units are t3. The output of the first delay element in lane 1 (i.e., the first lane) is coupled to the data input of the first TSPC register, which can resolve the size t1The time interval of (c); the output of the first delay cell in channel 2 (i.e., the second channel) is coupled to the data input of the second TSPC register, which can resolve the size t2＝2·t1The time interval of (c); the output of the first delay cell in channel 3 (i.e., the third channel) is coupled to the data input of the third TSPC register, which can resolve the size t3＝3·t1The time interval of (c); the output of the second delay cell in channel 1 is then connected to the data input of the fourth TSPC register, which can resolve the size t3+t1I.e. 4. t1The time intervals of (c), and so on. It can be known that the time resolution of the entire fine TDC is t1And under the same dynamic range, the length of the delay chain in each channel is only 1/3 of the conventional implementation method (i.e., if the length of the conventional implementation method is L, the method is L/3).
Represented by the formula (9)) It can be seen that when n is changed to 1/3, the uncertainty of the time interval remains unchanged under other conditions
The original 57% is changed, and therefore the uncertainty of the time interval of the scheme provided by the embodiment of the invention is only about 57% of the traditional uncertainty, and the performance of the TDC is obviously improved.
In the second stage TDC, in order to eliminate a phase difference that may exist between the START signal and the inverted signal thereof input to the voltage-controlled differential inverter, the START signal and the inverted signal thereof need to be input to the edge alignment module to perform an edge alignment process. However, the edge calibration module may introduce additional delay, resulting in large measurement results.
To compensate for this delay, the STOP signal needs to be delay compensated by a delay calibration unit before being input to the second stage TDC. The second stage TDC is the most critical part of the time-to-digital converter, and has high requirements on the delay value of the delay unit and the setup hold time of the D flip-flop, which are described separately below.
Fig. 7(a) shows a schematic diagram of the structure of the voltage-controlled differential inverter. In + and In-are two differential input ends, two differential signals with opposite states are input, Out + and Out-are signal output ends, and output signals are also differential signals with opposite states, so that when a plurality of voltage-controlled differential inverters are connected In series, the differential output of the previous stage can be just used as the differential input of the next stage. Compared with the simplest inverter, although the input signals are changed from one to two, the differential structure provides stronger interference resistance. Fig. 7(b) is a circuit configuration of the voltage-controlled differential inverter, and it can be seen that each cell has only 5 transistors, ensuring a small chip area. The working process is as follows: when the In + input is high and the In-input is low, M3 is on, M4 is off, and M5 is always on under control of Vbias, so Out-output is low, M2 is on, and Out + output is high. The analysis is the same as above when In + is input to low level and In-is input to high level, and the description is omitted here.
In specific implementations, for example: the size of the unit delay value can be adjusted by controlling the grid voltage of M5, and the larger the grid voltage of M5 is, the smaller the delay value is, thereby ensuring the good linearity of the delay chain and reducing the measurement error.
Fig. 8 is a circuit configuration of the TSPC flip-flop. The working process is as follows: when CLK is at low level, the first-stage inverter samples the inverted value of the input signal IN on the node X, the second-stage inverter is IN a pre-charging state, the node Y is charged to power voltage, the third-stage inverter is IN a holding state, namely the potential of the point Z is kept unchanged, and the output OUT keeps the original value; when the CLK is changed to a high level, the second-stage inverter starts to work, if the X node is at a high level when the rising edge of the CLK comes, the Y node is discharged, otherwise, the value of the Y node is kept in the original state, and because the third-stage inverter works normally when the CLK is at a high level, the value of the Y node is transmitted to the output end OUT.
From the viewpoint of discrimination accuracy, the setup time of the TSPC flip-flop is the delay of the first stage inverter, and the hold time is the delay of the second stage inverter, for example: the minimum establishing and holding time can be realized by adjusting the width-length ratio of the transistors in the two stages of inverters, errors in data sampling are avoided, and the precision of the system is further improved.
In summary, the high-precision multi-channel time-to-digital converter described in the embodiments of the present invention utilizes the principle of two-stage measurement, and combines the dynamic range and the resolution. A voltage-controlled differential inverter and a TSPC are used in the second-stage TDC, so that good linearity and low error rate of the system are guaranteed, meanwhile, a three-channel structure is adopted in the whole framework, the length of a single delay chain is reduced by 2/3, the uncertainty is reduced by 43%, and the performance of the system is effectively improved.
In the embodiment of the present invention, except for the specific description of the model of each device, the model of other devices is not limited, as long as the device can perform the above functions.
Those skilled in the art will appreciate that the drawings are only schematic illustrations of preferred embodiments, and the above-described embodiments of the present invention are merely provided for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (2)
1. A high-precision multi-channel time-to-digital converter is characterized in that,
the time-to-digital converter adopts a two-stage structure;
the first-stage structure adopts a pulse counting type time-to-digital converter based on a carry look-ahead adder and is used for realizing high working frequency and large dynamic range;
the second-stage structure adopts a multi-channel time-to-digital converter based on a voltage-controlled differential delay unit and a true single-phase clock trigger, and is used for improving the measurement precision and reducing the measurement error; the second-stage structure adopts a 3-channel structure;
the 3-channel structure specifically comprises:
the output of the first delay element in the first channel is connected to the data input of the first TSPC register for resolving the size t1The time interval of (c);
the output of the first delay cell in the second channel is connected to the data input of the second TSPC register for resolving the size t2＝2·t1The time interval of (c);
the output of the first delay unit in the third channel is connected to the data input end of the third TSPC register for distinguishing the value t3＝3·t1The time interval of (c);
then the output of the second delay unit in the first channel is connected to the data input end of the fourth TSPC register for distinguishing the size t3+t1The time intervals of (a) and (b) are sequentially cycled;
under the same dynamic range, the length of the delay chain in each channel is L/3, L is the length, and the uncertainty of the time interval is 57 percent of the original uncertainty.
2. A high accuracy multichannel time to digital converter as claimed in claim 1, characterized in that said true single phase clock flip-flop is used to guarantee a small setup hold time for the flip-flop.
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| DE102019205731A1 (en) * | 2019-04-18 | 2020-10-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Time-to-digital converter arrangement |
| CN112764342B (en) * | 2019-11-01 | 2022-02-18 | 北京一径科技有限公司 | Time measuring device and method |
| CN110865057B (en) * | 2019-11-06 | 2022-04-08 | 天津大学 | Non-uniform time-to-digital converter applied to fluorescence lifetime imaging |
| CN110794668B (en) * | 2019-11-14 | 2021-03-12 | 中电科思仪科技股份有限公司 | Time interval measuring device and method based on multi-channel interpolation |
| CN114280912A (en) * | 2020-09-28 | 2022-04-05 | 宁波飞芯电子科技有限公司 | Method for measuring flight time and time-to-digital converter |
| CN113835332B (en) * | 2021-09-29 | 2022-08-23 | 东南大学 | High-resolution two-stage time-to-digital converter and conversion method |
| CN115902835B (en) * | 2021-09-30 | 2024-02-27 | 深圳市速腾聚创科技有限公司 | Radar data receiving and transmitting device, ranging method and laser radar |
| CN114967409B (en) * | 2022-03-28 | 2023-06-20 | 中山大学 | PVT variation-resistant high-precision time-to-digital converter and implementation method thereof |
| CN116991227B (en) * | 2023-09-26 | 2024-01-26 | 北京中科昊芯科技有限公司 | Device for acquiring high-precision signals, soC chip and electronic equipment |
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