CN214480526U

CN214480526U - Residual time sampling circuit based on differential sampling and time-to-digital converter

Info

Publication number: CN214480526U
Application number: CN202120414921.8U
Authority: CN
Inventors: 张彪; 白雪飞
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2021-02-25
Filing date: 2021-02-25
Publication date: 2021-10-22
Anticipated expiration: 2031-02-25

Abstract

The utility model discloses a residual time sampling circuit and time digital converter of difference sampling, residual time sampling circuit includes the arbiter based on sensitive amplifier, the buffer and by the phase inverter of four MOS pipe series connections, CTDC output signal and Stop signal input carry out the comparison to the arbiter input based on sensitive amplifier, the opposite signal Q and the P of arbiter output symmetry are as the on-off control signal who constitutes the phase inverter by four MOS pipes, wherein, arbiter output Q end is connected to the grid of phase inverter NMOS pipe N1 and PMOS pipe P2, output P end is connected to another PMOS pipe P1's grid; the gate of another NMOS transistor N2 In the inverter is connected to the signal In, N ═ 1,2.. 16 through a buffer unit with a delay t; the residual time sampling circuit adopts a symmetrical structure, and the circuit is ensured to introduce the same error in the sampling process of the CTDC output signal and the Stop signal.

Description

Residual time sampling circuit based on differential sampling and time-to-digital converter

Technical Field

The utility model relates to a semiconductor integrated circuit field especially relates to a residual Time sampling circuit based on difference sampling and two-stage Time Digital Converter (Time-to-Digital Converter, TDC) based on gate ring oscillator.

Background

The residual time sampling circuit is applied to the design of a two-stage or multi-stage time-to-digital converter, and the time margin acquisition in the coarse quantization TDC is transferred to the fine quantization TDC. The time-to-digital converter is used for converting the time interval between the signals into corresponding numbers and outputting the corresponding numbers. At present, the TDC is widely applied to scientific research fields such as laser ranging, 3D imaging, quantum communication, nuclear physics, and the like, and TDCs of various structures emerge endlessly to meet the requirements of various engineering and scientific research fields.

With the great improvement of the semiconductor process level, the measurement precision of time is gradually improved and the femtosecond resolution is gradually achieved. Meanwhile, the time delay and low power consumption of the digital gate circuit are reduced along with the process, so the performance and power consumption performance of the time domain and digital domain circuit are continuously improved, and higher resolution and better linearity can be obtained in the time domain and the digital domain.

Disclosure of Invention

In order to solve the technical problem, the utility model provides a low-power consumption, accurate high residual time sampling circuit based on difference sampling and a high resolution, high linearity, great range and automatic re-setting's time-to-digital converter realizes quantizing input time interval accurately, exports corresponding digital signal. Meanwhile, a specific MOS tube is added in the rising edge/falling edge arbiter, so that the automatic reset function of the circuit is realized. In addition, compared with the traditional serial output circuit, the serial output circuit realized by adopting the improved trigger has simpler circuit structure and higher output frequency.

The utility model aims at realizing through the following technical scheme: a differentially sampled residual time sampling circuit, comprising: the device comprises an arbiter based on a sense amplifier, a buffer and a phase inverter formed by connecting four MOS tubes in series, wherein a roughly quantized TDC output signal and a Stop signal are input into the input of the arbiter based on the sense amplifier for comparison, and the arbiter outputs opposite signals Q and P with symmetry as switching control signals of the phase inverter formed by the four MOS tubes, wherein the Q end of the output of the arbiter is connected to the grid electrodes of an NMOS tube N1 and a PMOS tube P2 of the phase inverter, and the P end of the output of the arbiter is connected to the grid electrode of another PMOS tube P1; the gate of another NMOS transistor N2 In the inverter is connected to the signal In, N ═ 1,2.. 16 through a buffer unit with a delay t; the residual time sampling circuit adopts a symmetrical structure, and the circuit is ensured to introduce the same error in the sampling process of the coarse quantization TDC output signal and the Stop signal.

The utility model also provides a time digital converter based on gate control ring oscillator that utilizes the design of residual time sampling circuit, including coarse quantization TDC, fine quantization TDC, residual time sampling circuit, thermometer code/binary code converting circuit, serial output circuit, voltage-controlled phase-locked loop circuit, end signal generating circuit;

the voltage-controlled phase-locked loop circuit generates a voltage Vc to control all voltage-controlled delay units in the coarse quantization TDC; the output end of the coarse quantization TDC is respectively connected to a thermometer code/binary code conversion circuit, a residual time sampling circuit and a serial output circuit; the residual time sampling circuit transmits the time margin after the coarse quantization TDC is quantized into the fine quantization TDC; the output end of the fine quantization TDC is respectively connected to the thermometer code/binary code conversion circuit, the serial output circuit and the end signal generation circuit, wherein the end signal generation circuit is used for judging the output signal of the arbiter in the fine quantization TDC to generate an end signal to instruct the thermometer code/binary code conversion circuit and the serial output circuit to read the results of the arbiter in the coarse quantization TDC and the fine quantization TDC for conversion and output.

Further, a voltage-controlled delay chain is adopted as a high-section TDC structure, wherein the delay of a delay unit in the voltage-controlled delay chain is controlled and adjusted by the output voltage Vc of a voltage-controlled phase-locked loop, the low-section TDC adopts a vernier caliper type ring oscillator structure, a counter is added, and meanwhile, an end signal is fed back to an enable signal generating circuit.

Furthermore, a buffer unit formed by the simplest inverter is added behind the delay unit of the coarse quantization TDC and the delay phase-locked loop circuit, and the buffer unit is connected to each load through the output of the buffer unit.

Further, the coarse quantization TDC includes: a fast ring oscillator, a rising edge arbiter, a falling edge arbiter, a slow ring oscillator, and a four bit counter; the output of each delay unit in the fast ring oscillator and the slow ring oscillator is connected to the corresponding rising edge arbiter and the falling edge arbiter; the output of the first delay unit of the slow ring oscillator is used as a clock signal of the four-bit counter, and the oscillation period of the slow ring oscillator is the period of the trigger clock of the four-bit counter.

Further, the rising edge arbiter adds two PMOS tubes to the sense amplifier based arbiter, the sources of the two tubes are connected to the power voltage, the drains are connected to the input ends of two symmetrical output inverters respectively, and the gates are connected to the reset signal EVEN _ R; an NMOS tube is respectively added between the input ends of two symmetrical output buffers in the falling edge arbiter and the ground, and the gates of the NMOS tubes are connected to a reset signal ODD _ R.

Furthermore, the serial output circuit adopts a TSPC register, and two MOS tubes M1 and M2 are added to the TSPC register for sampling the result of the arbiter; the input port J of the register is connected to the output of the arbiter, and the input port T is connected to a fine quantization TDC quantization end flag signal R _ SIG; when the flag signal R _ SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R _ SIG is equal to one, the register serially outputs data triggered by the clock CLK, and the signal TC is generated by the signal R _ SIG.

The utility model adopts the above technical scheme to compare with prior art, have following technological effect:

(1) the utility model discloses in increase the same buffer unit behind the delay unit of coarse quantization TDC and delay phase-locked loop circuit, guaranteed promptly that the load of delay unit is the same in two circuits, increased the load capacity of delay unit in the coarse quantization TDC simultaneously to block the influence of the different input state of arbiter to delay unit time delay in the coarse quantization TDC, improve the linearity of coarse quantization TDC;

(2) the utility model reduces the power consumption of the time-to-digital converter by feeding back the end signal to the enable signal circuit;

(3) the utility model adopts a specific reset system, and adds an extra reset MOS tube in the rising edge/falling edge arbiter to ensure that the output of the arbiter is zero before quantization;

(4) the residual time sampling circuit in the utility model adopts a symmetrical structure, and simultaneously, the control of a plurality of signals ensures that no path is formed in the circuit, thereby reducing the power consumption of the circuit;

(5) the utility model discloses a serial output circuit realizes the sampling of data and two kinds of modes of transmission through specific control circuit and trigger, compares in traditional serial output circuit, and this circuit structure is simpler, and output frequency is higher.

Drawings

Fig. 1 is a schematic diagram of the overall circuit structure of the time-to-digital converter of the present invention;

FIG. 2 is a schematic timing diagram of the present invention;

fig. 3 is a coarse quantization TDC and remaining time sampling circuit provided by the present invention;

fig. 4 is a schematic diagram of a control circuit according to the present invention, (a) is a schematic diagram of generating a reset signal RST by inverting the Stop signal and performing a phase and operation with the Start signal; (b) the interval time Ti between the Stop signal and the Start signal is very small;

FIG. 5 is a generation circuit of a fine quantized TDC enable signal;

FIG. 6 is a circuit for generating an end signal R _ SIG;

FIG. 7 is a schematic diagram of a fine-scaled TDC circuit using a gated vernier caliper ring oscillator mechanism;

FIG. 8 illustrates a rising edge arbiter circuit and a falling edge arbiter circuit according to the present invention; (a) an arbiter circuit for a rising edge; (b) a falling edge arbiter circuit;

fig. 9 shows a serial output circuit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

According to the utility model discloses an embodiment, a time digital converter based on difference sampling, fig. 1 is shown, including Coarse quantization TDC (Coarse TDC, CTDC), Fine quantization TDC (Fine TDC, FTDC), remaining time sampling circuit, thermometer code/binary code converting circuit, serial output circuit, voltage-controlled phase-locked loop circuit.

Quantizing an input time interval, namely a time difference between rising edges of a Start signal and a Stop signal, by using a CTDC (computer to digital converter), and outputting 4 most significant bits by a decoder according to a quantization result; the residual time sampling circuit extracts the residual time of the CTDC, converts the residual time into a time difference between rising edges of a signal SE and a signal FE, inputs the time difference into the FTDC for re-quantization, and generates 7-bit least significant bits by a decoder according to a quantization result; the control circuit turns off the FTDC quantization action after detecting the FTDC quantization end signal and turns on the output of the serial circuit.

In order to avoid the influence of the external environment on the circuit, the voltage-controlled phase-locked loop circuit is added into the system, so that the stability and the accurate delay time of the system are improved. Fig. 2 is a timing diagram of the TDC of the present invention, in which the time difference between the rising edges of the Start signal and the Stop signal is the input time interval. The voltage controlled phase locked loop equally divides the period of the reference clock Fref with the frequency of 100MHz into fifty parts, and the delay value of each delay unit in the CTDC is maintained at 200 ps. The remaining time sampling circuit transmits the remaining time, i.e., the rising edge of the Stop signal and the rising edge of the first delay unit located after the Stop signal in the CTDC to the FTDC, wherein the FTDC includes two delay chains with different delays, a fast delay chain and a slow delay chain, i.e., an F-chain and an S-chain, as shown in fig. 7. And subtracting the delay difference t of the two delay units every time the residual time passes through one delay unit in the F chain until the rising edge or the falling edge of the output signal Fn of the F chain delay unit is earlier than that of the output signal Sn (n is 0,1.. 6) of the S chain delay unit, and indicating that the quantization is finished. The quantization result is calculated as:

T_in＝T×(N_c+1)-(T₁-T₂)×N_f (1)

wherein N is_cAnd N_fOutputs of CTDC respectivelyAnd the output of FTDC is binary code obtained by a decoding circuit, T is the delay of a delay unit in CTDC, T₁、T₂The delay of the delay unit of the slow delay chain and the fast delay chain in the FTDC respectively. Fig. 3 is a schematic diagram of a CTDC and remaining time sampling circuit according to an embodiment of the present invention. The device comprises an arbiter based on a sensitive amplifier, a buffer with larger time delay and an inverter formed by connecting four MOS in series, wherein the output of the arbiter and the buffer is used as an input signal of the inverter. In order to correctly sample the input signal, it is necessary to ensure that the signal passes through the buffer for a longer time than the arbiter.

Before each quantization, the reset signal R of the arbiter turns on the MOS transistors M1 and M4, pulling C0 and D0 high, and the outputs P and Q of the arbiter are reset to low through the inverter. Therefore, the MOS transistors P1 and P2 in the sampling unit are in the on state, pulling StartL and StopL high, and the output signals StopN and StartN are also reset to low. The output In (N ═ 1,2.. 14) of each delay cell of the CTDC at quantization is connected to the D port of the corresponding arbiter and compared with the SP signal input to the C port of the arbiter, and when the rising edge of In is located after the rising edge of the signal SP, the output Q of the corresponding arbiter rises high, so that the connected sampling cell pulls the signal StartL low through the MOS transistors N1 and N2, and the output signal StopN also rises high accordingly. Because each delay unit in the CTDC is connected with an arbiter and a residual time sampling circuit, in order to ensure that the load of the delay unit in the CTDC is the same as that of the delay unit in the voltage-controlled phase-locked loop, a buffer unit is connected to the delay unit in the two circuits, and the buffer unit is connected to other circuits. Meanwhile, the addition of the buffer unit increases the load capacity of each delay unit and avoids the influence of different states of the arbiter on the delay. The residual time sampling circuit ensures the balance of the system by using a symmetrical structure and reduces errors. To ensure that the time margin can be correctly collected, it is necessary to ensure that the time for the Stop to reach Y through the arbiter is less than the time t for the Stop to reach X through the buffer.

Before each measurement, the circuit needs to be ensured to be in an original state, so that a reset signal is generated to reset the FTDC, the arbiter, the counter and the like before the measurement. In fig. 4(a), the reset signal RST is generated by inverting the Stop signal and performing an and operation with the Start signal. Since the reset of the circuit requires a certain time, it has to be ensured that the reset pulse of the reset signal can be larger than the minimum reset time of the circuit. As shown in fig. 4(b), when the interval time Ti between the Stop signal and the Start signal is small, it is necessary to make the delay T of the inverter larger than the reset time of the circuit in order to ensure that the circuit can be reset.

Fig. 5 is a circuit for generating an FTDC enable signal, in order to ensure that the oscillator can automatically stop oscillation after FTDC quantization is finished to reduce power consumption, a quantization end signal R _ SIG is added to the circuit to control generation of the enable signal, that is, when R _ SIG is equal to zero, the StartN and StopN signals can generate the enable signal.

Fig. 6 shows a circuit for generating an R _ SIG signal, where circuit input signals Qn and Pn (n is 0,1.. 6) are output signals of arbiters in the FTDC, and when an output of one of the arbiters is at a high level, a circuit output thereof becomes a high level, which indicates that the FTDC quantization is finished.

FIG. 7 is a schematic diagram of an FTDC circuit employing a gated vernier caliper ring oscillator mechanism, comprising: fast ring oscillator 1, rising edge arbiter 2, falling edge arbiter 3, slow ring oscillator 4, and four bit counter 5. Before quantization, the reset signal EVEN _ R resets the output of the EVEN stage delay cells in the fast/slow ring oscillator to zero, and the signal ODD _ R sets the ODD stage delay cells to one. After CTDC quantization is finished, SE/SB and FE/FB signals are generated as starting signals of the fast ring oscillator and the slow ring oscillator respectively. And simultaneously inputting outputs Fn and Sn (n is 0.. 6) of the fast ring oscillator and the slow ring oscillator into a rising edge and falling edge arbiter, and judging whether the rising edge or the falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or the falling edge of the output signal of the slow ring oscillator. The counter starts counting as triggered by the slow ring oscillator output S0, and increments every time the signal goes through the S oscillator for one cycle, the final result being decremented by one because the counter automatically increments each time the FTDC starts quantizing. The quantization result of FTDC can thus be expressed as:

T_FO＝((N_C-1)×14+N_F)×(T_S-T_F) (2)

wherein N is_CRepresenting the output of a counter, N_FRepresenting the count of the oscillator, T_SIndicating S-oscillator delay unit delay, T_FRepresenting the F oscillator delay unit delay.

The rising edge arbiter is implemented by adding two PMOS transistors P1 and P2 to a conventional sense amplifier based arbiter, as shown in fig. 8(a), the source of the MOS transistor is connected to the supply voltage, the drain is connected to C0 or D0, and the gate R2 is connected to the reset signal EVEN _ R, resetting the arbiter output to zero at the beginning of quantization. Similarly, NMOS transistors N1 and N2 are added between C0, D0 and ground in the falling edge arbiter shown in fig. 8(b), while the gate R2 is connected to the reset signal ODD _ R. The minimum time difference between the input signals that can be detected determines the accuracy of the arbiter. In order to improve the accuracy of the arbiter, a MOS transistor is added between the arbiter nodes C1 and D1.

Fig. 9 is a serial output circuit as used herein. The serial output circuit stores the outputs of the arbiters in the CTDC and the FTDC after the FTDC quantization is finished, and outputs data under the trigger of a specified clock. The circuit adopts a TSPC register, and two MOS tubes M1 and M2 are added to the circuit for sampling the result of the arbiter. The register input port J is connected to the output of the arbiter, and the input port T is connected to the FTDC quantization end flag signal R _ SIG. When the flag signal R _ SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R _ SIG is equal to one, the register serially outputs data triggered by the clock CLK. The signal TC is generated by the signal R _ SIG.

The above description is only for the best embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are all covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A differentially sampled residual time sampling circuit, comprising: the device comprises an arbiter based on a sense amplifier, a buffer and a phase inverter formed by connecting four MOS tubes in series, wherein a CTDC output signal and a Stop signal are input into the input of the arbiter based on the sense amplifier for comparison, and the arbiter outputs opposite signals Q and P with symmetry as switching control signals of the phase inverter formed by the four MOS tubes, wherein the Q end of the output of the arbiter is connected to the grid electrodes of an NMOS tube N1 and a PMOS tube P2 of the phase inverter, and the P end of the output of the arbiter is connected to the grid electrode of another PMOS tube P1; the gate of another NMOS transistor N2 In the inverter is connected to the signal In, N ═ 1,2.. 16 through a buffer unit with a delay t; the residual time sampling circuit adopts a symmetrical structure, and the circuit is ensured to introduce the same error in the sampling process of the coarse quantization TDC output signal and the Stop signal.

2. A gated ring oscillator based time-to-digital converter designed using the residual time sampling circuit of claim 1, comprising CTDC, FTDC, a residual time sampling circuit, a thermometer code/binary code conversion circuit, a serial output circuit, a voltage controlled phase locked loop circuit, an end signal generation circuit;

the voltage-controlled phase-locked loop circuit generates a voltage Vc to control all voltage-controlled delay units in the CTDC; the output end of the CTDC is respectively connected to the thermometer code/binary code conversion circuit, the residual time sampling circuit and the serial output circuit; the residual time sampling circuit transmits the time margin after the CTDC quantization to the FTDC; the output end of the FTDC is respectively connected to the thermometer code/binary code conversion circuit, the serial output circuit and the end signal generation circuit, wherein the end signal generation circuit generates an end signal by judging the output signal of the arbiter in the FTDC, and the end signal generation circuit instructs the thermometer code/binary code conversion circuit and the serial output circuit to read the results of the arbiters in the CTDC and the FTDC for conversion and output.

3. A time-to-digital converter as claimed in claim 2, comprising: a voltage-controlled delay chain is adopted as a high-section TDC structure, wherein the delay of a delay unit in the voltage-controlled delay chain is controlled and adjusted by the output voltage Vc of a voltage-controlled phase-locked loop, and a low-section TDC adopts a vernier caliper type ring oscillator structure, is added into a counter, and simultaneously feeds back an end signal to an enabling signal generating circuit.

4. A time-to-digital converter as claimed in claim 2, characterized in that a buffer unit consisting of the simplest inverter is added after the delay unit of the CTDC and delay locked loop circuit, and connected to the respective load through the output of the buffer unit.

5. A time-to-digital converter as claimed in claim 2, wherein the CTDC comprises: a fast ring oscillator, a rising edge arbiter, a falling edge arbiter, a slow ring oscillator, and a four bit counter; the output of each delay unit in the fast ring oscillator and the slow ring oscillator is connected to the corresponding rising edge arbiter and the falling edge arbiter; the output of the first delay unit of the slow ring oscillator is used as a clock signal of the four-bit counter, and the oscillation period of the slow ring oscillator is the period of the trigger clock of the four-bit counter.

6. A time-to-digital converter as claimed in claim 2, characterized in that the rising edge arbiter is implemented by adding two PMOS transistors to the sense amplifier based arbiter, the sources of both transistors are connected to the supply voltage, the drains are connected to the input terminals of two symmetrical output inverters respectively, and the gates are connected to the reset signal EVEN _ R; an NMOS tube is respectively added between the input ends of two symmetrical output buffers in the falling edge arbiter and the ground, and the gates of the NMOS tubes are connected to a reset signal ODD _ R.

7. A time-to-digital converter as claimed in claim 2, characterized in that the serial output circuit employs a TSPC register, and two MOS transistors M1 and M2 are added therein for sampling the result of the arbiter; the input port J of the register is connected to the output of the arbiter, and the input port T is connected to an FTDC quantization end flag signal R _ SIG; when the flag signal R _ SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R _ SIG is equal to one, the register serially outputs data triggered by the clock CLK, and the signal TC is generated by the signal R _ SIG.