CN114047682A - Time-to-digital converter with PVT robustness based on fully differential ring oscillator - Google Patents
Time-to-digital converter with PVT robustness based on fully differential ring oscillator Download PDFInfo
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- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- H—ELECTRICITY
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Abstract
The invention discloses a time-to-digital converter with PVT robustness based on a fully differential ring oscillator, which relates to a time-to-digital converter, and provides a scheme aiming at the contradiction that the uncertainty of the process and the change of the PVT robustness seriously restrict the practical production application of a TDC, and a front-end module, a global control module, a delay unit and a decoding module which are electrically connected in sequence; and a delay calibration module is respectively connected with the delay unit and the decoding module and used for calibrating the delay of the delay unit, wherein the delay unit is a fully differential ring oscillator module. The method has the advantages that high precision and dynamic range can be achieved simultaneously, and PVT robustness tolerance and linearity of the TDC are improved through a simple and convenient calibration mode.
Description
Technical Field
The invention relates to a time-to-digital converter, in particular to a time-to-digital converter based on a fully differential ring oscillator with PVT robustness.
Background
In recent years, the development of the adpll technology has been fast, and a Time Digital Converter (TDC) is regarded as one of the key modules. The digital phase-locked loop based on the TDC has the characteristics of high integration level, easy calibration and programmability, and along with the evolution of process nodes, the all-digital phase-locked loop also has the advantages in terms of area and performance. The traditional charge pump phase-locked loop structure comprises a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a frequency divider and other modules, wherein passive devices such as capacitors and resistors contained in the charge pump and the loop filter deteriorate the phase noise performance of the phase-locked loop besides the consumed area. In a novel all-digital phase-locked loop, a TDC is used for replacing a phase frequency detector and a charge pump, phase information is directly processed on a time domain, and further processed through an on-chip digital filter. Due to the programmability of the digital filter, the loop dynamics of the digital pll can be changed in real time, thereby maintaining low phase noise while achieving fast lock. Furthermore, the area of the digital phase locked loop will be greatly reduced due to the elimination of the large capacitors used in the analog filter. However, the TDC has the same problem of limited accuracy as the conventional digital-to-analog converter, and the introduced quantization noise determines the in-band noise of the adpll. Besides the precision requirement, the measurement range of the TDC also needs to cover a complete input reference clock period, so that the problem of losing the lock of the digital phase-locked loop is avoided. In addition, the practical production application of the TDC is severely restricted by the uncertainty of the process and the variation of the PVT robustness, and the main reason is that the measurement accuracy of the ordinary TDC is determined by the delay time of the delay unit, and the delay time varies with the variation of the process angle, the voltage and the temperature.
The chain-type TDC of the inverter is simple to realize, has a large measurement range, and is limited by process nodes. The vernier chain type TDC has higher precision, but usually sacrifices indexes such as area and power consumption in order to increase the measurement range. The two-step TDC is a combination of an inverter chain type TDC and a vernier type TDC, and has high precision and a large measurement range, but does not have PVT (pyramid Vision Transformer) robustness. The vernier ring type TDC theoretically can provide infinite accuracy and a measurement range, and a measurement result consists of absolute delay and relative delay of two ring oscillators, so that the performances such as linearity and accuracy are influenced by the two aspects. In addition, because the ring oscillator is often composed of odd-level inverters, layout design work is difficult, and the difference between front and rear imitation performances is large.
Disclosure of Invention
The present invention aims to provide a time-to-digital converter based on a fully differential ring oscillator with PVT robustness to solve the above-mentioned problems of the prior art.
The invention relates to a time-to-digital converter with PVT robustness based on a fully differential ring oscillator, which comprises a front-end module, a global control module, a delay unit and a decoding module which are electrically connected in sequence; a delay calibration module is respectively connected with the delay unit and the decoding module and used for calibrating the delay of the delay unit;
the delay unit is a fully differential ring oscillator module.
The fully-differential ring oscillator module includes,
four fully differential inverters which are connected end to form a slow ring;
the other four fully differential inverters are connected end to form a fast ring; and the number of the first and second groups,
and the four-edge SR flip-flop is used for collecting and comparing the node signals in the slow loop and the fast loop to lead or lag.
The four fully-differential inverters forming the slow ring are respectively a first fully-differential inverter, a second fully-differential inverter, a third fully-differential inverter and a fourth fully-differential inverter: the in-phase output end of the first fully differential inverter is connected with the inverting input end of the second fully differential inverter, and the inverting output end of the first fully differential inverter is connected with the in-phase input end of the second fully differential inverter; the in-phase output end of the second fully differential inverter is connected with the inverting input end of the third fully differential inverter, and the inverting output end of the second fully differential inverter is connected with the in-phase input end of the third fully differential inverter; the in-phase output end of the third fully differential inverter is connected with the inverting input end of the fourth fully differential inverter, and the inverting output end of the third fully differential inverter is connected with the in-phase input end of the fourth fully differential inverter; the in-phase output end of the fourth fully differential inverter is connected with the in-phase input end of the first fully differential inverter, and the reverse-phase output end of the fourth fully differential inverter is connected with the reverse-phase input end of the first fully differential inverter;
the four fully-differential inverters forming the fast ring are respectively a fifth fully-differential inverter, a sixth fully-differential inverter, a seventh fully-differential inverter and an eighth fully-differential inverter: the in-phase output end of the fifth fully differential inverter is connected with the inverting input end of the sixth fully differential inverter, and the inverting output end of the fifth fully differential inverter is connected with the in-phase input end of the sixth fully differential inverter; the in-phase output end of the sixth fully differential inverter is connected with the inverting input end of the seventh fully differential inverter, and the inverting output end of the sixth fully differential inverter is connected with the in-phase input end of the seventh fully differential inverter; the in-phase output end of the seventh fully differential inverter is connected with the inverting input end of the eighth fully differential inverter, and the inverting output end of the seventh fully differential inverter is connected with the in-phase input end of the eighth fully differential inverter; the in-phase output end of the eighth fully differential inverter is connected with the in-phase input end of the fifth fully differential inverter, and the reverse-phase output end of the eighth fully differential inverter is connected with the reverse-phase input end of the fifth fully differential inverter;
the four edge SR flip-flops are respectively a first edge SR flip-flop, a second edge SR flip-flop, a third edge SR flip-flop, and a fourth edge SR flip-flop: the slow loop input end of the first edge SR trigger is connected with the inverted output end of the first fully-differential inverter, the fast loop input end of the first edge SR trigger is connected with the inverted output end of the fifth fully-differential inverter, and the reset end RST _ E of the first edge SR trigger is connected with the inverted output end of the third fully-differential inverter; the slow loop input end of the second edge SR trigger is connected with the in-phase output end of the first fully-differential phase inverter, the fast loop input end of the second edge SR trigger is connected with the in-phase output end of the fifth fully-differential phase inverter, and the reset end RST _ E of the second edge SR trigger is connected with the in-phase output end of the third fully-differential phase inverter; the slow loop input end of the third edge SR trigger is connected with the inverted output end of the third fully differential inverter, the fast loop input end of the third edge SR trigger is connected with the inverted output end of the seventh fully differential inverter, and the reset end RST _ E of the third edge SR trigger is connected with the in-phase output end of the first fully differential inverter; the slow loop input end of the fourth edge SR trigger is connected with the in-phase output end of the third fully-differential phase inverter, the fast loop input end of the fourth edge SR trigger is connected with the in-phase output end of the seventh fully-differential phase inverter, and the reset end RST _ E of the fourth edge SR trigger is connected with the anti-phase output end of the first fully-differential phase inverter; the first edge SR trigger, the second edge SR trigger, the third edge SR trigger and the fourth edge SR trigger have respective reset terminals RST _ I connected to an external global reset signal RST, and have respective output terminals connected to the decoding module.
The four edge SR triggers have the same structure, and each edge SR trigger mainly comprises three buffer modules, three rising edge detection modules, four PMOS transistors and six NMOS transistors;
the source electrode of the fifth PMOS transistor and the source electrode of the sixth PMOS transistor are connected with VDD in a point-sharing mode;
the grid of the fifth PMOS transistor is arranged in front of the first rising edge detection module and then is used as the input end of the fast loop, and the grid of the sixth PMOS transistor is arranged in front of the second rising edge detection module and then is used as the input end of the fast loop and the slow loop;
the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, and the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor;
the drain electrode of the seventh PMOS transistor, the gate electrode of the eighth PMOS transistor, the drain electrode of the ninth NMOS transistor, the drain electrode of the eleventh NMOS transistor, the gate electrode of the eighth NMOS transistor, the drain electrode of the seventh NMOS transistor and the input of the first buffer module are in common, and the output end QB of the first buffer module is suspended;
the drain electrode of the eighth PMOS transistor, the gate electrode of the seventh PMOS transistor, the drain electrode of the twelfth NMOS transistor, the drain electrode of the tenth NMOS transistor, the gate electrode of the seventh NMOS transistor, the drain electrode of the eighth NMOS transistor and the input end of the second buffer module are in the same point, and the output end Q of the second buffer module is connected to the decoding module;
the grid electrode of the ninth NMOS transistor and the grid electrode of the tenth NMOS transistor are connected to the input end of the third buffer module in a concurrent mode, the output end of the third buffer module is connected with the reset end RST _ I, and the RST _ I is externally connected with the global reset end RST; a third rising edge detection module is arranged in front of the eleventh NMOS transistor after the grid electrodes of the eleventh NMOS transistor and the twelfth NMOS transistor are in a common point mode and serves as a reset terminal RST _ E;
and the sources of the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are connected with VSS at the same point.
The four fully-differential inverters forming the slow ring and the other four fully-differential inverters forming the fast ring have the same structure, and each fully-differential inverter mainly comprises two inverters, four PMOS transistors, six NMOS transistors and two capacitor arrays;
the source electrode of the third PMOS transistor is connected with VDD, the grid electrode of the third PMOS transistor is connected with the output end of the first inverter, and the drain electrode of the third PMOS transistor is respectively connected with the source electrodes of the first PMOS transistor and the second PMOS transistor;
the input end of the first inverter is used as the enabling end of the fully differential inverter;
the common point of the grid of the first PMOS transistor and the grid of the first NMOS transistor is used as a non-inverting input end, and the common point of the grids of the second PMOS transistor and the second NMOS transistor is used as an inverting input end;
the drain electrode of the first PMOS transistor, the drain electrode of the sixth NMOS transistor, the drain electrode of the first NMOS transistor, the drain electrode of the third NMOS transistor, the grid electrode of the fourth NMOS transistor and the upper polar plate of the first capacitor array are in the same point to serve as an inverted output end;
the drain electrode of the second PMOS transistor, the drain electrode of the fourth PMOS transistor, the drain electrode of the second NMOS transistor, the drain electrode of the fourth NMOS transistor, the grid electrode of the third NMOS transistor and the upper polar plate of the second capacitor array are in the same point as the in-phase output end;
the source electrode of the sixth NMOS transistor is connected with VSS, and the grid electrode of the sixth NMOS transistor is connected with the output end of the first inverter; the source electrode of the fourth PMOS transistor is connected with VDD, and the grid electrode of the fourth PMOS transistor is connected with the output end of the second inverter; the lower pole plates of the first capacitor array and the second capacitor array are respectively connected with VSS;
the source electrodes of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are connected with the drain electrode of the fifth NMOS transistor after being in a point-sharing mode;
the source electrode of the fifth NMOS transistor is connected with VSS, and the grid electrode of the fifth NMOS transistor is connected with the output end of the second inverter;
the input end of the second inverter is connected with the output end of the first inverter.
The time-to-digital converter with the PVT robustness and based on the fully differential ring oscillator has the advantages that high precision and dynamic range can be achieved simultaneously, and the PVT robustness tolerance and linearity of the TDC are improved through a simple and convenient calibration mode.
Drawings
FIG. 1 is a schematic diagram of a time-to-digital converter according to the present invention;
FIG. 2 is a circuit schematic of the fully differential ring oscillator of the present invention;
FIG. 3 is a circuit schematic of the edge SR flip-flop of the present invention;
fig. 4 is a circuit schematic of the fully differential inverter of the present invention.
Reference numerals:
FDINV1 to FDINV 8: first to eighth fully-differential inverters;
ARB1 to ARB 4: a first edge SR flip-flop to a fourth edge SR flip-flop;
RUD 1-RUD 3: a first rising edge detection module to a third rising edge detection module;
BUF1 to BUF 3: first to third buffer modules;
INV 1-first inverter, INV 2-second inverter;
MP1 to MP 8: first to eighth PMOS transistors;
MN1 to MN 12: first to twelfth NMOS transistors;
CDAC 1-first capacitor array, CDAC 2-second capacitor array;
von-inverting output terminal, Vop-non-inverting output terminal.
Detailed Description
As shown in fig. 1, the time-to-digital converter with PVT robustness based on a fully differential ring oscillator according to the present invention includes a front-end module, a global control module, a delay unit and a decoding module, which are electrically connected in sequence; and a delay calibration module is also arranged to be respectively connected with the delay unit and the decoding module, wherein the delay unit is of a fully differential ring oscillator module.
Two inputs of the front-end module are connected with a clock REF and a frequency divider output clock DIV, the phases of two clock signals are judged, two corresponding outputs are generated, namely a fast signal LEAD _ PUS and a slow signal LAG _ PUS, and the most significant bit MSB of the TDC and a global reset signal RST are simultaneously output. The front-end module judges the arrival speeds of two clocks, if the clock REF arrives first, the clock REF is sent to a fast signal LEAD _ PUS output, the clock LAG is sent to a slow signal LAG _ PUS output, and the MSB of the highest bit is changed into 1; if clock DIV arrives first, clock REF is sent to the output of LAG _ PUS, clock DIV is sent to the output of LEAD _ PUS, and MSB of the most significant bit is changed to 0.
The global control module has two working modes, wherein the global control module works in the first mode when a signal CAL _ EN is 0, and works in the second mode when the signal CAL _ EN is 1. The first mode is used for receiving a fast signal LEAD _ PUS and a slow signal LAG _ PUS, respectively converting the fast signal LEAD _ PUS and the slow signal LAG _ PUS into a fast signal LEAD _ PUS and a slow signal LAG _ PUS with certain pulse widths according to a signal STOP, and controlling the operation and the turn-off of a fully differential ring oscillator module; and the second mode is used for receiving the calibration signal CAL _ EN, converting the period of the clock into two fast signals LEAD _ PUS and slow signals LAG _ PUS with corresponding intervals, and further completing the delay calibration of the fully differential ring oscillator module through the cooperative coordination of the delay calibration module. When receiving a global reset signal RST of 1, the global control module resets and waits for the arrival of the next pair of LEAD _ PUS and LAG _ PUS. When the received signal STOP is 1, the fast signal LEAD _ PUS and the slow signal LAG _ PUS are simultaneously changed from 1 to 0, and simultaneously generate a falling edge for turning off the fully differential ring oscillator module of the next stage so as to avoid generating power consumption continuously.
The fully differential ring oscillator module sends the received fast signal LEAD _ PUS to the slow ring, and the slow ring starts to oscillate; and sending the later received slow signal LAG _ PUS to the fast loop, wherein the fast loop also starts to oscillate, and simultaneously starts to catch up with the slow loop. The number of turns of the two loops and the specific positions caught up are output to the next-stage decoding module through the SLAP end, the FLAP end and the Q end.
The decoding module comprises two 3-bit counters, a thermometer code parser and a digital logic unit. The digital logic unit is used for synthesizing and converting the outputs of the counter and the thermometer code resolver into an output signal D of the TDC and generating a signal STOP.
The delay calibration module is a digital circuit, the input of the delay calibration module is connected to an output signal D of the time-to-digital converter, and the two outputs of the delay calibration module are respectively connected to a CFGS end and a CFGF end of the fully differential ring oscillator module and used for adjusting the delay time of the delay units in the slow ring and the fast ring. And in the calibration stage, directly reading the corresponding digital output signal D, comparing the digital output signal D with a preset numerical value, setting a CFGF end and a CFGS end according to SAR logic successive approximation, and further adjusting the precision of the time-to-digital converter.
As shown in fig. 2, the fully differential ring oscillator module includes: four full-differential inverters on the periphery and four other full-differential inverters on the inner periphery, and four edge SR triggers for collecting and comparing node signals in the slow ring and the fast ring to lead or lag behind the signals between the slow ring and the fast ring. The four peripheral fully differential inverters are connected end to form a Slow Ring (SR), and the four peripheral fully differential inverters are connected end to form a Fast Ring (FR).
The four fully differential inverters constituting the slow loop are a first fully differential inverter FDINV1, a second fully differential inverter FDINV2, a third fully differential inverter FDINV3 and a fourth fully differential inverter FDINV4, respectively: the non-inverting output end of the first fully differential inverter FDINV1 is connected with the inverting input end of the second fully differential inverter FDINV2, and the inverting output end of the first fully differential inverter FDINV1 is connected with the non-inverting input end of the second fully differential inverter FDINV 2; the non-inverting output end of the second fully differential inverter FDINV2 is connected with the inverting input end of a third fully differential inverter FDINV3, and the inverting output end of the second fully differential inverter FDINV2 is connected with the non-inverting input end of a third fully differential inverter FDINV 3; the non-inverting output end of the third fully differential inverter FDINV3 is connected with the inverting input end of the fourth fully differential inverter FDINV4, and the inverting output end of the third fully differential inverter FDINV3 is connected with the non-inverting input end of the fourth fully differential inverter FDINV 4; the non-inverting output end of the fourth fully differential inverter FDINV4 is connected with the non-inverting input end of the first fully differential inverter FDINV1, and the inverting output end of the fourth fully differential inverter FDINV4 is connected with the inverting input end of the first fully differential inverter FDINV 1.
The four fully differential inverters constituting the fast loop are a fifth fully differential inverter FDINV5, a sixth fully differential inverter FDINV6, a seventh fully differential inverter FDINV7 and an eighth fully differential inverter FDINV8, respectively: the non-inverting output end of the fifth fully differential inverter FDINV5 is connected with the inverting input end of the sixth fully differential inverter FDINV6, and the inverting output end of the fifth fully differential inverter FDINV5 is connected with the non-inverting input end of the sixth fully differential inverter FDINV 6; the non-inverting output end of the sixth fully differential inverter FDINV6 is connected with the inverting input end of the seventh fully differential inverter FDINV7, and the inverting output end of the sixth fully differential inverter FDINV6 is connected with the non-inverting input end of the seventh fully differential inverter FDINV 7; the non-inverting output end of the seventh fully differential inverter FDINV7 is connected with the inverting input end of the eighth fully differential inverter FDINV8, and the inverting output end of the seventh fully differential inverter FDINV7 is connected with the non-inverting input end of the eighth fully differential inverter FDINV 8; the non-inverting output end of the eighth fully differential inverter FDINV8 is connected with the non-inverting input end of the fifth fully differential inverter FDINV5, and the inverting output end of the eighth fully differential inverter FDINV8 is connected with the inverting input end of the fifth fully differential inverter FDINV 5.
The four edge SR flip-flops are a first edge SR flip-flop ARB1, a second edge SR flip-flop ARB2, a third edge SR flip-flop ARB3, and a fourth edge SR flip-flop ARB 4: the slow loop input end of the first edge SR flip-flop ARB1 is connected with the inverted output end of the first fully differential inverter FDINV1, the fast loop input end of the first edge SR flip-flop ARB1 is connected with the inverted output end of the fifth fully differential inverter FDINV5, and the reset end RST _ E of the first edge SR flip-flop ARB1 is connected with the inverted output end of the third fully differential inverter FDINV 3; the slow loop input end of the second edge SR flip-flop ARB2 is connected with the in-phase output end of the first fully differential inverter FDINV1, the fast loop input end of the second edge SR flip-flop ARB2 is connected with the in-phase output end of the fifth fully differential inverter FDINV5, and the reset end RST _ E of the second edge SR flip-flop ARB2 is connected with the in-phase output end of the third fully differential inverter FDINV 3; the slow ring input end of the third edge SR flip-flop ARB3 is connected with the inverted output end of the third fully differential inverter FDINV3, the fast ring input end of the third edge SR flip-flop ARB3 is connected with the inverted output end of the seventh fully differential inverter FDINV7, and the reset end RST _ E of the third edge SR flip-flop ARB3 is connected with the non-inverted output end of the first fully differential inverter FDINV 1; the slow ring input end of the fourth edge SR flip-flop ARB4 is connected with the in-phase output end of the third fully differential inverter FDINV3, the fast ring input end of the fourth edge SR flip-flop ARB4 is connected with the in-phase output end of the seventh fully differential inverter FDINV7, and the reset end RST _ E of the fourth edge SR flip-flop ARB4 is connected with the inverted output end of the first fully differential inverter FDINV 1; the reset ends RST _ I of the first edge SR flip-flop ARB1, the second edge SR flip-flop ARB2, the third edge SR flip-flop ARB3 and the fourth edge SR flip-flop ARB4 are all connected to an external global reset signal RST, and the output ends of the first edge SR flip-flop ARB, the second edge SR flip-flop ARB2 and the fourth edge SR flip-flop ARB4 are respectively connected to the decoding module.
In the initial stage, the first-stage inverters of the two rings work in a preset state of enabling invalidation, and the other three stages work in a state of enabling validation. When the fast signal LEAD _ PUS arrives, the slow loop starts to oscillate, and the fast signal LEAD _ PUS is transmitted along the slow loop; when the slow signal LAG _ PUS arrives, the fast loop also starts to oscillate, the slow signal LAG _ PUS is transmitted along the fast loop, and starts to catch up with the fast signal LEAD _ PUS in the slow loop. Meanwhile, the 4 edge SR triggers are used for judging the arrival sequence of the fast signal LEAD _ PUS and the slow signal LAG _ PUS at the same node, if the slow signal LAG _ PUS at the FN <0> end arrives earlier than the fast signal LEAD _ PUS at the SN <0> end, the output of the edge SR trigger is 1, otherwise, the output is 0.
Compared with the traditional sampling mode using D flip-flop, the following advantages are obtained by using the edge SR flip-flop: the D flip-flop compares the speed of two signals through a clock end CLK and a data end D, but the structures of the clock end CLK and the data end D are asymmetric, so that an offset influenced by PVT exists, and the edge SR flip-flop has a strictly symmetric structure and a smaller offset; in addition, the sampling of the D trigger needs to be processed in a case 010 and a case 10, so that the following digital processing circuit is more complex and redundant, and the sampling of two rings by the edge SR trigger only has the case 10, so that the subsequent design work and difficulty are reduced. Because the slow loop is used as a reference to judge the arrival speed of the fast signal LEAD _ PUS and the slow signal LAG _ PUS, the reset of the edge SR trigger is given by the output node of the slow loop, and the reset of the next-stage edge SR trigger is given by the node of the previous-stage slow loop.
As shown in fig. 3, the four edge SR flip-flops have the same structure, and each edge SR flip-flop mainly includes three rising edge detection modules, four PMOS transistors, and six NMOS transistors. On the basis of matching with a fully differential ring oscillator, the time-to-digital converter can realize the grabbing of the position on a signal transmission path only by using the SR triggers with four edges, so that the complexity of the whole design is reduced.
The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected to VDD at the same point; the gate of the fifth PMOS transistor MP5 is preceded by the first rising edge detection module RUD1 and then serves as the slow-loop input terminal, and the gate of the sixth PMOS transistor MP6 is preceded by the second rising edge detection module RUD2 and then serves as the fast-loop input terminal.
The drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7, and the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP 8.
The drain electrode of the seventh PMOS transistor MP7, the gate electrode of the eighth PMOS transistor MP8, the drain electrode of the ninth NMOS transistor MN9, the drain electrode of the eleventh NMOS transistor MN11, the gate electrode of the eighth NMOS transistor MN8, the drain electrode of the seventh NMOS transistor MN7, and the input of the first buffer module (BUF1) are in common, and the output terminal QB of the first buffer module (BUF1) is floating;
the drain electrode of the eighth PMOS transistor MP8, the gate electrode of the seventh PMOS transistor MP7, the drain electrode of the twelfth NMOS transistor MN12, the drain electrode of the tenth NMOS transistor MN10, the gate electrode of the seventh NMOS transistor MN7, the drain electrode of the eighth NMOS transistor MN8 and the input end of the second buffer module BUF2 are in a point-sharing relationship, and the output end Q of the second buffer module BUF2 is connected to the decoding module;
the grid electrode common point of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 is connected to the input end of the third buffer module BUF3, the output end of the third buffer module is connected with a reset end RST _ I, and the RST _ I is externally connected with a global reset end RST; the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 have their gates connected in common and then preceded by a third rising edge detection module RUD3 as a reset terminal RST _ E;
the sources of the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the first NMOS transistor MN1 and the twelfth NMOS transistor MN12 are connected with VSS in a common point.
In the initial stage, the reset terminal RST _ I is 1, the Q terminal and the QB terminal are both discharged to 0 through the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10, and the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are turned on in advance. The reset terminal RST _ I becomes 0 after the reset is completed. If the S terminal detects the rising edge first, a short negative pulse is generated by the second rising edge detection module RUD2, the sixth PMOS transistor MP6 is turned on, the Q terminal is charged to a high level, the seventh NMOS transistor MN7 is turned on, and the QB terminal is further discharged to a low level. On the other hand, if the R terminal detects a rising edge first, the Q terminal becomes 0. The other reset terminal RST _ E is used for local reset, and when the third rising edge detection module RUD3 detects the rising edge of the reset terminal RST _ E, a short positive pulse is generated at the output, so as to turn on the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 for reset.
As shown in fig. 4, the four fully-differential inverters constituting the slow ring and the other four fully-differential inverters constituting the fast ring have the same structure, and each fully-differential inverter mainly includes two inverters, four PMOS transistors, six NMOS transistors, and two capacitor arrays.
The source of the third PMOS transistor MP3 is connected to VDD, the gate is connected to the output terminal of the first inverter INV1, and the drain is connected to the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2, respectively.
The input end of the first inverter INV1 is used as the enable end of the fully differential inverter; an output end of the first inverter INV1 is connected to an input end of the second inverter INV 2. The gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are at the same point as a non-inverting input terminal, and the gate of the second PMOS transistor MP2 and the gate of the second NMOS transistor MN2 are at the same point as an inverting input terminal.
The drain electrode of the first PMOS transistor MP1, the drain electrode of the sixth NMOS transistor MN6, the drain electrode of the first NMOS transistor MN1, the drain electrode of the third NMOS transistor MN3, the gate electrode of the fourth NMOS transistor MN4 and the upper plate electrode of the first capacitor array CDAC1 are in a point-sharing connection to serve as an inverting output end.
The drain of the second PMOS transistor MP2, the drain of the fourth PMOS transistor MP4, the drain of the second NMOS transistor MN2, the drain of the fourth NMOS transistor MN4, the gate of the third NMOS transistor MN3 and the upper plate of the second capacitor array CDAC2 are in common as the non-inverting output terminal.
The source of the sixth NMOS transistor MN6 is connected to VSS, and the gate is connected to the output end of the first inverter INV 1; the source of the fourth PMOS transistor MP4 is connected to VDD, and the gate is connected to the output end of the second inverter INV 2; the lower plates of the first capacitor array CDAC1 and the second capacitor array CDAC2 are respectively connected with VSS.
The sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected with the drain of the fifth NMOS transistor MN5 after being in a point-sharing mode.
The source of the fifth NMOS transistor MN5 is connected to VSS, and the gate is connected to the output end of the second inverter INV 2.
EN has two states, which are set at 0 and 1, respectively. When EN is 0, the third PMOS transistor MP3 and the fifth NMOS transistor MN5 are both turned off, the sixth NMOS transistor MN6 and the fourth PMOS transistor MP4 are turned on, Von is discharged to a low level, and Vop is charged to a high level; when EN is 1, the third PMOS transistor MP3 and the fifth NMOS transistor MN5 are turned on, the inverter operates normally, and further, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 accelerate the transition of the output state by a positive feedback action. The first capacitor array CDAC1 and the second capacitor array CDAC2 which are arranged at the output are used for adjusting the delay of the inverter, the purpose is to calibrate the delay time in the calibration stage, the influence of PVT robustness on the delay of the inverter is overcome, the precision of the TDC is improved, and compared with the existing time TDC, the PVT robustness resistance is better.
It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.
Claims (5)
1. A time-to-digital converter with PVT robustness based on a fully differential ring oscillator comprises a front-end module, a global control module, a delay unit and a decoding module which are electrically connected in sequence; a delay calibration module is respectively connected with the delay unit and the decoding module and used for calibrating the delay of the delay unit;
it is characterized in that the preparation method is characterized in that,
the delay unit is a fully differential ring oscillator module.
2. The PVT robust fully differential ring oscillator based time-to-digital converter of claim 1, wherein said fully differential ring oscillator module comprises,
four fully differential inverters which are connected end to form a slow ring;
the other four fully differential inverters are connected end to form a fast ring;
and the number of the first and second groups,
and the four-edge SR flip-flop is used for collecting and comparing the node signals in the slow loop and the fast loop to lead or lag.
3. The PVT robust fully differential ring oscillator based time-to-digital converter of claim 2,
the four fully differential inverters constituting the slow loop are a first fully differential inverter (FDINV1), a second fully differential inverter (FDINV2), a third fully differential inverter (FDINV3), and a fourth fully differential inverter (FDINV4), respectively: the non-inverting output end of the first fully differential inverter (FDINV1) is connected with the inverting input end of the second fully differential inverter (FDINV2), and the inverting output end of the first fully differential inverter (FDINV1) is connected with the non-inverting input end of the second fully differential inverter (FDINV 2); the non-inverting output end of the second fully differential inverter (FDINV2) is connected with the inverting input end of a third fully differential inverter (FDINV3), and the inverting output end of the second fully differential inverter (FDINV2) is connected with the non-inverting input end of a third fully differential inverter (FDINV 3); the non-inverting output end of the third fully differential inverter (FDINV3) is connected with the inverting input end of the fourth fully differential inverter (FDINV4), and the inverting output end of the third fully differential inverter (FDINV3) is connected with the non-inverting input end of the fourth fully differential inverter (FDINV 4); the non-inverting output end of the fourth fully differential inverter (FDINV4) is connected with the non-inverting input end of the first fully differential inverter (FDINV1), and the inverting output end of the fourth fully differential inverter (FDINV4) is connected with the inverting input end of the first fully differential inverter (FDINV 1);
the four fully differential inverters constituting the fast loop are a fifth fully differential inverter (FDINV5), a sixth fully differential inverter (FDINV6), a seventh fully differential inverter (FDINV7), and an eighth fully differential inverter (FDINV8), respectively: the non-inverting output end of the fifth fully differential inverter (FDINV5) is connected with the inverting input end of the sixth fully differential inverter (FDINV6), and the inverting output end of the fifth fully differential inverter (FDINV5) is connected with the non-inverting input end of the sixth fully differential inverter (FDINV 6); the non-inverting output end of the sixth fully differential inverter (FDINV6) is connected with the inverting input end of the seventh fully differential inverter (FDINV7), and the inverting output end of the sixth fully differential inverter (FDINV6) is connected with the non-inverting input end of the seventh fully differential inverter (FDINV 7); the non-inverting output end of the seventh fully differential inverter (FDINV7) is connected with the inverting input end of the eighth fully differential inverter (FDINV8), and the inverting output end of the seventh fully differential inverter (FDINV7) is connected with the non-inverting input end of the eighth fully differential inverter (FDINV 8); the non-inverting output end of the eighth fully differential inverter (FDINV8) is connected with the non-inverting input end of the fifth fully differential inverter (FDINV5), and the inverting output end of the eighth fully differential inverter (FDINV8) is connected with the inverting input end of the fifth fully differential inverter (FDINV 5);
the four edge SR flip-flops are a first edge SR flip-flop (ARB1), a second edge SR flip-flop (ARB2), a third edge SR flip-flop (ARB3), and a fourth edge SR flip-flop (ARB4), respectively: the slow ring input end of the first edge SR flip-flop (ARB1) is connected with the inverted output end of the first fully differential inverter (FDINV1), the fast ring input end of the first edge SR flip-flop (ARB1) is connected with the inverted output end of the fifth fully differential inverter (FDINV5), and the reset end RST _ E of the first edge SR flip-flop (ARB1) is connected with the inverted output end of the third fully differential inverter (FDINV 3); the slow ring input end of the second edge SR flip-flop (ARB2) is connected with the in-phase output end of the first fully differential inverter (FDINV1), the fast ring input end of the second edge SR flip-flop (ARB2) is connected with the in-phase output end of the fifth fully differential inverter (FDINV5), and the reset end RST _ E of the second edge SR flip-flop (ARB2) is connected with the in-phase output end of the third fully differential inverter (FDINV 3); the slow ring input end of the third edge SR flip-flop (ARB3) is connected with the inverted output end of the third fully differential inverter (FDINV3), the fast ring input end of the third edge SR flip-flop (ARB3) is connected with the inverted output end of the seventh fully differential inverter (FDINV7), and the reset end RST _ E of the third edge SR flip-flop (ARB3) is connected with the in-phase output end of the first fully differential inverter (FDINV 1); the slow ring input end of the fourth edge SR flip-flop (ARB4) is connected with the in-phase output end of the third fully differential inverter (FDINV3), the fast ring input end of the fourth edge SR flip-flop (ARB4) is connected with the in-phase output end of the seventh fully differential inverter (FDINV7), and the reset end RST _ E of the fourth edge SR flip-flop (ARB4) is connected with the inverted output end of the first fully differential inverter (FDINV 1); the reset ends RST _ I of the first edge SR flip-flop (ARB1), the second edge SR flip-flop (ARB2), the third edge SR flip-flop (ARB3) and the fourth edge SR flip-flop (ARB4) are all connected to an external global reset signal RST, and the output ends of the first edge SR flip-flop, the second edge SR flip-flop and the fourth edge SR flip-flop are respectively connected to the decoding module.
4. The PVT robustness fully differential ring oscillator based time-to-digital converter as recited in claim 3, wherein said four edge SR triggers are identical in structure, each edge SR trigger mainly comprises three buffer modules, three rising edge detection modules, four PMOS transistors and six NMOS transistors;
the source of the fifth PMOS transistor (MP5) and the source of the sixth PMOS transistor (MP6) are connected to VDD in common;
the grid of the fifth PMOS transistor (MP5) is arranged in front of the first rising edge detection module (RUD1) and then serves as a slow ring input end, and the grid of the sixth PMOS transistor (MP6) is arranged in front of the second rising edge detection module (RUD2) and then serves as a fast ring input end;
the drain of the fifth PMOS transistor (MP5) is connected to the source of the seventh PMOS transistor (MP7), and the drain of the sixth PMOS transistor (MP6) is connected to the source of the eighth PMOS transistor (MP 8);
the drain electrode of the seventh PMOS transistor (MP7), the gate electrode of the eighth PMOS transistor (MP8), the drain electrode of the ninth NMOS transistor (MN9), the drain electrode of the eleventh NMOS transistor (MN11), the gate electrode of the eighth NMOS transistor (MN8), the drain electrode of the seventh NMOS transistor (MN7) and the input of the first buffer module (BUF1) are in common, and the output end QB of the first buffer module (BUF1) is suspended;
the drain electrode of the eighth PMOS transistor (MP8), the gate electrode of the seventh PMOS transistor (MP7), the drain electrode of the twelfth NMOS transistor (MN12), the drain electrode of the tenth NMOS transistor (MN10), the gate electrode of the seventh NMOS transistor (MN7), the drain electrode of the eighth NMOS transistor (MN8) and the input end of the second buffer module (BUF2) are connected in common, and the output end Q of the second buffer module (BUF2) is connected to the decoding module;
the grid electrode of the ninth NMOS transistor (MN9) and the grid electrode of the tenth NMOS transistor (MN10) are connected to the input end of the third buffer module (BUF3) in a common point mode, the output end of the third buffer module is connected with the reset end RST _ I, and the RST _ I is externally connected with the global reset end RST; the eleventh NMOS transistor (MN11) and the twelfth NMOS transistor (MN12) are connected with the grid electrodes in common and then are preceded by a third rising edge detection module (RUD3) to serve as a reset terminal RST _ E;
the sources of the seventh NMOS transistor (MN7), the eighth NMOS transistor (MN8), the ninth NMOS transistor (MN9), the tenth NMOS transistor (MN10), the eleventh NMOS transistor (MN11), and the twelfth NMOS transistor (MN12) are connected to VSS in common.
5. The PVT robustness fully differential ring oscillator based time-to-digital converter as recited in claim 3, wherein four fully differential inverters constituting the slow ring and another four fully differential inverters constituting the fast ring are identical in structure, each fully differential inverter mainly consists of two inverters, four PMOS transistors, six NMOS transistors and two capacitor arrays;
the source electrode of the third PMOS transistor (MP3) is connected with VDD, the grid electrode of the third PMOS transistor (MP3) is connected with the output end of the first inverter (INV1), and the drain electrode of the third PMOS transistor (MP3) is respectively connected with the source electrodes of the first PMOS transistor (MP1) and the second PMOS transistor (MP 2);
the input end of the first inverter (INV1) is used as the enabling end of the fully differential inverter;
the gate of the first PMOS transistor (MP1) and the gate of the first NMOS transistor (MN1) are in the same point as a non-inverting input end, and the gate of the second PMOS transistor (MP2) and the gate of the second NMOS transistor (MN2) are in the same point as an inverting input end;
the drain electrode of the first PMOS transistor (MP1), the drain electrode of the sixth NMOS transistor (MN6), the drain electrode of the first NMOS transistor (MN1), the drain electrode of the third NMOS transistor (MN3), the gate electrode of the fourth NMOS transistor (MN4) and the upper plate electrode of the first capacitor array (CDAC1) are in the same point to serve as an inverting output end;
the drain of the second PMOS transistor (MP2), the drain of the fourth PMOS transistor (MP4), the drain of the second NMOS transistor (MN2), the drain of the fourth NMOS transistor (MN4), the gate of the third NMOS transistor (MN3) and the upper plate of the second capacitor array (CDAC2) are in the same point to serve as a non-inverting output end;
the source electrode of the sixth NMOS transistor (MN6) is connected with VSS, and the grid electrode of the sixth NMOS transistor is connected with the output end of the first inverter (INV 1); the source electrode of the fourth PMOS transistor (MP4) is connected with VDD, and the grid electrode of the fourth PMOS transistor is connected with the output end of the second inverter (INV 2); the lower plates of the first capacitor array (CDAC1) and the second capacitor array (CDAC2) are respectively connected with VSS;
the sources of the first NMOS transistor (MN1), the second NMOS transistor (MN2), the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are connected with the drain of the fifth NMOS transistor (MN5) after being in a point-sharing mode;
the source electrode of the fifth NMOS transistor (MN5) is connected with VSS, and the grid electrode of the fifth NMOS transistor is connected with the output end of the second inverter (INV 2);
the input end of the second inverter (INV2) is connected to the output end of the first inverter (INV 1).
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