CN110752846A

CN110752846A - Delay control circuit of asynchronous successive approximation analog-digital converter

Info

Publication number: CN110752846A
Application number: CN201911182338.2A
Authority: CN
Inventors: 郑锐
Original assignee: Canxin Semiconductor Suzhou Co Ltd
Current assignee: Canxin Semiconductor Suzhou Co Ltd
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2020-02-04

Abstract

The invention discloses a delay control circuit of an asynchronous successive approximation analog-digital converter, which comprises: the phase-locked loop correction circuit comprises a voltage-controlled oscillator and a delay chain circuit, and the phase-locked loop correction circuit provides a first control voltage of the voltage-controlled oscillator; the delay chain circuit includes: the delay chain is formed by cascading N stages of first delay units; the multiplexer is respectively connected with the output end of each first delay unit in the delay chain; the input end of the first buffer is connected with the first control voltage, and the output end of the first buffer is connected with each first delay unit; one end of the first capacitor is grounded, and the other end of the first capacitor is connected with the output end of the first buffer. The first control voltage generates a second control voltage for controlling the delay time of each first delay unit after passing through the first buffer and the first capacitor. The working speed of the ADC can be improved, the linearity and the signal-to-noise ratio of the ADC are improved, and the yield of mass production chips is increased.

Description

Delay control circuit of asynchronous successive approximation analog-digital converter

Technical Field

The invention relates to the field of data conversion integrated circuits, in particular to a delay control circuit of an asynchronous SAR-ADC (successive approximation analog-digital converter).

Background

The successive approximation analog-digital converter (SAR-ADC) has the characteristics of simple structure, low power consumption, small area, easiness in integration and the like, and is widely applied to the field of medium-precision (8-16 bits) and medium-speed (<150 Msps).

The clock control of the conventional SAR-ADC is a synchronous mode, namely, one clock is externally accessed, and each step of sampling, converting, storing and outputting in a chip is defined by the external clock. The accuracy of the external clock is matched to the sampling accuracy of the SAR-ADC. Besides the need to ensure the purity of the clock source, great care must be taken to the noise from the clock to each link inside the chip. In addition, the high clock frequency requires a strong driving capability of the logic gate in the chip, which means a large power consumption. For high-speed SAR-ADC, the speed of more than 100MS/s and the precision of more than 10 bits are achieved, and the adoption of synchronous control is very uneconomical and very difficult.

Asynchronous clocking is the most important system-level solution for SAR-ADC speed up in recent years. The SAR-ADC has some characteristics, such as high clock precision requirement of sampling, but almost no clock precision requirement of conversion, and just provides a space for exerting advantages for an asynchronous clock. The pulse required by the control circuit is generated by itself, and the asynchronous clock control abandons the frequency division operation of a synchronous clock, but adopts an external clock with the same sampling frequency to divide the clock into two stages of sampling and conversion. The system has no requirement on the edge of an operation clock during conversion, the conversion is made into asynchronous triggering, the comparator is used for triggering the SAR logic, and the SAR logic drives a digital-analog conversion Array (DAC Array) to complete N times of comparison. And finally outputting results of N data which are sequentially finished but not aligned with the clock in a synchronous mode.

The basic structure of an asynchronous SAR-ADC is shown in FIG. 2, where an external clock signal generates a sampling clock CLK via a clock generation circuit_sample. After sampling the input differential signals INP and INN by the sampling clock, comparing the input differential signals by a high-speed comparator, generating a Ready signal through exclusive OR, inputting the Ready signal to a high-speed digital circuit consisting of a multi-phase clock generator and successive approximation logic, on one hand, generating a clock signal to provide a comparison clock for the comparator through a delay chain, and on the other hand, controlling a switched capacitor Array (DAC Array) of the SAR-ADC through a DAC (digital-analog conversion) control circuit. The reference voltage of the DAC is generated by an external reference source (BG) through a reference voltage buffer (VREF BUF). Delay loop routing comparator, exclusive-or gate, multi-phase clock generation circuit and of whole asynchronous SAR-ADCAnd (4) forming a delay chain. Since the delays of the other circuits are substantially fixed, the adjustment of the delay chain delay time becomes the only controllable factor.

A conventional asynchronous SAR-ADC delay control circuit is shown in fig. 3, where VIN is used as the input signal of the delay chain. The multiplexer (muxnx 1) selects one path from the taps of the N DELAY units (DELAY) as the output signal VOUT. Due to variations in delay time of the delay chain with process corner, voltage and temperature (PVT), the delay time varies by even more than a factor of two under different PVT variations. The larger delay time can increase the settling time of the DAC, thereby improving the overall performance of the ADC, but may cause the loss of the last several comparison pulses of the ADC, which affects the yield of the ADC in mass production. Smaller delay times can cause poor performance of the ADC.

Disclosure of Invention

The invention aims to provide a delay control circuit of an asynchronous successive approximation analog-digital converter, which can improve the working speed of an ADC (analog-to-digital converter), improve the linearity and the signal-to-noise ratio (SNR) of the ADC and increase the yield of mass production chips.

The technical scheme for realizing the purpose is as follows:

a delay control circuit for an asynchronous successive approximation analog-to-digital converter, comprising: a phase-locked loop correction circuit and a delay chain circuit, wherein,

the phase-locked loop correction circuit comprises a voltage-controlled oscillator and provides a first control voltage of the voltage-controlled oscillator;

the delay chain circuit includes:

the delay chain is formed by cascading N stages of first delay units; n is more than or equal to 2 and is a positive integer;

the multiplexer is respectively connected with the output end of each first delay unit in the delay chain;

the input end of the first buffer is connected with the first control voltage, and the output end of the first buffer is connected with each first delay unit; (BUF) and

a first capacitor with one end grounded and the other end connected with the output end of the first buffer;

the first control voltage generates a second control voltage for controlling the delay time of each first delay unit after passing through the first buffer and the first capacitor.

Preferably, the phase-locked loop correction circuit further includes: a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop filter (LPF), a first inverter and an M-frequency divider, wherein,

the phase frequency detector receives a reference frequency;

the output end of the phase frequency detector is connected with the input end of the charge pump;

the output end of the charge pump is connected with the loop filter and the voltage-controlled oscillator;

the loop filter generates the first control voltage to supply to the voltage-controlled oscillator;

the output end of the voltage-controlled oscillator is connected with the input end of the phase frequency detector through the first phase inverter and the M frequency divider in sequence.

Preferably, the voltage controlled oscillator includes: n stages of second delay units which are mutually cascaded, and a third delay unit which is cascaded with the last stage of second delay unit and outputs feedback to the first stage of second delay unit; n is more than or equal to 2 and is a positive integer;

the delay time of the second delay unit is twice the delay time of the third delay unit;

the first control voltage is supplied to each of the second delay unit and the third delay unit.

Preferably, the first delay unit and the second delay unit have the same structure and are formed by cascading two controllable inverters; the third delay unit comprises a controllable inverter;

the voltage controlled oscillator and the delay chain circuit each further include: the error amplifier comprises an Error Amplifier (EA), a first PMOS (P-channel metal oxide semiconductor) tube, a first resistor, a second PMOS tube and a first NMOS (N-channel metal oxide semiconductor) tube, wherein the first input end of the error amplifier is connected with the first control voltage or the second control voltage, the second input end of the error amplifier is grounded through the first resistor, and the output end of the error amplifier is connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube;

the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is grounded through the first resistor;

the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube;

the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube;

the source electrode of the first NMOS tube is grounded;

the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube are respectively connected with each first delay unit or each second delay unit and each third delay unit;

the delay chain circuit further includes: and the second buffer is connected with the output end of the multiplexer.

Preferably, the first delay unit and the second delay unit have the same structure and are formed by cascading two stages of differential inverters; the third delay unit comprises a first-stage differential inverter;

the voltage controlled oscillator and the delay chain circuit each further include: the double-conversion single circuit converts the differential signal output by the third delay unit or the differential signal output by the multiplexer into a single-path signal;

the delay chain circuit further includes: and the third buffer is connected with the output end of the double-conversion single circuit.

Preferably, the controllable inverter comprises: a third PMOS tube, a fourth PMOS tube, a second NMOS tube and a third NMOS tube, wherein,

the source electrode of the third PMOS tube is connected with a power supply, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, and the grid electrode of the third PMOS tube is connected with the grid electrode of the second PMOS tube;

the connection end of the drain electrode of the fourth PMOS tube and the drain electrode of the second NMOS tube is used as an output end;

the connection end of the grid electrode of the fourth PMOS tube and the grid electrode of the second NMOS tube is used as an input end;

the source electrode of the third NMOS tube is grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube.

Preferably, the differential inverter includes: a variable capacitor, a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, wherein,

the control end of the variable capacitor is connected with the first control voltage or the second control voltage;

the source electrodes of the fifth PMOS tube and the sixth PMOS tube are connected with a power supply;

the source electrodes of the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are grounded;

the connection end of the grid electrode of the fifth PMOS tube and the grid electrode of the fourth NMOS tube is used as an input end;

the connection end of the grid electrode of the sixth PMOS tube and the grid electrode of the seventh NMOS tube is used as the other input end;

the drain electrode of the fifth PMOS tube, the drain electrode of the fourth NMOS tube, the drain electrode of the fifth NMOS tube, the gate electrode of the sixth NMOS tube and the first end of the variable capacitor are connected, and the connected end serves as an output end;

and the drain electrode of the sixth PMOS tube, the drain electrode of the seventh NMOS tube, the grid electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube and the second end of the variable capacitor are connected, and the connected end is used as the other output end.

Preferably, the double-conversion single circuit comprises: a seventh PMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein,

the source electrode of the seventh PMOS tube is connected with a power supply, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube, and the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube and the drain electrode of the seventh PMOS tube;

the source electrode of the eighth PMOS tube is connected with a power supply;

the connection end of the drain electrode of the eighth PMOS tube and the drain electrode of the ninth NMOS tube is used as an output end;

the source electrodes of the eighth NMOS transistor and the ninth NMOS transistor are grounded;

and the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube are used as two input ends.

The invention has the beneficial effects that: the invention adopts a phase-locked loop to automatically correct the delay time of the delay control circuit in real time, and reduces the variation of a comparison clock generated by the asynchronous SAR-ADC delay loop along with the process angle, the voltage and the temperature (PVT). Therefore, in mass production, the variation of the ADC conversion time can be greatly reduced, thereby leaving sufficient margin for the settling time of the capacitance digital-to-analog conversion array (CDAC) in the ADC. The invention can improve the working speed of the asynchronous SAR-ADC, improve the linearity and the signal-to-noise ratio of the ADC and increase the yield of mass production chips.

Drawings

FIG. 1 is a delay control circuit of an asynchronous successive approximation analog-to-digital converter of the present invention;

FIG. 2 is a schematic diagram of the basic structure of an asynchronous SAR-ADC;

FIG. 3 is a circuit diagram of a prior art delay control circuit for an asynchronous SAR-ADC;

FIG. 4 is a circuit diagram of a phase locked loop correction circuit of the present invention;

FIG. 5 is a circuit diagram of an embodiment of a voltage controlled oscillator according to the present invention;

FIG. 6 is a circuit diagram of one embodiment of a delay chain circuit of the present invention;

fig. 7 is a circuit diagram of a second embodiment of a voltage controlled oscillator of the present invention;

fig. 8 is a circuit diagram of a second embodiment of the delay chain circuit of the present invention.

Detailed Description

The invention will be further explained with reference to the drawings.

Referring to fig. 1, the delay control circuit of the asynchronous successive approximation analog-to-digital converter of the present invention includes: a phase-locked loop (PLL) correction circuit and a delay chain circuit.

The phase-locked loop correction circuit comprises a voltage controlled oscillator 11, the phase-locked loop correction circuit providing a first control voltage VC of the voltage controlled oscillator 11.

The delay chain circuit includes: a delay chain, a multiplexer 22, a first buffer 23 and a first capacitor C1. The delay chain is formed by cascading N stages of first delay units 21, wherein N is more than or equal to 2 and is a positive integer. The multiplexers 22 are connected to the outputs of the first delay cells 21 in the delay chain, respectively. Namely: the multiplexer 22 selects one path from the N taps of the first delay unit 21 as the output signal VOUT. The input end of the first buffer 23 is connected with the first control voltage VC, and the output end is connected with each first delay unit 21. The first capacitor C1 has one end connected to ground and the other end connected to the output end of the first buffer 23. The first control voltage VC generates a second control voltage VTRIM for controlling the delay time of each first delay unit 21 after passing through the first buffer 23 and the first capacitor C1. The first capacitor C1 is capable of filtering out high frequency glitches from the phase-locked loop correction circuit.

As shown in fig. 4, the phase-locked loop correction circuit further includes: a phase frequency detector 12, a charge pump 13, a loop filter 14, a first inverter 15 and an M-divider 16.

The phase frequency detector 12 receives a reference frequency FREF. The output end of the phase frequency detector 12 is connected with the input end of the charge pump 13. The output of the charge pump 13 is connected to the loop filter 14 and the voltage controlled oscillator 11. The loop filter 14 generates a first control voltage VC to supply the voltage controlled oscillator 11. The output end of the voltage-controlled oscillator 11 is connected to the input end of the phase frequency detector 12 through the first inverter 15 and the M-frequency divider 16 in sequence.

Specifically, the voltage-controlled oscillator 11 includes: n stages of second delay units 17 which are cascaded with each other, and a third delay unit 18 which is cascaded with the last stage of second delay unit 17 and outputs feedback to the first stage of second delay unit 17; n is more than or equal to 2 and is a positive integer. The delay time of the second delay unit 17 is twice the delay time of the third delay unit 18. The first control voltage VC is supplied to each of the second delay unit 17 and the third delay unit 18, respectively.

If the delay cells in the delay chain circuit and the phase-locked loop correction circuit are the same circuit, the clock period of the voltage controlled oscillator 11(VCO) in the phase-locked loop correction circuit is proportional to the total delay time of the delay chain. Since the reference voltage of the phase-locked loop is derived from a stable clock source outside the chip, the frequency period of the voltage-controlled oscillator 11 in the PLL does not vary with PVT, and the total delay time in the delay chain circuit does not vary with PVT. Once the phase locked loop is locked, the oscillation frequency of the voltage controlled oscillator 11 is equal to M times the external reference frequency and does not vary with PVT. The oscillation period of the voltage-controlled oscillator 11 is proportional to the delay of the N-th order delay unit. The lock voltage of the PLL is taken out to control the delay cells of the delay chain circuit.

As shown in fig. 5 and 6, the first delay unit 21 and the second delay unit 17 have the same structure and are composed of two cascaded controllable inverters; the third delay unit 18 comprises a controllable inverter stage.

The voltage-controlled oscillator 11 and the delay chain circuit each further include: the error amplifier 31, the first PMOS transistor PM1, the first resistor R1, the second PMOS transistor PM2, and the first NMOS transistor NM 1. The first input end of the error amplifier 31 is connected to the first control voltage VC or the second control voltage VTRIM, the second input end is connected to the ground through the first resistor R1, and the output end is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM 2. The source of the first PMOS transistor PM1 is connected to the power supply, and the drain is connected to the ground through the first resistor R1. The source of the second PMOS transistor PM2 is connected to the power supply, and the drain is connected to the drain of the first NMOS transistor NM 1. The drain of the first NMOS transistor NM1 is connected to the gate of the first NMOS transistor NM 1. The source of the first NMOS transistor NM1 is grounded. The gate of the second PMOS transistor PM2 and the gate of the first NMOS transistor NM1 are respectively connected to each first delay unit 21 or each second delay unit 17 and third delay unit 18;

the delay chain circuit further includes: a second buffer 32 connected to the output of the multiplexer 22.

The first control voltage VC or the second control voltage VTRIM generates a controllable current VC/R on the first resistor R1 through the error amplifier 31 and the first PMOS transistor PM1, and the controllable current VC/R is mirrored to each of the first delay unit 21 or the second delay unit 17 and the third delay unit 18 through the second PMOS transistor PM2 and the first NMOS transistor NM 1.

In this embodiment, the controllable inverter includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a second NMOS transistor NM2, and a third NMOS transistor NM 3.

The source electrode of the third PMOS tube PM3 is connected with the power supply, the drain electrode is connected with the source electrode of the fourth PMOS tube PM4, and the grid electrode is connected with the grid electrode of the second PMOS tube PM 2. The connection end of the drain of the fourth PMOS transistor PM4 and the drain of the second NMOS transistor NM2 serves as an output terminal. The gate of the fourth PMOS transistor PM4 and the gate of the second NMOS transistor NM2 are connected as an input terminal. The source of the third NMOS transistor NM3 is grounded, the drain is connected to the source of the second NMOS transistor NM2, and the gate is connected to the gate of the first NMOS transistor NM 1.

In the first delay unit 21 or the second delay unit 17, two fourth PMOS transistors PM4 and two second NMOS transistors NM2 form a delay buffer, and two third PMOS transistors PM3 and two third NMOS transistors NM3 are controlled by a controllable mirror current to change the oscillation frequency through charging and discharging. In fig. 5, the N-stage second delay unit 17 is connected to the third delay unit 18, and the output is fed back to the input of the first-stage second delay unit 17, thereby forming an odd-order ring oscillator circuit. Finally the output of this circuit outputs the VCO signal via a first inverter 15 to the frequency divider circuit of the PLL. In fig. 6, the delay cell structure is the same as that in fig. 5. Then, the input signal is delayed by the N-stage first delay unit 21, and the multiplexer 22 selects one of the taps of the N first delay units 21 to be shaped by the second buffer 32 as the output signal VOUT.

As shown in fig. 7 and 8, the first delay unit 21 and the second delay unit 17 have the same structure and are composed of two stages of differential inverters in cascade connection; the third delay unit 18 includes a one-stage differential inverter.

The voltage-controlled oscillator 11 and the delay chain circuit each further include: and a double-single-conversion circuit 41 for converting the differential signal output from the third delay unit 18 or the differential signal output from the multiplexer 22 into a single-channel signal.

The delay chain circuit further includes: and a third buffer 42 connected to an output terminal of the double conversion circuit 41.

The differential inverter includes: the variable capacitor C2, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM 7.

The control end of the variable capacitor C2 is connected with the first control voltage VC or the second control voltage VTRIM. The sources of the fifth PMOS pipe PM5 and the sixth PMOS pipe PM6 are connected with the power supply. The sources of the fourth, fifth, sixth and seventh NMOS transistors NM4, NM5, NM6 and NM7 are grounded, respectively. The gate of the fifth PMOS transistor PM5 and the gate of the fourth NMOS transistor NM4 are connected as an input terminal. The connection end of the gate of the sixth PMOS transistor PM6 and the gate of the seventh NMOS transistor NM7 serves as the other input end. The drain of the fifth PMOS transistor PM5, the drain of the fourth NMOS transistor NM4, the drain of the fifth NMOS transistor NM5, the gate of the sixth NMOS transistor NM6 and the first end of the variable capacitor C2 are connected, and the connected end serves as an output end.

The drain of the sixth PMOS transistor PM6, the drain of the seventh NMOS transistor NM7, the gate of the fifth NMOS transistor NM5, the drain of the sixth NMOS transistor NM6 and the second end of the variable capacitor C2 are connected, and the connected end serves as the other output end.

The double-conversion single circuit 41 includes: a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, an eighth NMOS transistor NM8, and a ninth NMOS transistor NM 9. The source electrode of the seventh PMOS tube PM7 is connected with the power supply, the drain electrode is connected with the drain electrode of the eighth NMOS tube NM8, and the grid electrode is connected with the grid electrode of the eighth PMOS tube PM8 and the drain electrode of the seventh PMOS tube PM 7. The source electrode of the eighth PMOS pipe PM8 is connected with the power supply. The connection end of the drain of the eighth PMOS transistor PM8 and the drain of the ninth NMOS transistor NM9 serves as an output terminal. The sources of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are grounded, respectively. The gate of the eighth NMOS transistor NM8 and the gate of the ninth NMOS transistor NM9 serve as two input terminals.

The first control voltage VC or the second control voltage VTRIM controls the output capacitive load of the first delay cell 21 or the second delay cell 17 through two variable capacitors C2. The fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the fourth NMOS transistor NM4, and the seventh NMOS transistor NM7 form a differential inverter, and the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 form a latch, which regeneratively amplifies the output voltage. The oscillation frequency is changed by adjusting the variable capacitance C2 in each stage of the circuit. In fig. 7, the N-stage second delay unit 17 is cascaded with the third delay unit 18, and the output is fed back to the input of the first-stage second delay unit 17, thereby forming an odd-order ring oscillator circuit. Finally, the output of the circuit is converted into a single-path signal by the double-conversion single circuit 41, and the VCO signal is output to the frequency divider circuit of the PLL by the first inverter 15. In the double-conversion single circuit 41, two input ends respectively receive two paths of high-frequency voltage signals with opposite phases, convert the high-frequency voltage signals into current, add the current at an output stage and convert the current into voltage. In fig. 8, the delay cell structure is the same as that in fig. 7. An input signal VIN generates a path of inverted signal through an inverter, and is simultaneously supplied to a differential delay link as an input together with a self signal, the input signal is delayed by the N-order cascade first delay unit 21, the multiplexer 22 selects a path of differential signal from taps of the N first delay units 21, and outputs the differential signal to the double-conversion single circuit 41, and then the differential signal is shaped by the third buffer 42 to be used as an output signal VOUT.

The invention is implemented in a CMOS process. Since the PLL circuit is used only for generating the dc correction voltage instead of generating the high frequency clock, it can be implemented with a small area and power consumption. Compared with the prior art, the high-frequency phase-locked loop is adopted to automatically correct the delay time of the delay link, the working speed of the ADC is improved, the linearity and the signal-to-noise ratio of the ADC are improved, and the yield of mass production chips is increased.

The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.

Claims

1. A delay control circuit for an asynchronous successive approximation analog-to-digital converter, comprising: a phase-locked loop correction circuit and a delay chain circuit, wherein,

the delay chain circuit includes:

the input end of the first buffer is connected with the first control voltage, and the output end of the first buffer is connected with each first delay unit; and

2. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 1, wherein said phase-locked loop correction circuit further comprises: a phase frequency detector, a charge pump, a loop filter, a first inverter and an M frequency divider, wherein,

the phase frequency detector receives a reference frequency;

3. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 2, wherein said voltage controlled oscillator comprises: n stages of second delay units which are mutually cascaded, and a third delay unit which is cascaded with the last stage of second delay unit and outputs feedback to the first stage of second delay unit; n is more than or equal to 2 and is a positive integer;

4. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 3, wherein said first delay unit and said second delay unit have the same structure and are each composed of two cascaded controllable inverters; the third delay unit comprises a controllable inverter;

the voltage controlled oscillator and the delay chain circuit each further include: the error amplifier comprises an error amplifier, a first PMOS (P-channel metal oxide semiconductor) tube, a first resistor, a second PMOS tube and a first NMOS (N-channel metal oxide semiconductor) tube, wherein the first input end of the error amplifier is connected with the first control voltage or the second control voltage, the second input end of the error amplifier is grounded through the first resistor, and the output end of the error amplifier is connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube;

the source electrode of the first NMOS tube is grounded;

5. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 3, wherein said first delay unit and said second delay unit are identical in structure and are each composed of two stages of differential inverter cascades; the third delay unit comprises a first-stage differential inverter;

6. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 4, wherein said controllable inverter comprises: a third PMOS tube, a fourth PMOS tube, a second NMOS tube and a third NMOS tube, wherein,

7. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 5, wherein said differential inverter comprises: a variable capacitor, a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, wherein,

8. The delay control circuit of an asynchronous successive approximation analog-to-digital converter according to claim 5, wherein said double single conversion circuit comprises: a seventh PMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein,

the source electrode of the eighth PMOS tube is connected with a power supply;