CN106209080A - A kind of all-digital phase-locked loop of low jitter width capture frequency scope - Google Patents
A kind of all-digital phase-locked loop of low jitter width capture frequency scope Download PDFInfo
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- CN106209080A CN106209080A CN201610618131.5A CN201610618131A CN106209080A CN 106209080 A CN106209080 A CN 106209080A CN 201610618131 A CN201610618131 A CN 201610618131A CN 106209080 A CN106209080 A CN 106209080A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses the all-digital phase-locked loop of a kind of low jitter width capture frequency scope, including TDC module, digital filter, DCO module, two-divider and variable mould frequency divider；TDC module compares the reference clock of input and the phase place of feedback clock, output phase error signal；Phase error signal is converted to one group of control word by digital filter, and DCO module adjusts frequency and the phase place of output clock according to this group control word；Two-divider generates feedback clock after the frequency of output clock is reduced half, divided according to default modulus value by variable mould frequency divider and compares to TDC module；Circulation is until reference clock is consistent with the frequency of feedback clock according to this, and when phase place reaches to preset error, all-digital phase-locked loop locks.TDC module reduces output jitter；The capture frequency scope of phaselocked loop has been widened in the adjustment of DCO module, solves the problem that jitter value is higher, capture frequency scope is narrower of existing all-digital phase-locked loop.
Description
Technical field
The present invention relates to PHASE-LOCKED LOOP PLL TECHNIQUE field, digital phase-locked particularly to a kind of low jitter width capture frequency scope
Ring.
Background technology
Phaselocked loop (Phase-Locked Loop, PLL) is that one automatically controls feedback system, and it is by outside ginseng
Examine the frequency plot of clock signal and feedback clock signal, produce clock signal consistent with reference clock signal frequency plot.Change
For it, phaselocked loop is used to locking and follows the trail of the frequency of reference clock signal and phase place.When phaselocked loop is in the lock state
Time, feedback clock frequency is consistent with reference clock frequency, and between feedback clock phase place and reference clock phase place, existence one is small
Error.
According to the difference of method for designing, phaselocked loop can be divided into again analog phase-locked look, digital phase-locked loop and digital phase-locked
Ring.A classical phase-locked loop systems structure as shown in Figure 1, it includes that digital phase discriminator, digital filter, a numerical control are shaken
Swing device and digital frequency divider.ADPLL(All-Digitally controlled Phase-Locked Loop, all-digitized demodulator
Phaselocked loop or all-digital phase-locked loop) stability that has, motility and portability make it obtain substantial amounts of grinding in recent years
Study carefully interest, and instead of traditional analog phase-locked look in some performance application occasion.
Shake is an important performance indexes of phaselocked loop, in order to allow the jitter performance of all-digital phase-locked loop can be with simulation
The jitter performance of phaselocked loop matches in excellence or beauty, and needs constantly to reduce the output jitter value of phaselocked loop in Design of PLL.Shake based on annular
Although the all-digital phase-locked loop output frequency swinging device is the highest, but area is little is easily achieved.In order to improve the application scenario of phaselocked loop,
Also need to widen the capture frequency scope of phaselocked loop.
Thus prior art could be improved and improve.
Summary of the invention
In place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of low jitter width capture frequency model
The all-digital phase-locked loop enclosed, to solve the problem that the jitter value of existing all-digital phase-locked loop is higher, capture frequency scope is narrower.
In order to achieve the above object, this invention takes techniques below scheme:
A kind of all-digital phase-locked loop of low jitter width capture frequency scope, it include TDC module, digital filter, DCO module,
Two-divider and variable mould frequency divider；
Described TDC module compares the reference clock of input and the phase place of feedback clock, the phase error signal of output numeral；Numeral
Phase error signal is converted to one group of control word by wave filter, and DCO module adjusts the frequency of output clock according to this group control word
And phase place；Two-divider will output clock frequency reduce half, then by variable mould frequency divider according to default modulus value frequency dividing after
Generate feedback clock to continue to compare to TDC module；
Circulation is until reference clock is consistent with the frequency of feedback clock according to this, when phase place reaches to preset error, and all-digital phase-locked loop
Locking.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described TDC module includes PFD circuit, whole
Number TDC, decimal TDC and decoder:
Described PFD circuit comparison reference clock and the phase place of feedback clock, output phase error initial signal and phase error are eventually
Stop signal；The phase error resolution with integer TDC is judged according to phase error initial signal and phase error termination signal
Size, and corresponding selection integer TDC works or decimal TDC work；
The thermometer code of one group 31 is exported during integer TDC work；The one-hot encoding of output 7 during decimal TDC work；
The thermometer code of described 31 is converted to the high 5 of phase error signal by decoder, removes last position of one-hot encoding
After be converted to the low 6 of phase error signal, output phase error signal after integration.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described PFD circuit judges phase error is big
When the resolution of integer TDC, control integer TDC work；When phase error is less than the resolution of integer TDC, control decimal TDC
Work；
Described phase error is the pulse between phase error initial signal and adjacent two rising edges of phase error termination signal
Length.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described DCO module includes:
DCO decoder, for generating two groups of coarse adjustment control words and one group of coarse control word according to control word；
DCO circuit, for adjusting frequency and the phase place of output clock according to two groups of coarse adjustment control words, adjusts according to coarse control word
The resolution of DCO module.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described DCO circuit includes:
Coarse adjustment time delay electronic circuit, adjusts frequency and the phase of output clock for adjusting delay time according to two groups of coarse adjustment control words
Position, and export upper limit magnitude signal and Lower Limit Amplitude signal；
Fine tuning time delay electronic circuit, for adjusting the resolution of upper limit magnitude signal and Lower Limit Amplitude signal also according to coarse control word
The oscillator signal that output is corresponding；
Phase inverter, for by anti-phase for oscillator signal output output clock.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described PFD circuit include the first trigger,
Second trigger, first with door, second with door, the first NAND gate, the second NAND gate, the 3rd NAND gate, the 4th NAND gate, the 5th
NAND gate, the 6th NAND gate, the 7th NAND gate and NAND gate group；The D foot of described first trigger and the second trigger is all connected with
Positive source, the CK foot of the first trigger connects reference clock；The Q foot of the first trigger connects the first input of NAND gate group
End, an input of the first NAND gate and an input of the 5th NAND gate；The Rst foot of the first trigger connects the second trigger
Rst foot and first connect feedback clock with the outfan of door, the CK foot of the second trigger；The Q foot of the second trigger connects the
Two with an input of door, an input of the 4th NAND gate and another input of the 5th NAND gate；5th NAND gate defeated
Go out end and connect an input of first and door, first and the reset signal outside the input of another input of door, the 5th NAND gate
An input connect second with another input of door and an input of the 3rd NAND gate, second is connected with the outfan of door
Digital filter, another input of the 5th NAND gate connects the second input and an input of the second NAND gate of NAND gate group
End；First outfan of NAND gate group connects another input sum of another input of the first NAND gate, the 4th NAND gate
Word wave filter；Second outfan of NAND gate group connects another input and an input of the 3rd NAND gate of the second NAND gate
End, the outfan of the first NAND gate connects an input of the 6th NAND gate, and the outfan of the second NAND gate connects the 6th with non-
Another input of door, the outfan of the 6th NAND gate connects integer TDC and decimal TDC, and the outfan of the 3rd NAND gate connects
One input of the 7th NAND gate, the outfan of the 4th NAND gate connects another input of the 7th NAND gate, the 7th NAND gate
Outfan connect integer TDC and decimal TDC.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described first trigger, the second trigger
Trigger for sense amplifier type.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described integer TDC include the 3rd with door, 31
Individual d type flip flop and 31 chronotron；Described 31 chronotron are connected into gate delay chain, and the described 3rd is connected with an input of door
The outfan of the 6th NAND gate, the 3rd is connected decimal TDC with another input of door, and the 3rd is connected first with the outfan of door
The input of chronotron, the D foot of each chronotron is connected one to one with the input of each d type flip flop, and the CK foot of each d type flip flop is equal
Connect the outfan of the 7th NAND gate；The Q foot of each d type flip flop connects decoder, exports the thermometer code of 31.
In the all-digital phase-locked loop of described low jitter width capture frequency scope, described decimal TDC include the first amplifier,
Second amplifier, the 3rd amplifier, the 4th amplifier, the 5th amplifier, the 6th amplifier, the 7th amplifier, the first integer inspection
Survey device, the second integer detector, the 3rd integer detector, the 4th integer detector, the 5th integer detector, the 6th integer detection
Device, the 7th integer detector, the first XOR gate, the second XOR gate, the 3rd XOR gate, the 4th XOR gate, the 5th XOR gate, the 6th
XOR gate and the 7th XOR gate；
One input of described first amplifier connects outfan and an input of the first integer detector of the 6th NAND gate,
The outfan of another input connection the 7th NAND gate of the first amplifier and another input of the first integer detector, first
The outfan of integer detector connects another input of the 3rd and door, and an outfan of the first amplifier connects the second amplifier
An input and an input of the second integer detector, another outfan of the first amplifier connects the another of the second amplifier
One input and another input of the second integer detector, the one of outfan connection the 3rd amplifier of the second amplifier is defeated
Entering an input of end and the 3rd integer detector, another outfan of the second amplifier connects another input of the 3rd amplifier
End and another input of the 3rd integer detector, an outfan of the 3rd amplifier connect the 4th amplifier an input and
One input of the 4th integer detector, another outfan of the 3rd amplifier connects another input and the of the 4th amplifier
Another input of four integer detectors, an outfan of the 4th amplifier connects an input of the 5th amplifier and the 5th whole
One input of number detector, another outfan of the 4th amplifier connects another input and the 5th integer of the 5th amplifier
Another input of detector, an outfan of the 5th amplifier connects an input and the detection of the 6th integer of the 6th amplifier
One input of device, another outfan of the 5th amplifier connects another input and the 6th integer detector of the 6th amplifier
Another input, the 6th amplifier one outfan connect the 7th amplifier an input and the one of the 7th integer detector
Input, another outfan of the 6th amplifier connects another of another input of the 7th amplifier and the 7th integer detector
Input, one end power cathode of the first XOR gate, the outfan of the second integer detector connects the other end of the first XOR gate
With one end of the second XOR gate, the outfan of the 3rd integer detector connects the other end of the second XOR gate and the 3rd XOR gate
One end, the outfan of the 4th integer detector connects the other end and one end of the 4th XOR gate, the 5th integer of the 3rd XOR gate
The outfan of detector connects the other end and one end of the 5th XOR gate, the outfan of the 6th integer detector of the 4th XOR gate
Connecting the other end and one end of the 6th XOR gate of the 5th XOR gate, the outfan of the 7th integer detector connects the 6th XOR gate
The other end and one end of the 7th XOR gate, the other end of the 7th XOR gate connects positive source；The outfan of each XOR gate is even
Connect decoder, export the one-hot encoding of 7.
Compared to prior art, the all-digital phase-locked loop of the low jitter width capture frequency scope that the present invention provides, pass through TDC
Module compares the reference clock of input and the phase place of feedback clock, the phase error signal of output numeral；Digital filter is by phase
Position error signal is converted to one group of control word, and DCO module adjusts frequency and the phase place of output clock according to this group control word；Two points
Frequently the frequency of output clock is reduced half by device, then generates feedback clock by variable mould frequency divider according to after default modulus value frequency dividing
Continue to compare to TDC module；Circulation is until reference clock is consistent with the frequency of feedback clock according to this, and phase place reaches to preset error
Time, all-digital phase-locked loop locks.TDC module improves the accuracy of differential phase error, reduces output jitter；DCO module
Adjustment widened the capture frequency scope of phaselocked loop, the jitter value solving existing all-digital phase-locked loop is higher, capture frequency
The problem that scope is narrower.
Accompanying drawing explanation
Fig. 1 is existing phase-locked loop systems structure.
The structured flowchart of the all-digital phase-locked loop of the low jitter width capture frequency scope that Fig. 2 provides for the present invention.
The structured flowchart of TDC module in the all-digital phase-locked loop that Fig. 3 provides for the present invention.
The circuit diagram of pfc circuit in the all-digital phase-locked loop that Fig. 4 provides for the present invention.
The circuit diagram of integer TDC in the all-digital phase-locked loop that Fig. 5 provides for the present invention.
The circuit diagram of decimal TDC in the all-digital phase-locked loop that Fig. 6 provides for the present invention.
The input and output schematic diagram of decoder in the all-digital phase-locked loop that Fig. 7 provides for the present invention.
The workflow diagram of decoder in the all-digital phase-locked loop that Fig. 8 provides for the present invention.
The circuit diagram of DCO circuit in the all-digital phase-locked loop that Fig. 9 provides for the present invention.
The circuit diagram of fine tuning time delay electronic circuit in the all-digital phase-locked loop that Figure 10 provides for the present invention.
Detailed description of the invention
The present invention provides the all-digital phase-locked loop of a kind of low jitter width capture frequency scope.For making the purpose of the present invention, skill
Art scheme and effect are clearer, clear and definite, and the present invention is described in more detail for the embodiment that develops simultaneously referring to the drawings.Should manage
Solving, specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Referring to Fig. 2, the embodiment of the present invention provides the all-digital phase-locked loop of a kind of low jitter width capture frequency scope, its bag
Include TDC(Timer Digital Converter, time-to-digit converter) module 10, digital filter 20, DCO
(Digitally Controlled Oscillator, digital controlled oscillator) module 30, two-divider 40 and variable mould frequency divider
50.Described TDC module 10 comparison reference clock (outside input) in_Refclk and the phase place of feedback clock in_Divclk, output
Numeral phase error signal to digital filter 20, digital filter 20 through internal a series of computings by phase error signal
Being converted to one group of control word and be transferred to DCO module 30, DCO module 30 adjusts the frequency of output clock Out_CLK according to control word
Rate and phase place；The frequency of output clock is reduced half by described two-divider 40, then by variable mould frequency divider according to default mould
Generate feedback clock after value frequency dividing and feed back to TDC module 10.TDC module 10 is further continued for comparing, and so circulation work is until reference
Clock is consistent with the frequency of feedback clock, when there is default error (the most small, such as less than the 5% of phase lock loop locks cycle) in phase place,
Phase lock loop locks (generally jitter value less than the phase lock loop locks cycle 5% time think phase-locked locking).Phase-locked in the present embodiment
Ring i.e. all-digital phase-locked loop.
In the present embodiment, the core of ADPLL is TDC module 10 and DCO module 30.See also Fig. 3, described
TDC module 10 includes PFD(Phase Frequency Detector, phase frequency detector or phase discriminator) circuit 110, integer TDC
120, decimal TDC 130 and decoder 140.
Wherein, for small phase error, TDC module 10 is called decimal TDC 130 and is quantified；For bigger phase
Position error, TDC module 10 is called integer TDC 120 and is quantified.The resolution of decimal TDC 130 is high and in hypoexponential distribution,
The dynamic range of integer TDC 120 is big and has the good linearity.So while guaranteeing TDC module 10 dynamic range also
Its resolution can be improved, be especially suitable for PLL(phaselocked loop) design requirement.
The operation principle of TDC module 10 is: PFD circuit 110 comparison reference clock in_Refclk and feedback clock in_
The phase place of Divclk, output phase error direction signal Dir, phase error more new signal Update, phase error initial signal
Start and phase error termination signal Stop.TDC, according to the size of phase error, automatically selects integer TDC or decimal TDC work
Make, particularly as follows: when phase error is more than the resolution of integer TDC 120, integer TDC 120 works, and decimal TDC 130 exports
0.When phase error is less than the resolution of integer TDC 120, decimal TDC 130 works, and integer TDC 120 exports 0.
Integer TDC 120 is made up of traditional gate delay chain TDC, its resolution τ equal to two phase inverters time delay (
Under 0.18 μm CMOS technology, phase inverter transmission delay ≈ 40ps, then τ ≈ 80ps).Integer TDC 120 exports the heat of one group 31
Thermometer-code High [30:0].Decimal TDC 130 is made up of the twice time amplifier of one group of series connection, and it can be small phase place
Error is amplified to more than τ.Decimal TDC produces the one-hot encoding Low [6:0] of 7, and each precision represented corresponds to τ's respectively
2-1, 2-2..., 2-6, 2-7.31 thermometer codes of integer TDC 120 are translated as the phase error of numeral by decoder 140
Signals DP haseError's is high 5；The one-hot encoding of the decimal TDC of 7 is removed last position, is converted to phase error signal
DPhaseError's is low 6；The phase error signal DPhaseError of i.e. the most exportable complete 11 after integration.Whole TDC
Module 10 finally exports the phase error signal DPhaseError of 11 bit digital.The resolution of TDC module 10 is 1.25ps, dynamic
State scope is 2.5ns.
See also Fig. 4, described PFD circuit 110 include the first trigger SAFF1, the second trigger SAFF2, first
With door A1, second and door A2, the first NAND gate S1, the second NAND gate S2, the 3rd NAND gate S3, the 4th NAND gate S4, the 5th with
Not gate S5, the 6th NAND gate S6, the 7th NAND gate S7 and NAND gate group 111；Described first trigger SAFF1 and the second trigger
The D foot of SAFF2 is all connected with the CK foot of positive source VDD, the first trigger SAFF1 and connects reference clock in_Refclk；First touches
Send out device SAFF1 Q foot connect the first input end I1 of NAND gate group 111, the first NAND gate S1 an input and the 5th with non-
One input of door S5；The Rst foot of the first trigger SAFF1 connects the Rst foot and first of the second trigger SAFF2 with door A1's
Outfan, the CK foot of the second trigger SAFF2 connects feedback clock in_Divclk；The Q foot of the second trigger SAFF2 connects the
Two with an input of door A2, an input of the 4th NAND gate S4 and another input of the 5th NAND gate S5；5th with non-
The outfan of door S5 connects an input of first and door A1, the reset signal outside the input of another input of first and door A1
In_Reset, it is defeated with the one of another input of door A2 and the 3rd NAND gate S3 that an input of the 5th NAND gate S5 connects second
Entering end, second is connected digital filter (Update) with the outfan of door A2, the connection of another input of the 5th NAND gate S5 and
Second input I2 of not gate group 111 and an input of the second NAND gate S2；First outfan O1 of NAND gate group 111 connects
Another input of first NAND gate S1, another input of the 4th NAND gate S4 and digital filter (Dir)；NAND gate group
The second outfan O2 of 111 connects another input and an input of the 3rd NAND gate S3 of the second NAND gate S2, first with
The outfan of not gate S1 connects an input of the 6th NAND gate S6, and the outfan of the second NAND gate S2 connects the 6th NAND gate S6
Another input, the outfan (Start) of the 6th NAND gate S6 connects integer TDC and decimal TDC, the 3rd NAND gate S3 defeated
Going out end and connect an input of the 7th NAND gate S7, the outfan of the 4th NAND gate S4 connects another input of the 7th NAND gate S7
End, the outfan (Stop) of the 7th NAND gate S7 connects integer TDC and decimal TDC.
The circuit structure of described NAND gate group 111 as shown in Figure 4, is not described further.The core technology of PFD circuit 110
It it is that the trigger (SAFF1, SAFF2) using sense amplifier type replaces conventional transmission door trigger so that PFD circuit (phase demodulation
Device) reduce the dependence to the time of setting up, improve timing performance and the accuracy of phase error discriminating of phase discriminator.This mirror
Phase device is long by the pulse between phase error initial signal Start and adjacent two rising edges of phase error termination signal Stop
Degree represents phase error.Phase error initial signal Start represents the initial of phase error, phase error termination signal Stop
Represent the termination of phase error.Phase error direction signal Dir represents the direction of phase error, when the phase place of reference clock is advanced
During feedback clock, Dir exports high level；When the phase place of reference clock lags behind the phase place of feedback clock, Dir exports low electricity
Flat；Dir is signally attached to the digital filter end of phaselocked loop, and the data for digital filter process.Each phase error is examined
(whenever a phase error is measured complete) when surveying complete, phase error more new signal Update exports an of short duration pulse
Signal, Update produces the synchronised clock of digital filter through clock generator.
The major function of integer TDC is to improve the dynamic range of TDC, and therefore the resolution of integer TDC need not do very
Height, but the linearity to be got well.In the present embodiment, described integer TDC uses gate delay chain TDC structure, sees also Fig. 5, whole
Number TDC includes the 3rd and door A3,31 d type flip flops (DFF0 ~ DFF30) and 31 chronotron (BUF0 ~ BUF30)；Described 31
Chronotron (BUF0 ~ BUF30) is connected into gate delay chain, and the described 3rd is connected the 6th with non-with an input (Start) of door A3
The outfan of door S6, the 3rd is connected decimal TDC with another input (EN_BTDC) of door A3, and the outfan of the 3rd and door A3 is even
Connect the input (i.e. the input of gate delay chain) of first chronotron BUF0, the D foot of each chronotron (BUF0 ~ BUF30) with
The input of each d type flip flop connect one to one (BUF0 connects DFF0, BUF1 and connects DFF1, by that analogy), each d type flip flop (DFF0 ~
DFF30) CK foot is all connected with the outfan of the 7th NAND gate S7；The Q foot of each d type flip flop (DFF0 ~ DFF30) connects decoder,
Export the thermometer code High [30:0] of 31.
Enable signal EN_BTDC in Fig. 5 transmits from decimal TDC, when phase error is less than gate delay chain
During time delay τ, enabling signal EN_BTDC is low level, and integer TDC does not works.When phase error is more than τ, enable signal EN_
BTDC is high level, and integer TDC works.Phase error initial signal Start is along gate delay chain onwards transmission, due to each D
The input of trigger (DFF) is ined succession the output of a chronotron BUF.The clock end of all d type flip flops connects phase error eventually
Stop signal Stop, when phase error termination signal Stop rising edge arrives, d type flip flop gathers each chronotron BUF output
Value, obtains the phase error signal of one group of thermometer-code form.Chronotron BUF is made up of, at SMIC the phase inverter of two series connection
Under 0.18 μm CMOS technology, the time delay of phase inverter the chances are 40ps, therefore the resolution of integer TDC is 80ps.Because integer
TDC has 31 delay units, and therefore the dynamic range of integer TDC is 2.48ns (31 × 80 ps), approximates 2.5ns.
Decimal TDC is the key of whole TDC, sees also Fig. 6, and it includes the first amplifier TA0, the second amplifier
TA1, the 3rd amplifier TA2, the 4th amplifier TA3, the 5th amplifier TA4, the 6th amplifier TA5, the 7th amplifier TA6,
One integer detector C the 0, second integer detector C the 1, the 3rd integer detector C the 2, the 4th integer detector C the 3, the 5th integer inspection
Survey device C4, the 6th integer detector C the 5, the 7th integer detector C the 6, first XOR gate X0, the second XOR gate X1, the 3rd XOR gate
X2, the 4th XOR gate X3, the 5th XOR gate X4, the 6th XOR gate X5 and the 7th XOR gate X6.
One input of described first amplifier TA0 connects outfan (Start) and first integer of the 6th NAND gate S6
One input of detector C 0, another input of the first amplifier TA0 connect the 7th NAND gate S7 outfan (Stop) and
Another input of first integer detector C 0, the outfan of the first integer detector C 0 connects another input of the 3rd and door A3
End (EN_BTDC), an outfan of the first amplifier TA0 connects an input and the detection of the second integer of the second amplifier TA1
One input of device C1, another outfan of the first amplifier TA0 connects another input of the second amplifier TA1 and second whole
Another input of number detector C 1, an outfan of the second amplifier TA1 connects an input and the of the 3rd amplifier TA2
One input of three integer detector C 2, another outfan of the second amplifier TA0 connects another input of the 3rd amplifier TA2
End and another input of the 3rd integer detector C 2, an outfan of the 3rd amplifier TA2 connects the one of the 4th amplifier TA3
Input and an input of the 4th integer detector C 3, another outfan of the 3rd amplifier TA2 connects the 4th amplifier TA3
Another input and another input of the 4th integer detector C 3, an outfan of the 4th amplifier TA3 connects the 5th to be put
One input of big device TA4 and an input of the 5th integer detector C 4, another outfan of the 4th amplifier TA3 connects the
Another input of five amplifier TA4 and another input of the 5th integer detector C 4, an outfan of the 5th amplifier TA4
Connecting an input and an input of the 6th integer detector C 5 of the 6th amplifier TA5, another of the 5th amplifier TA4 is defeated
Go out another input and another input of the 6th integer detector C 5, the 6th amplifier TA5 that end connects the 6th amplifier TA5
An outfan connect the input of the 7th amplifier TA6 and an input of the 7th integer detector C 6, the 6th amplifier
Another outfan of TA5 connects another input and another input of the 7th integer detector C 6 of the 7th amplifier TA6, the
One end power cathode VSS of one XOR gate X0, the outfan of the second integer detector C 1 connects the other end of the first XOR gate X0
With one end of the second XOR gate X1, the outfan of the 3rd integer detector C 2 connects the other end of the second XOR gate X1 and the 3rd different
Or one end of door X2, the outfan of the 4th integer detector C 3 connects the other end of the 3rd XOR gate X2 and the 4th XOR gate X3
One end, the outfan of the 5th integer detector C 4 connects the other end and one end of the 5th XOR gate X4 of the 4th XOR gate X3, the
The outfan of six integer detector C 5 connects the other end and one end of the 6th XOR gate X5 of the 5th XOR gate X4, the 7th integer inspection
The outfan surveying device C6 connects the other end of the 6th XOR gate X5 and one end of the 7th XOR gate X6, another of the 7th XOR gate X6
End connects positive source VDD；The outfan of each XOR gate connects decoder, exports the one-hot encoding Low [6:0] of 7.
Amplifier is twice time amplifier (TA, Time Amplifier).Phase error is connected at 7 amplifiers
TA chain transmits, often just the phase error of input is amplified twice through an amplifier.The effect of integer detector is detection
Whether phase error is more than resolution τ (≈ 80ps) of integer TDC.When the phase error of amplifier output is more than τ, integer is examined
Survey device output logic 1；When the phase error of amplifier output is less than τ, integer detector output logical zero.Finally connect one more
Amplifier (TA6) is to make the driving force of last integer detector identical with integer detector before.XOR gate
Effect be the output of 7 integer detectors to be converted to the one-hot encoding of 7.The detection threshold of integer detector is 80ps, solely
Hot code Low [6:0] is the one-hot encoding of the binary number of 7, have every time and only one be 1, other positions are all 0.Such as, D [6:
0]=1000000, D6 are 1, and to represent phase error signal be 40ps (=80 × 2-1).D [6:0]=0100000, D5 are 1 representative
Phase error signal is 20ps (=80 × 2-2).D [6:0]=0010000, D4 are 1, and to represent phase error signal be 10ps (=80
×2-3).D [6:0]=0001000, D3 are 1, and to represent phase error signal be 5ps (=80 × 2-4).D [6:0]=0000100, D2
Being 1, to represent phase error signal be 2.5ps (=80 × 2-5)；D [6:0]=0000010, D1 are 1 and represent phase error signal
For 1.25ps (=80 × 2-6)；D [6:0]=0000001, D0 then represent all phase error signals less than 1.25ps.
Taking resolution 1.25ps in the present embodiment, the most last Low0 position can be filtered during decoding.Work as PLL
When soon reaching lock-out state, the phase error of TDC module input is far smaller than the resolution of integer TDC, in order to reduce power consumption,
Therefore added an integer detector in TA chain front end to export the enable signal EN_BTDC of integer TDC, so when phase place by mistake
Difference can turn off integer TDC when of the least and only stays decimal TDC to work.
Seeing also Fig. 7, described in_Reset and represent the reset signal of decoder, EN_BTDC is the enable of decoder
Signal.The workflow of decoder is as shown in Figure 8: when either input signal changes, it is judged that reset signal in_Reset
Effectiveness.As reset signal in_Reset effectively (low level 0 is effective), decoder resets, output phase error signal
DPhaseError [10:0] is 0；When reset signal in_RUN is invalid, decoder is whole according to enabling signal EN_BTDC judgement
Number TDC work or decimal TDC work.Enabling signal EN_BTDC is 1 integer TDC work, directly by phase error signal
Low six of DPhaseError is set to 0, and 31 thermometer-codes that integer TDC exports are converted to phase error signal
High five outputs of DPhaseError.Enabling signal EN_BTDC is 0 decimal TDC work, directly by phase error signal
High five of DPhaseError is set to 0, and 7 one-hot encoding that decimal TDC exports are cast out last position as phase error signal
DPhaseError is low six.Constitute the most altogether the phase error signal DPhaseError of the numeral of 11.
This enforcement uses DCO module 30 based on cascade mechanism to design, and DCO module shown in Fig. 2 30 includes DCO decoder
310 and DCO circuit 320.Described DCO decoder 310 generates two groups of coarse adjustment control words (L [2:0] and U [2:0]) according to control word
With one group of coarse control word (F [5:0])；DCO circuit 320 adjusts frequency and the phase of output clock according to two groups of coarse adjustment control words
Position, improves the resolution of DCO module according to coarse control word.
Seeing also Fig. 9, described DCO circuit 320 uses cascade structure, prolongs including coarse adjustment time delay electronic circuit 311, fine tuning
Time electronic circuit 312 and phase inverter 313.Coarse adjustment time delay electronic circuit 311 uses delay path selection technique defeated to the frequency improving DCO
Going out scope, it adjusts delay time according to two groups of coarse adjustment control words and adjusts frequency and the phase place of output clock, and exports the upper limit
Amplitude signal UPPER and Lower Limit Amplitude signal LOWER.Fine tuning time delay electronic circuit 312 uses interpolation technique to improve what DCO differentiated
Resolution, it adjusts upper limit magnitude signal UPPER and the resolution of Lower Limit Amplitude signal LOWER according to coarse control word and exports
Corresponding oscillator signal Out_DCO.Phase inverter 313 is for by anti-phase for oscillator signal Out_DCO i.e. exportable output clock Out_
CLK。
Described coarse adjustment time delay electronic circuit includes the first switch IS1(tristate inverter), second switch IS2, the 3rd switch
IS3, the 4th switch IS4, the 5th switch IS5, the 6th switch IS6, the first main phase inverter IM1, the second main phase inverter IM2, the 3rd
Main phase inverter IM3, the 4th main phase inverter IM4, the 5th main phase inverter IM5, the 6th main phase inverter IM6, the 7th main phase inverter IM7,
8th main phase inverter IM8, the 9th main phase inverter IM9, the tenth main phase inverter IM10, the 11st main phase inverter IM11, the first compensation
Inverter ic the 1, second compensated inverter IC2, the 3rd compensated inverter IC3, the 4th compensated inverter IC4, the 5th compensate anti-phase
Device IC5, the 6th compensated inverter IC6, the 7th compensated inverter IC7, the 8th compensated inverter IC8, the 9th compensated inverter
IC9, the tenth compensated inverter IC10, the 11st compensated inverter IC11 and the 8th NAND gate S8.
One input of described 8th NAND gate S8 connects input and the fine tuning time delay electricity of the first compensated inverter IC1
Road 312, another input input reset signal of the 8th NAND gate S8；The outfan of the 8th NAND gate S8 connects the first switch
The input of IS1, the input of the first main phase inverter IM1 and the input of the 3rd compensated inverter IC3；First main phase inverter
The outfan of IM1 connects the input of the second main phase inverter IM2, the outfan of the first compensated inverter IC1 and second and compensates anti-
The input of phase device IC2；The outfan of the second main phase inverter IM2 connects the input of the 3rd main phase inverter IM3, the 3rd compensation instead
The outfan of phase device IC3, the input of the 4th compensated inverter IC4 and the input of second switch IS2；3rd main phase inverter
The outfan of IM3 connects the input of the 4th main phase inverter IM4, the outfan of the second compensated inverter IC2 and the 5th and compensates anti-
The input of phase device IC5；The outfan of the 4th main phase inverter IM4 connects the input of the 5th main phase inverter IM5, the 4th compensation instead
The outfan of phase device IC4, the input of the 3rd switch IS3 and the input of the 7th compensated inverter IC7；5th main phase inverter
The outfan of IM5 connects the input of the 6th main phase inverter IM6, the outfan of the 5th compensated inverter IC5 and the 6th and compensates anti-
The input of phase device IC6；The outfan of the 6th main phase inverter IM6 connects the input of the 7th main phase inverter IM7, the 7th compensation instead
The outfan of phase device IC7, the input of the 4th switch IS4 and the input of the 8th compensated inverter IC8；7th main phase inverter
The outfan of IM7 connects the input of the 8th main phase inverter IM8, the outfan of the 6th compensated inverter IC6 and the 9th and compensates anti-
The input of phase device IC9；The outfan of the 8th main phase inverter IM8 connects the input of the 9th main phase inverter IM9, the 8th compensation instead
The outfan of phase device IC8, the input of the 5th switch IS5 and the input of the 11st compensated inverter IC11；9th is main anti-phase
The outfan of device IM9 connects the input of the tenth main phase inverter IM10, the outfan of the 9th compensated inverter IC9 and the tenth and compensates
The input of inverter ic 10；The outfan of the tenth main phase inverter IM10 connect the input of the 11st main phase inverter IM11, the
The outfan of 11 compensated inverter IC11 and the input of the 6th switch IS6；The outfan of the 11st main phase inverter IM11 is even
Connect the outfan of the tenth compensated inverter IC10；First switch IS1, second switch IS2, the 3rd switch IS3, the 4th switch IS4,
5th switch IS5, the control end of the 6th switch IS6 are all connected with DCO decoder 310(L [2:0], U [2:0])；First switch IS1,
3rd switch IS3, the outfan of the 5th switch IS5 are all connected and connect one end of fine tuning time delay electronic circuit 312；Second switch
IS2, the 4th switch IS4, the outfan of the 6th switch IS6 are all connected and connect the other end of fine tuning time delay electronic circuit 312.
Wherein, as shown in dotted outline in FIG., the time delay of a delay unit is 112ps to delay unit.In order to make numerical control shake
Swinging device and can possess reset function, the phase inverter of first delay unit has changed NAND gate (S8) into.During the work of coarse adjustment time delay chain
Adjacent two switch can only be selected every time to open, be so to prevent DCO output frequency from undergoing mutation.As switch IS1(L
[0]) and IS2(U [0]) open other switches when all closing, the transmission delay of coarse adjustment time delay chain is minimum, the output frequency of DCO circuit
Rate is the highest.When switching IS5(L [2]) and IS6(U [2]) open other switches when all closing, the time delay of time delay chain is maximum, and DCO is electric
The output frequency on road is minimum.
The present embodiment is provided with 5 coarse adjustment frequency ranges of choice.The effect of the compensated inverter in coarse adjustment time delay chain is
Suppression power supply noise.When compensated inverter time delay is changed equal with the change of two main phase inverter time delays by power supply noise,
Two contrary polarity of voltages just can offset the power supply noise impact on digital controlled oscillator.Compensated inverter not only can be offset
The impact of power supply noise, also will not destroy the absolute time delay of main phase inverter, because when main phase inverter fast driving node is turned to
During opposite polarity, compensated inverter transfers the most completely.The DCO Module nodes of this structure is little to internodal time delay,
Because the amplitude of oscillation that when signal transmits on this chain, the amplitude of oscillation is slightly less than between power supply and ground, the agitator of the most this structure is permissible
Export higher frequency.In the case of meeting compensation condition, the size of compensated inverter is the least, DCO module (agitator)
Output frequency is the highest.
(representing with I in Fig. 9, a positive input, one anti-phase rear defeated by tristate inverter for fine tuning time delay electronic circuit 312
Enter) composition.Fine tuning time delay electronic circuit 312 is the resolution in order to improve designed DCO module, sees also Figure 10, described
Fine tuning time delay electronic circuit 312 includes 7 tristate inverters (I1 ~ I7, control signal positive inputs) and 7 anti-phase phase inverters of tri-state
(Iv1 ~ Iv7, control signal anti-phase input control there is anti-phase mark (circle) on end).1 tristate inverter and 1 tri-state are anti-
Phase phase inverter forms one group (shown in dotted line), then have 7 groups；Often in group, control end and the tri-state of tristate inverter are anti-phase
The control end of device is connected, and in one group, the control end of tristate inverter connects positive source VDD；Tristate inverter in remaining 6 groups
Control end and be all connected with DCO decoder, respectively one coarse control word (F [0] ~ F [5]) of input；Often tristate inverter in group (I1 ~
I7) input is all connected with the outfan of the first switch IS1, and the input of the anti-phase phase inverter of tri-state (Iv1 ~ Iv7) is all connected with
The outfan of two switch IS2；Often in group, the outfan of tristate inverter (I1 ~ I7) connects the anti-phase phase inverter of tri-state (Iv1 ~ Iv7)
Outfan；The outfan of the tristate inverter (I1 ~ I7) of each group is all connected and connects phase inverter 313, outputting oscillation signal
Out_DCO.Oscillator signal Out_DCO output output clock Out_CLK after phase inverter 313 is anti-phase again.
Use this structure to be because interpolation technique can be easy to change path delay.Number on tristate inverter in figure
What word represented is the weight of tristate inverter size, the size (WP/ of the tristate inverter that such as one control word F [0] controls
WN, WP are the sizes of PMOS, and WN is the size of NMOS tube) it is 2, then the size of the tristate inverter that control word F [1] controls
(WP/WN) being 4, the size (WP/WN) of the tristate inverter that control word F [5] controls is 64 by that analogy.Coarse control word F [5:
0] being simple binary code, the complexity which decreasing circuit decreases chip area and power consumption.
Coarse adjustment control word in DCO circuit is L [2:0] and U [2:0], and coarse adjustment can only gate two adjacent switches every time,
Therefore coarse adjustment has L [0] U [0], U [0] L [1], L [1] U [1], U [1] L [2], L [2] U [2] five kinds combination.Coarse control word F
[5:0] is the binary system of six bits, therefore has again 64 point of adjustment in each coarse adjustment range.So whole DCO circuit has
320 rate-adaptive pacemaker points, therefore wave filter needs the control word exporting 9 to decode these coarse adjustment coarse control word of generation.
In sum, the present invention, in all-digital phase-locked loop designs, arranges sense amplifier in PFD circuit (phase discriminator)
(SAFF) replacing conventional transmission door trigger, sense amplifier D-flip flop has negative sets up the time, it is possible to effectively reduces and builds
Impact on phase discriminator between immediately, improves the timing performance of phase discriminator and improves the accurate of phase discriminator differential phase error
Degree.
It is an important performance indexes of phaselocked loop based on shake, in order to allow the jitter performance of all-digital phase-locked loop can be with
The jitter performance of analog phase-locked look matches in excellence or beauty, and is provided with full custom high-resolution subset index TDC based on time amplifier, thus carries
High TDC and DCO resolution, reduces the quantization error of phase-locked loop systems, and the output successfully reducing all-digital phase-locked loop is trembled
Dynamic so that TDC resolution reaches 1.25ps, and has the dynamic range of 2.5ns.
In order to improve the range of application of phaselocked loop, widen the capture frequency scope of phaselocked loop, be provided with based on cascade structure
The DCO circuit that output frequency is high, scope is wide.DCO is divided into coarse adjustment and fine tuning two-stage, and coarse adjustment uses delay path selection technique to expand
DCO reference frequency output, fine tuning uses interpolation technique to improve the resolution of DCO.Designed DCO is made to have good dullness
Property, the surge frequency range of output is 500MHz-1.55GHz, and resolution is 1-8ps.
It is understood that for those of ordinary skills, can be according to technical scheme and send out
Bright design in addition equivalent or change, and all these change or replace the guarantor that all should belong to appended claims of the invention
Protect scope.
Claims (9)
1. the all-digital phase-locked loop of a low jitter width capture frequency scope, it is characterised in that include TDC module, digital filtering
Device, DCO module, two-divider and variable mould frequency divider；
Described TDC module compares the reference clock of input and the phase place of feedback clock, the phase error signal of output numeral；Numeral
Phase error signal is converted to one group of control word by wave filter, and DCO module adjusts the frequency of output clock according to this group control word
And phase place；Two-divider will output clock frequency reduce half, then by variable mould frequency divider according to default modulus value frequency dividing after
Generate feedback clock to continue to compare to TDC module；
Circulation is until reference clock is consistent with the frequency of feedback clock according to this, when phase place reaches to preset error, and all-digital phase-locked loop
Locking.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 1, it is characterised in that described
TDC module includes PFD circuit, integer TDC, decimal TDC and decoder:
Described PFD circuit comparison reference clock and the phase place of feedback clock, output phase error initial signal and phase error are eventually
Stop signal；The phase error resolution with integer TDC is judged according to phase error initial signal and phase error termination signal
Size, and corresponding selection integer TDC works or decimal TDC work；
The thermometer code of one group 31 is exported during integer TDC work；The one-hot encoding of output 7 during decimal TDC work；
The thermometer code of described 31 is converted to the high 5 of phase error signal by decoder, removes last position of one-hot encoding
After be converted to the low 6 of phase error signal, output phase error signal after integration.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 2, it is characterised in that described
When PFD circuit judges phase error is more than the resolution of integer TDC, control integer TDC work；Phase error is less than integer TDC
Resolution time, control decimal TDC work；
Described phase error is the pulse between phase error initial signal and adjacent two rising edges of phase error termination signal
Length.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 1, it is characterised in that described
DCO module includes:
DCO decoder, for generating two groups of coarse adjustment control words and one group of coarse control word according to control word；
DCO circuit, for adjusting frequency and the phase place of output clock according to two groups of coarse adjustment control words, adjusts according to coarse control word
The resolution of DCO module.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 4, it is characterised in that described
DCO circuit includes:
Coarse adjustment time delay electronic circuit, adjusts frequency and the phase of output clock for adjusting delay time according to two groups of coarse adjustment control words
Position, and export upper limit magnitude signal and Lower Limit Amplitude signal；
Fine tuning time delay electronic circuit, for adjusting the resolution of upper limit magnitude signal and Lower Limit Amplitude signal also according to coarse control word
The oscillator signal that output is corresponding；
Phase inverter, for by anti-phase for oscillator signal output output clock.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 2, it is characterised in that described
PFD circuit include the first trigger, the second trigger, first with door, second with door, the first NAND gate, the second NAND gate, the 3rd
NAND gate, the 4th NAND gate, the 5th NAND gate, the 6th NAND gate, the 7th NAND gate and NAND gate group；Described first trigger and
The D foot of the second trigger is all connected with positive source, and the CK foot of the first trigger connects reference clock；The Q foot of the first trigger is even
Connect the first input end of NAND gate group, an input of the first NAND gate and an input of the 5th NAND gate；First trigger
Rst foot connect the Rst foot of the second trigger and first with the outfan of door, the CK foot of the second trigger connects feedback clock；
The Q foot of the second trigger connect second with another of an input of door, an input of the 4th NAND gate and the 5th NAND gate
Input；The outfan of the 5th NAND gate connects an input of first and door, and first is outside with another input input of door
Reset signal, an input of the 5th NAND gate connect second with another input of door and an input of the 3rd NAND gate
End, second is connected digital filter with the outfan of door, and the second of another input connection NAND gate group of the 5th NAND gate is defeated
Enter an input of end and the second NAND gate；First outfan of NAND gate group connect another input of the first NAND gate,
Another input of four NAND gate and digital filter；Second outfan of NAND gate group connects another input of the second NAND gate
End and an input of the 3rd NAND gate, the outfan of the first NAND gate connects an input of the 6th NAND gate, and second with non-
The outfan of door connects another input of the 6th NAND gate, and the outfan of the 6th NAND gate connects integer TDC and decimal TDC,
The outfan of the 3rd NAND gate connects an input of the 7th NAND gate, and the outfan of the 4th NAND gate connects the 7th NAND gate
Another input, the outfan of the 7th NAND gate connects integer TDC and decimal TDC.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 6, it is characterised in that described
One trigger, the second trigger are the trigger of sense amplifier type.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 6, it is characterised in that described whole
Number TDC include the 3rd with door, 31 d type flip flops and 31 chronotron；Described 31 chronotron are connected into gate delay chain, and described
Three are connected the outfan of the 6th NAND gate with an input of door, and the 3rd is connected decimal TDC with another input of door, the 3rd with
The outfan of door connects the input of first chronotron, and the D foot of each chronotron connects one to one with the input of each d type flip flop
Connecing, the CK foot of each d type flip flop is all connected with the outfan of the 7th NAND gate；The Q foot of each d type flip flop connects decoder, exports 31
Thermometer code.
The all-digital phase-locked loop of low jitter width capture frequency scope the most according to claim 8, it is characterised in that described little
Number TDC include the first amplifier, the second amplifier, the 3rd amplifier, the 4th amplifier, the 5th amplifier, the 6th amplifier, the
Seven amplifiers, the first integer detector, the second integer detector, the 3rd integer detector, the 4th integer detector, the 5th integer
Detector, the 6th integer detector, the 7th integer detector, the first XOR gate, the second XOR gate, the 3rd XOR gate, the 4th different
Or door, the 5th XOR gate, the 6th XOR gate and the 7th XOR gate；
One input of described first amplifier connects outfan and an input of the first integer detector of the 6th NAND gate,
The outfan of another input connection the 7th NAND gate of the first amplifier and another input of the first integer detector, first
The outfan of integer detector connects another input of the 3rd and door, and an outfan of the first amplifier connects the second amplifier
An input and an input of the second integer detector, another outfan of the first amplifier connects the another of the second amplifier
One input and another input of the second integer detector, the one of outfan connection the 3rd amplifier of the second amplifier is defeated
Entering an input of end and the 3rd integer detector, another outfan of the second amplifier connects another input of the 3rd amplifier
End and another input of the 3rd integer detector, an outfan of the 3rd amplifier connect the 4th amplifier an input and
One input of the 4th integer detector, another outfan of the 3rd amplifier connects another input and the of the 4th amplifier
Another input of four integer detectors, an outfan of the 4th amplifier connects an input of the 5th amplifier and the 5th whole
One input of number detector, another outfan of the 4th amplifier connects another input and the 5th integer of the 5th amplifier
Another input of detector, an outfan of the 5th amplifier connects an input and the detection of the 6th integer of the 6th amplifier
One input of device, another outfan of the 5th amplifier connects another input and the 6th integer detector of the 6th amplifier
Another input, the 6th amplifier one outfan connect the 7th amplifier an input and the one of the 7th integer detector
Input, another outfan of the 6th amplifier connects another of another input of the 7th amplifier and the 7th integer detector
Input, one end power cathode of the first XOR gate, the outfan of the second integer detector connects the other end of the first XOR gate
With one end of the second XOR gate, the outfan of the 3rd integer detector connects the other end of the second XOR gate and the 3rd XOR gate
One end, the outfan of the 4th integer detector connects the other end and one end of the 4th XOR gate, the 5th integer of the 3rd XOR gate
The outfan of detector connects the other end and one end of the 5th XOR gate, the outfan of the 6th integer detector of the 4th XOR gate
Connecting the other end and one end of the 6th XOR gate of the 5th XOR gate, the outfan of the 7th integer detector connects the 6th XOR gate
The other end and one end of the 7th XOR gate, the other end of the 7th XOR gate connects positive source；The outfan of each XOR gate is even
Connect decoder, export the one-hot encoding of 7.
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| CN109600126A (en) * | 2018-12-06 | 2019-04-09 | 中国科学院微电子研究所 | A kind of clock generator |
| CN109600126B (en) * | 2018-12-06 | 2023-02-28 | 中国科学院微电子研究所 | Clock generator |
| CN109698697A (en) * | 2018-12-29 | 2019-04-30 | 西安智多晶微电子有限公司 | A kind of phase-locked loop apparatus and fpga chip applied to fpga chip |
| CN109698697B (en) * | 2018-12-29 | 2023-11-14 | 西安智多晶微电子有限公司 | Phase-locked loop device applied to FPGA chip and FPGA chip |
| CN111934674A (en) * | 2020-08-20 | 2020-11-13 | 成都海光微电子技术有限公司 | Error calibration device and method, phase-locked loop and chip |
| WO2022232982A1 (en) * | 2021-05-06 | 2022-11-10 | Micron Technology, Inc. | Systems having a phase frequency detector |
| CN114726368A (en) * | 2022-06-08 | 2022-07-08 | 成都世源频控技术股份有限公司 | Low-phase noise loop and loop presetting method using same |
| CN116243585A (en) * | 2023-05-12 | 2023-06-09 | 江苏润石科技有限公司 | First jump signal output circuit in ring vernier time digital converter |
| CN116243585B (en) * | 2023-05-12 | 2023-07-18 | 江苏润石科技有限公司 | First jump signal output circuit in ring vernier time digital converter |
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