CN108923782B - All-digital phase-locked loop and rapid phase locking method thereof - Google Patents
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Abstract
The invention discloses an all-digital phase-locked loop and a rapid phase-locking method thereof, wherein the rapid phase-locking method detects whether the falling edge of the currently input reference signal arrives, and a numerically-controlled oscillator outputs a reconstruction signal when the falling edge of the reference signal arrives; comparing the frequency of the reconstructed signal with the frequency of a reference signal after frequency division is carried out on the reconstructed signal, and outputting a corresponding level signal according to a comparison result; the value of the frequency control word is roughly adjusted according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal; when the coarse adjustment times reach the preset times, the value of the frequency control word is finely adjusted according to the phase relation between the reconstruction signal and the reference signal, so that the frequency of the reconstruction signal after frequency division is equal to the frequency of the reference signal, the all-digital phase-locked loop enters a locking state, the locking time of the phase-locked loop is only related to the output frequency range and precision, the search times are effectively reduced through the coarse adjustment and the fine adjustment with different step lengths, and the locking time is reduced to realize quick phase locking.
Description
Technical Field
The invention relates to the technical field of phase-locked loops, in particular to an all-digital phase-locked loop and a rapid phase-locking method thereof.
Background
A Phase-Locked Loop (PLL) is a negative feedback control circuit that can automatically track an input signal. The phase lock, as the name implies, is to automatically adjust the phase by using the phase difference between the input and output signals, so that the frequency of the output signal automatically tracks the frequency of the input signal, thereby finally completing the functions of phase synchronization and frequency automatic tracking between the two signals. The phase locking technique is an important automatic feedback control technique, and is widely applied in many fields, such as instruments and meters, communication, digital signal processing and the like.
The current fully integrated transceiver SOC is rapidly developing towards multimode, multifunction, low voltage and low power consumption, and the advanced CMOS process adopting the feature size of the transistor to be continuously reduced has become a mainstream choice of the current radio frequency integrated circuit design, and has the advantages of not only having a device with higher cut-off frequency for selection, but also being beneficial to further improving the system integration level, and being capable of arranging more modules on the same chip to complete more functions. However, as the power supply voltage of the core device is continuously reduced, the design difficulty of the pll frequency synthesizer as a key module therein is also continuously increased, and new problems and new challenges to be dealt with are also continuously raised. In particular, how to implement a pll frequency synthesizer with high integration, high spectral purity, high frequency resolution, wide output frequency coverage and fast locking has become a bottleneck problem that restricts the performance of an integrated wireless communication system. This problem has attracted extensive attention from both academic and industrial fields as a common challenge to designers of rf integrated circuits, and has become a hot research direction.
At present, there are many techniques applied to fast locking, such as increasing the reference clock frequency, loop bandwidth adaptive technique, feed forward compensation technique, and frequency control word preset technique, etc., and the locking time of the All Digital Phase Locked Loop (ADPLL) with the conventional structure is related to the frequency range of the output, the filter bandwidth, the target frequency and the frequency precision, and the larger the output frequency range is, the smaller the filter bandwidth is, the farther the target frequency is from the starting frequency, and the higher the frequency precision is, the longer the locking time is, thereby limiting the development of the fast phase locking technique.
Thus, the prior art has yet to be improved and enhanced.
Disclosure of Invention
In view of the above disadvantages of the prior art, the present invention provides an all-digital phase-locked loop and a fast phase-locking method thereof, so that the locking time of the phase-locked loop is only related to the frequency range and precision of the output, and the search times are effectively reduced by coarse adjustment and fine adjustment with different step lengths, and the fast phase-locking is realized by reducing the locking time.
In order to achieve the purpose, the invention adopts the following technical scheme:
a fast phase locking method of an all-digital phase-locked loop comprises the following steps:
detecting whether a falling edge of a currently input reference signal arrives, and outputting a reconstructed signal by the numerically-controlled oscillator when the falling edge of the reference signal arrives;
comparing the frequency of the reconstructed signal with the frequency of a reference signal after frequency division is carried out on the reconstructed signal, and outputting a corresponding level signal according to a comparison result;
the value of the frequency control word is roughly adjusted according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal;
and when the coarse tuning frequency reaches a preset frequency, finely tuning the value of the frequency control word according to the phase relation between the reconstruction signal and the reference signal to enable the frequency of the frequency-divided reconstruction signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state.
In the fast phase-locking method of the all-digital phase-locked loop, before the step of detecting whether a falling edge of a currently input reference signal arrives and controlling the digital oscillator to output a reconstruction signal when the falling edge of the reference signal arrives, the method further comprises: and detecting whether a reset signal is received currently, and if not, detecting whether the falling edge of the currently input reference signal arrives.
In the fast phase-locking method of the all-digital phase-locked loop, the step of comparing the frequency of the reference signal with the frequency of the reconstructed signal after frequency division and outputting a corresponding level signal according to a comparison result specifically includes:
comparing the frequency of the reconstructed signal with the frequency of the reference signal after frequency division of the reconstructed signal, and outputting a high-level signal when the frequency of the reference signal is greater than the frequency of the reconstructed signal; and outputting a low-level signal when the frequency of the reference signal is less than that of the reconstructed signal.
In the fast phase-locking method of the all-digital phase-locked loop, the step of coarsely adjusting the value of the frequency control word according to the level signal and a preset rule to adjust the output frequency of the reconstructed signal specifically includes:
when a high level signal is output, increasing the value of the frequency control word according to a preset rule; when a low level signal is output, the value of the frequency control word is reduced according to a preset rule to adjust the output frequency of the reconstructed signal.
In the fast phase-locking method of the all-digital phase-locked loop, the step of increasing the value of the frequency control word according to a preset rule when outputting a high-level signal specifically comprises:
when a high level signal is output, the value of the frequency control word is increased by half the difference between the maximum value of the frequency control word and the value of the current frequency control word, and the updated value of the frequency control word is assigned to the minimum value of the frequency control word.
In the fast phase-locking method of the all-digital phase-locked loop, when a low-level signal is output, the step of reducing the value of the frequency control word according to a preset rule specifically includes:
when a low level signal is output, the value of the frequency control word is reduced by half the difference between the value of the current frequency control word and the minimum value of the frequency control word, and the updated value of the frequency control word is assigned to the maximum value of the frequency control word.
In the fast phase-locking method of the all-digital phase-locked loop, after the step of coarsely adjusting the value of the frequency control word according to the level signal and a preset rule to adjust the output frequency of the reconstructed signal, the method further comprises:
and adding one to the hopping times every time the frequency control word hopping is finished, judging whether the current hopping times are larger than or equal to the preset times, if so, outputting a mode switching signal to enter a fine tuning mode, and otherwise, outputting a mode maintaining signal to continuously maintain the coarse tuning mode.
In the fast phase-locking method of the all-digital phase-locked loop, when the coarse tuning frequency reaches a preset frequency, the value of the frequency control word is finely tuned according to the phase relation between the reconstruction signal and the reference signal, so that the frequency of the frequency-divided reconstruction signal is equal to the frequency of the reference signal, and the step of the all-digital phase-locked loop entering a locking state includes:
when the coarse adjustment times reach preset times, judging whether the phase relation between the reconstruction signal and the reference signal changes, if so, recording the values of the corresponding frequency control words when the phase relation changes for a plurality of times;
calculating the average value of the corresponding frequency control word when the phase relation changes for a plurality of times, and taking the average value as the value of the current frequency control word;
and finely adjusting the value of the frequency control word according to the phase relation between the reconstructed signal and the reference signal to ensure that the frequency of the frequency-divided reconstructed signal is equal to that of the reference signal, and enabling the all-digital phase-locked loop to enter a locking state.
In the fast phase locking method of the all-digital phase-locked loop, the preset times are 10 times.
An all-digital phase-locked loop using the fast phase-locking method as described above, comprising:
a numerically controlled oscillator for outputting a reconstructed signal when a falling edge of the reference signal comes;
the frequency division module is used for carrying out frequency division on the reconstructed signal;
the frequency comparison module is used for comparing the frequency of the frequency-divided reconstructed signal with the frequency of the reference signal and outputting a corresponding level signal according to a comparison result;
the control module is used for roughly adjusting the value of the frequency control word according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal; and when the coarse tuning frequency reaches a preset frequency, finely tuning the value of the frequency control word according to the phase relation between the reconstruction signal and the reference signal to enable the frequency of the frequency-divided reconstruction signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state.
Compared with the prior art, in the all-digital phase-locked loop and the fast phase-locking method thereof provided by the invention, the fast phase-locking method detects whether the falling edge of the currently input reference signal arrives, and the time-controlled oscillator outputs a reconstruction signal when the falling edge of the reference signal arrives; comparing the frequency of the reconstructed signal with the frequency of a reference signal after frequency division is carried out on the reconstructed signal, and outputting a corresponding level signal according to a comparison result; the value of the frequency control word is roughly adjusted according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal; when the coarse adjustment times reach the preset times, the value of the frequency control word is finely adjusted according to the phase relation between the reconstruction signal and the reference signal, so that the frequency of the reconstruction signal after frequency division is equal to the frequency of the reference signal, the all-digital phase-locked loop enters a locking state, the locking time of the phase-locked loop is only related to the output frequency range and precision, the search times are effectively reduced through the coarse adjustment and the fine adjustment with different step lengths, and the locking time is reduced to realize quick phase locking.
Drawings
Fig. 1 is a flowchart of a fast phase-locking method for an adpll according to the present invention.
Fig. 2 is a schematic diagram illustrating a frequency comparison between a reference signal and a reconstructed signal in the fast phase-locking method of an adpll provided by the present invention.
Fig. 3 (a) is a schematic diagram of a locking process of a phase-locked loop in the prior art.
FIG. 3 (b) is a schematic diagram of the locking process of the fast phase-locking method of the ADPLL according to the present invention
Fig. 4 is a flowchart of an embodiment of a fast phase-locking method for an adpll according to the invention.
Fig. 5 is a simulated waveform diagram of capturing a 2.24G clock by the fast phase-locking method of the adpll provided by the invention.
Fig. 6 is a block diagram of an adpll according to the present invention.
Detailed Description
In view of the disadvantages in the prior art that the locking time of a phase-locked loop is related to the output frequency range, the filter loan' target frequency and frequency progress, and the locking time is affected, the invention aims to provide an all-digital phase-locked loop and a rapid phase-locking method thereof, so that the locking time of the phase-locked loop is only related to the output frequency range and precision, the search times are effectively reduced through coarse adjustment and fine adjustment with different step lengths, and the locking time is reduced to realize rapid phase-locking.
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the fast phase-locking method of the adpll provided by the present invention includes the following steps:
s100, detecting whether a falling edge of a currently input reference signal comes, and outputting a reconstructed signal by a numerically-controlled oscillator when the falling edge of the reference signal comes;
s200, comparing the frequency of the reconstructed signal with the frequency of a reference signal after frequency division is carried out on the reconstructed signal, and outputting a corresponding level signal according to a comparison result;
s300, roughly adjusting the value of the frequency control word according to the level signal and a preset rule to adjust the output frequency of the reconstructed signal;
s400, when the coarse adjustment times reach preset times, finely adjusting the value of the frequency control word according to the phase relation between the reconstruction signal and the reference signal to enable the frequency of the frequency-divided reconstruction signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state.
The invention provides a fast phase locking method of an all-digital phase-locked loop, which firstly detects whether the falling edge of the currently input reference signal arrives, if the falling edge does not arrive, the numerical control oscillator is in a reset state and does not work, when the falling edge of the reference signal arrives, the numerical control oscillator starts working to generate a reconstruction signal, then the reconstruction signal is subjected to frequency division processing and then is compared with the frequency of the reference signal, a corresponding level signal is output according to the comparison result, then frequency hopping is carried out according to the level signal and the value of a preset rule coarse tuning frequency control word to adjust the output frequency of the reconstruction signal, after coarse tuning of preset times is carried out according to the number of all frequency control words of the numerical control oscillator, namely when the coarse tuning times reach the preset times, the value of the frequency control word is finely tuned according to the phase relation between the reconstruction signal and the reference signal so that the frequency of the frequency-divided reconstruction signal is equal to the frequency of the reference signal, the all-digital phase-locked loop enters a locking state, the quick phase-locking method provided by the invention ensures that the locking time is only related to the output frequency range and precision, and the search times are effectively reduced through coarse adjustment and fine adjustment of different step lengths, so that the locking time is reduced and the quick phase-locking is realized.
Preferably, the step S100 further comprises the steps of: s110, detecting whether a reset signal is received currently, and if not, detecting whether the falling edge of the currently input reference signal arrives.
After the all-digital phase-locked loop starts to work, the reset signal judgment circuit is firstly checked to judge whether the circuit is reset or not, if the circuit is reset, the phase-locked loop does not work, the subsequent process of detecting the falling edge of the reference signal is not carried out, if the reset signal is not received, whether the falling edge of the currently input reference signal comes or not is detected, and the working accuracy and stability of the phase-locked loop are ensured.
Specifically, when performing frequency comparison, the step S200 specifically includes: comparing the frequency of the reconstructed signal with the frequency of the reference signal after frequency division of the reconstructed signal, and outputting a high-level signal when the frequency of the reference signal is greater than the frequency of the reconstructed signal; and outputting a low-level signal when the frequency of the reference signal is less than that of the reconstructed signal.
In this embodiment, when performing frequency comparison, a high level signal is output when the frequency of the reference signal is greater than the frequency of the reconstructed signal; as the digitally controlled oscillator is in the reset state and does not work when the reference signal is at the high level, the reset state is finished when the falling edge of the reference signal comes, and the digitally controlled oscillator starts to work to output the reconstructed signal, when the frequency comparison is performed, only the rising edge of the reference signal needs to be compared with the rising edge of the reconstructed signal, and when the rising edge of the reference signal comes first, the frequency of the reference signal is greater than the frequency of the reconstructed signal, and the output result signal is at the high level; when the rising edge of the reconstructed signal comes first, it means that the frequency of the reference signal is smaller than that of the reconstructed signal, and the output result signal is low level, as shown in fig. 2, by the above comparison method, it can be accurately and directly determined that the frequency of the reconstructed signal 1 is smaller than that of the reference signal, and the frequency of the reconstructed signal 2 is greater than that of the reference signal, so as to implement accurate and efficient frequency comparison, thereby outputting an accurate comparison result for subsequent frequency locking.
Further, after obtaining the frequency comparison result, the step S300 specifically includes: when a high level signal is output, increasing the value of the frequency control word according to a preset rule; when a low level signal is output, the value of the frequency control word is reduced according to a preset rule to adjust the output frequency of the reconstructed signal.
In this embodiment, after performing frequency comparison to obtain a level signal, when a high level signal is output, which indicates that the frequency of the reference signal is greater than the frequency of the reconstructed signal at this time, the value of the frequency control word is increased according to a preset rule, so that the frequency control word jumps to a high frequency; when a low-level signal is output, the frequency of the reference signal is smaller than the frequency of the reconstructed signal at the moment, the value of the frequency control word is reduced according to a preset rule, the frequency control word jumps to a low frequency position to adjust the output frequency of the reconstructed signal, the frequency coarse adjustment process is completed, the output frequency of the reconstructed signal can quickly approach the target frequency, and the frequency locking speed is improved.
Specifically, in the step of increasing the value of the frequency control word according to a preset rule when a high-level signal is output, increasing the value of the frequency control word by half of the difference between the maximum value of the frequency control word and the value of the current frequency control word when the high-level signal is output, and assigning the updated value of the frequency control word to the minimum value of the frequency control word; and when a low level signal is output, reducing the value of the frequency control word according to a preset rule, and when the low level signal is output, reducing the value of the frequency control word by half of the difference between the value of the current frequency control word and the minimum value of the frequency control word, and assigning the updated value of the frequency control word to the maximum value of the frequency control word.
I.e. when embodied, the value of the frequency control word P is adjusted according to the output result of the frequency comparison, and when the comparison result is high, the reference signal is asserted
Is greater than the reconstructed signal
The control frequency control word P increases by the maximum value of the control frequency word
Half of the difference with the current frequency control word P, and assigning the value of the updated frequency control word to the minimum value of the frequency control word
As shown in equation (1):
and when the comparison result is low level, the reference signal
Is less than the reconstructed signal
The control frequency control word P is decreased by the current frequency control word P and the minimum value of the frequency control word P
And assigning the updated value of the frequency control word to the maximum value of the frequency control word
As shown in equation (2):
referring to fig. 3, in the conventional pll locking process, as shown in fig. 2 (a), at the beginning, a target frequency is gradually approached in a certain step length according to the loop bandwidth, the detection range of the time-to-digital converter, the resolution of the digital controlled oscillator, and other factors, and after the target frequency is approached, the pll is wobbled around the target frequency to approach the target frequency. The disadvantage of this mode is that the lock time of the phase locked loop is related to the bandwidth of the loop, the frequency range of the output, the maximum step size when approaching the target frequency, the distance of the target frequency from the start frequency. The locking time is longer as the loop bandwidth is smaller, the maximum step size when the loop bandwidth is close to the maximum step size is smaller, the target frequency is farther from the starting frequency, and the output frequency range is larger.
The phase locking process of the fast phase locking method provided by the present invention, as shown in (b) of fig. 2, is based on the input reference signal
Reconstructed signal output by digital controlled oscillator
After frequency comparison is carried out, according to a comparison result, all frequency control words of the numerical control oscillator are used as a search range, half of the difference between the current frequency control word and the maximum or minimum frequency control word is used as a step length, frequency hopping is carried out, and the target frequency is approached.
Preferably, the step S300 further includes:
and S310, adding one to the jump frequency every time the frequency control word jumps, judging whether the current jump frequency is larger than or equal to a preset frequency, if so, outputting a mode switching signal to enter a fine tuning mode, and otherwise, outputting a mode maintaining signal to continuously maintain the coarse tuning mode.
In this example, the process was carried outAnd during frequency coarse tuning, adding one to the hopping frequency every time frequency control word hopping is completed, judging whether the current hopping frequency is greater than or equal to a preset frequency before frequency hopping is performed every time, if so, outputting a mode switching signal to enter a fine tuning mode, and reducing the frequency hopping step length, otherwise, outputting a mode maintaining signal to continuously maintain a coarse tuning mode so as to quickly approach the target frequency. In specific implementation, the numerically controlled oscillator can be divided into a coarse tuning module and a fine tuning module, and the coarse tuning module passes through two three-bit signals U2: 0]And L2: 0]To control, the fine-tuning module passes a six-bit signal F [5:0 ]]For example, in order to prevent the problem of abrupt frequency change of the output of the numerically controlled oscillator, the coarse tuning signal can only select two adjacent switches to be opened each time, 5 combinations are sequentially adopted for coarse tuning, 64 combinations are sequentially adopted for fine tuning, so the whole numerically controlled oscillator has 320 different frequency control words, and the frequency control words are different because the whole numerically controlled oscillator has the following characteristics
Therefore, in this embodiment, the preset number of times is selected to be 10 times, so as to complete the coarse adjustment control, enter the fine adjustment mode,
further, the step S400 includes:
s401, when the coarse adjustment times reach preset times, judging whether the phase relation between the reconstruction signal and the reference signal changes, if so, recording the values of corresponding frequency control words when the phase relation changes for a plurality of times;
s402, calculating the average value of the corresponding frequency control word when the phase relation changes for a plurality of times, and taking the average value as the value of the current frequency control word;
s403, fine-adjusting the value of the frequency control word according to the phase relation between the reconstructed signal and the reference signal to enable the frequency of the frequency-divided reconstructed signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state.
In this embodiment, after the coarse frequency adjustment for the preset number of times is completed, the method enters a fine adjustment mode, fine adjustment is performed on the frequency of the reconstructed signal, it is first determined whether the phase relationship between the reconstructed signal and the reference signal changes, if so, the values of the corresponding frequency control words when the phase relationship changes for several times are recorded, for example, when the phase relationship between the reconstructed signal and the reference signal changes for two times, the values of the two corresponding frequency control words when the phase relationship changes for two times are recorded, then an average value of the corresponding frequency control words when the phase relationship changes for several times is calculated, that is, the values of the two previously recorded frequency control words are taken as the current frequency control word, and then the values of the frequency control words are fine adjusted according to the phase relationship between the reconstructed signal and the reference signal so that the frequency of the frequency-divided reconstructed signal is equal to the frequency of the reference signal, and finishing the fine adjustment process to enable the all-digital phase-locked loop to enter a locking state, quickly approaching the target frequency through the coarse adjustment process, and then finely adjusting the frequency to quickly finish the phase locking process, thereby greatly improving the working efficiency of the phase-locked loop.
The phase locking process and simulation result of the fast phase locking method provided by the present invention are described below with reference to fig. 4 and 5 by way of example:
s1, checking the reset signal, judging whether the circuit is reset, if so, entering the step S2;
s2, detecting whether the falling edge of the reference signal comes, if the falling edge of the reference signal does not come, entering the step S3; if the falling edge of the reference signal arrives, the process proceeds to step S4;
s3, the numerically controlled oscillator is in a reset state and does not work;
s4, the numerical control oscillator starts to work to generate a reconstruction signal;
s5, comparing the frequencies of the reference signal and the reconstructed signal, judging whether the rising edge of the reference signal comes first, if so, entering the step S7, otherwise, entering the step S6;
s6, controlling the frequency control word to jump to the low frequency when the frequency of the reconstructed signal is larger than that of the reference signal;
s7, controlling the frequency control word to jump to a high frequency when the frequency of the reference signal is larger than that of the reconstruction signal;
s8, adding one to the jumping times after jumping is completed;
s9, judging whether the jumping times are more than 10; if yes, go to step S10, otherwise return to step S2;
s10, fine adjustment is carried out on the reconstruction signal;
s11, judging whether the phase relation between the reconstructed signal and the reference signal changes twice, if so, entering the step S12;
s12, recording the value of the frequency control word of the two phase relation changes, and taking the average value of the two values as the value of the current frequency control word;
and S13, finely adjusting the value of the frequency control word according to the phase relation between the reconstructed signal and the reference signal to enable the frequency of the frequency-divided reconstructed signal to be equal to that of the reference signal, and enabling the phase-locked loop to enter a locked state.
The simulation waveform is shown in fig. 5, the frequency range of the output of the reconstructed signal is 800 MHz-2.4 GHz, wherein the frequency division factor is 32, the 2.24GHz clock is captured, the coarse tuning mode is changed into the fine tuning mode at 230ns, and the whole circuit starts to lock at 590 ns. In the adpll using the conventional structure, 2400ns is required to capture a clock of 2.24GHz, and the lock time for capturing clocks of other frequencies is different. According to the rapid phase locking method provided by the invention, the locking time of all captured clocks is basically consistent, and about 72% of time is saved.
Based on the above fast phase-locking method of the all-digital phase-locked loop, the present invention further provides a corresponding all-digital phase-locked loop, which performs phase-locking by using the fast phase-locking method as described above, as shown in fig. 6, the all-digital phase-locked loop includes a numerically controlled oscillator 10, a frequency division module 20, a frequency comparison module 30, and a control module 40, the numerically controlled oscillator 10, the frequency division module 20, the frequency comparison module 30, and the control module 40 are sequentially connected, the control module 40 is further connected to the numerically controlled oscillator 10, wherein the numerically controlled oscillator 10 is configured to output a reconstruction signal when a falling edge of a reference signal comes; the frequency dividing module 20 is configured to frequency-divide the reconstructed signal; the frequency comparison module 30 is configured to compare the frequency of the frequency-divided reconstructed signal with the frequency of the reference signal, and output a corresponding level signal according to a comparison result; the control module 40 is configured to coarsely adjust the value of the frequency control word according to the level signal and a preset rule to adjust the output frequency of the reconstructed signal; and when the coarse tuning frequency reaches a preset frequency, finely tuning the value of the frequency control word according to the phase relation between the reconstruction signal and the reference signal to enable the frequency of the frequency-divided reconstruction signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state. Please refer to the corresponding embodiments of the above methods.
Further, the all-digital phase-locked loop further includes a coarse and fine adjustment judging module 50 and a DCO decoder 60, where the coarse and fine adjustment judging module 50 is connected to the control module 40, and is configured to add one to the number of hops each time the frequency control word hops is completed, judge whether the current number of hops is greater than or equal to a preset number, if so, output a mode switching signal to enter a fine adjustment mode, and otherwise, output a mode maintaining signal to continue to maintain a coarse adjustment mode. The DCO decoder 60 is connected to the control module 40 and the digitally controlled oscillator 10, and is configured to decode the control signal output by the control module 40 and output the control signal to the digitally controlled oscillator 10. Please refer to the corresponding embodiments of the above methods.
Furthermore, the frequency dividing module 20 includes a frequency divider 201 and a variable modulus frequency divider 202, the frequency divider 201 is connected to the variable modulus frequency divider 202, and the frequency divider and the variable modulus frequency divider 202 divide the frequency of the reconstructed signal to obtain a corresponding output frequency, where the frequency divider 201 can operate at a high frequency, the highest operating frequency is 2.7GHz, the variable modulus frequency divider 202 is an N-input even-numbered frequency divider, and the frequency division range can be from 2 to 30, which can be specifically selected according to actual needs.
In summary, in the all-digital phase-locked loop and the fast phase-locking method thereof provided by the present invention, the fast phase-locking method detects whether a falling edge of a currently input reference signal arrives, and outputs a reconstructed signal by a time-controlled oscillator when the falling edge of the reference signal arrives; comparing the frequency of the reconstructed signal with the frequency of a reference signal after frequency division is carried out on the reconstructed signal, and outputting a corresponding level signal according to a comparison result; the value of the frequency control word is roughly adjusted according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal; when the coarse adjustment times reach the preset times, the value of the frequency control word is finely adjusted according to the phase relation between the reconstruction signal and the reference signal, so that the frequency of the reconstruction signal after frequency division is equal to the frequency of the reference signal, the all-digital phase-locked loop enters a locking state, the locking time of the phase-locked loop is only related to the output frequency range and precision, the search times are effectively reduced through the coarse adjustment and the fine adjustment with different step lengths, and the locking time is reduced to realize quick phase locking.
It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.
Claims (6)
1. A fast phase locking method of an all-digital phase-locked loop is characterized by comprising the following steps:
detecting whether a falling edge of a currently input reference signal arrives, and outputting a reconstructed signal by the numerically-controlled oscillator when the falling edge of the reference signal arrives;
comparing the frequency of the reconstructed signal with the frequency of a reference signal after frequency division is carried out on the reconstructed signal, and outputting a corresponding level signal according to a comparison result;
the value of the frequency control word is roughly adjusted according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal;
when the coarse tuning frequency reaches a preset frequency, finely tuning the value of the frequency control word according to the phase relation between the reconstruction signal and the reference signal to enable the frequency of the frequency-divided reconstruction signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state;
the step of comparing the frequency of the reference signal with the frequency of the reconstructed signal after frequency division, and outputting a corresponding level signal according to a comparison result specifically includes: comparing the frequency of the reconstructed signal with the frequency of the reference signal after frequency division of the reconstructed signal, and outputting a high-level signal when the frequency of the reference signal is greater than the frequency of the reconstructed signal; outputting a low level signal when the frequency of the reference signal is less than the frequency of the reconstructed signal;
the step of roughly adjusting the value of the frequency control word according to the level signal and a preset rule to adjust the output frequency of the reconstructed signal specifically includes: when a high level signal is output, increasing the value of the frequency control word according to a preset rule; when a low level signal is output, reducing the value of the frequency control word according to a preset rule so as to adjust the output frequency of the reconstructed signal;
when a high-level signal is output, the step of increasing the value of the frequency control word according to a preset rule specifically includes: when a high-level signal is output, increasing the value of the frequency control word by half of the difference value between the maximum value of the frequency control word and the value of the current frequency control word, and assigning the updated value of the frequency control word to the minimum value of the frequency control word;
the step of reducing the value of the frequency control word according to a preset rule when outputting the low level signal specifically includes: when a low-level signal is output, reducing the value of the frequency control word by half of the difference value between the value of the current frequency control word and the minimum value of the frequency control word, and assigning the value of the updated frequency control word to the maximum value of the frequency control word;
after frequency comparison is carried out according to an input reference signal and a reconstructed signal output by the numerically controlled oscillator, according to a comparison result, all frequency control words of the numerically controlled oscillator are used as a search range, half of the difference between the current frequency control word and the maximum or minimum frequency control word is used as a step length, frequency hopping is carried out, and the target frequency is approximated, so that the locking time is irrelevant to the loop bandwidth, irrelevant to the size of the target frequency from the initial frequency and only relevant to the output frequency range and the resolution of the numerically controlled oscillator.
2. The fast phase-locking method for the adpll of claim 1, wherein the step of detecting whether a falling edge of a currently inputted reference signal arrives, and controlling the digital oscillator to output a reconstructed signal when the falling edge of the reference signal arrives further comprises: and detecting whether a reset signal is received currently, and if not, detecting whether the falling edge of the currently input reference signal arrives.
3. The fast phase-locking method for adpls of claim 1, wherein the step of coarsely adjusting the value of the frequency control word according to the level signal by a predetermined rule to adjust the output frequency of the reconstructed signal is followed by the step of:
and adding one to the hopping times every time the frequency control word hopping is finished, judging whether the current hopping times are larger than or equal to the preset times, if so, outputting a mode switching signal to enter a fine tuning mode, and otherwise, outputting a mode maintaining signal to continuously maintain the coarse tuning mode.
4. The fast phase-locking method of the adpll of claim 3, wherein when the coarse tuning frequency reaches a preset frequency, the fine tuning of the value of the frequency control word is performed according to the phase relationship between the reconstructed signal and the reference signal so that the frequency of the frequency-divided reconstructed signal is equal to the frequency of the reference signal, and the step of entering the adpll into the locked state comprises:
when the coarse adjustment times reach preset times, judging whether the phase relation between the reconstruction signal and the reference signal changes, if so, recording the values of the corresponding frequency control words when the phase relation changes for a plurality of times;
calculating the average value of the corresponding frequency control word when the phase relation changes for a plurality of times, and taking the average value as the value of the current frequency control word;
and finely adjusting the value of the frequency control word according to the phase relation between the reconstructed signal and the reference signal to ensure that the frequency of the frequency-divided reconstructed signal is equal to that of the reference signal, and enabling the all-digital phase-locked loop to enter a locking state.
5. The fast phase-locking method for the adpll according to any one of claims 1 to 4, wherein the predetermined number is 10.
6. An all-digital phase-locked loop phase-locked using the fast phase-locking method of claim 1, comprising:
a numerically controlled oscillator for outputting a reconstructed signal when a falling edge of the reference signal comes;
the frequency division module is used for carrying out frequency division on the reconstructed signal;
the frequency comparison module is used for comparing the frequency of the frequency-divided reconstructed signal with the frequency of the reference signal and outputting a corresponding level signal according to a comparison result;
the control module is used for roughly adjusting the value of the frequency control word according to the level signal and a preset rule so as to adjust the output frequency of the reconstructed signal; and when the coarse tuning frequency reaches a preset frequency, finely tuning the value of the frequency control word according to the phase relation between the reconstruction signal and the reference signal to enable the frequency of the frequency-divided reconstruction signal to be equal to the frequency of the reference signal, and enabling the all-digital phase-locked loop to enter a locked state.
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| CN110927560A (en) * | 2019-12-16 | 2020-03-27 | 无锡矽鹏半导体检测有限公司 | Integrated circuit testing method |
| CN111610433A (en) * | 2020-06-17 | 2020-09-01 | 江西联智集成电路有限公司 | Chip power-on and power-off reset test method and device |
| CN113242038A (en) * | 2021-06-02 | 2021-08-10 | 南方电网科学研究院有限责任公司 | Phase-locked loop, phase-locking method and phase-locking equipment |
| CN117169593B (en) * | 2023-11-02 | 2024-01-30 | 成都电科星拓科技有限公司 | Indirect measurement method, system, equipment and medium for step length of time-to-digital converter |
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