CN110927560A - Integrated circuit testing method - Google Patents
Integrated circuit testing method Download PDFInfo
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- CN110927560A CN110927560A CN201911294300.4A CN201911294300A CN110927560A CN 110927560 A CN110927560 A CN 110927560A CN 201911294300 A CN201911294300 A CN 201911294300A CN 110927560 A CN110927560 A CN 110927560A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention relates to the field of integrated circuit testing, and discloses an integrated circuit testing method, which comprises the steps of firstly determining the interval of signal source output signal values when the output pin of an integrated circuit has state jump, namely adjusting the signal value input into the integrated circuit by a large step pitch until the output pin of the integrated circuit has state jump, then retreating the output signal value of a signal source by two large step pitches, then adjusting the output signal value of the signal source by a small step pitch until the output pin of the integrated circuit has jump again, and at the moment, the output signal value of the signal source is the measurement result. The invention firstly determines the interval of the signal value output by the signal source when the output pin of the integrated circuit has state jump, and then adjusts the output signal of the signal source in small steps in the interval, thereby reducing the test time and improving the test efficiency while ensuring the test accuracy.
Description
Technical Field
The invention relates to the field of integrated circuit testing, in particular to an integrated circuit testing method.
Background
When the jump test is carried out on an integrated circuit, particularly an analog quantity chip, a continuously changing input value is firstly given to the chip, and then the corresponding input value when the output pin of the chip generates state jump is recorded, wherein the input value can be voltage and current.
In the existing test method, the input value is adjusted in a small step distance between the lower limit and the upper limit of the specification during the test, namely the input value is slightly changed from the lower limit of the specification each time until the output pin of the chip generates state jump or reaches the upper limit of the specification. However, in the actual test, the input value variation is small each time, the test efficiency is low, and if the variation of the input value is increased, the corresponding input value is inaccurate when the chip output pin has state jump, which affects the test accuracy.
Disclosure of Invention
In view of the shortcomings of the background art, the invention provides an integrated circuit testing method, and aims to improve the testing efficiency of the jump test of the integrated circuit under the condition of not influencing the measurement accuracy.
In order to solve the technical problems, the invention provides the following technical scheme: an integrated circuit testing method, comprising the steps of:
s1: an input pin of the integrated circuit is connected with a signal source, and a signal input to the integrated circuit by the signal source is adjustable;
s2: the testing is started, the output signal value of the signal source is adjusted to the measuring initial value, then the signal value output by the signal source is adjusted in a large step, whether the output pin of the integrated circuit generates state jump or not is observed, if the state jump occurs, the size of the signal value output by the current signal source is recorded and recorded as a first jump value, and then the step S3 is carried out;
s3: backing the signal value output by the signal source by two large steps from the first jump value, and recording as a second measurement starting value;
s4: and testing again, adjusting the output signal value of the signal source to a second measurement initial value, then adjusting the signal value output by the signal source in a small step, observing whether the output pin of the integrated circuit generates state jump, if so, recording the signal value output by the current signal source, and stopping testing.
The jump test has a measurement starting value and a measurement ending value, the signal output by the signal source is gradually adjusted from the measurement starting value to the measurement ending value, the measurement starting value is subtracted from the measurement ending value, then the result is divided by any integer from 15 to 20 to obtain a large step pitch, and the small step pitch is one tenth of the large step pitch.
Further, the signal source comprises a voltage source or a current source.
Furthermore, the amplitude, the frequency and the duty ratio of the output signal of the signal source are adjustable.
During testing, the interval of the signal value output by the signal source when the output pin of the integrated circuit has state jump is determined, namely the output signal of the signal source starts from the lower limit of the specification, then a large step is added every time, and if the state jump occurs, the signal value output by the current signal source is recorded and recorded as a first jump value. And backing the first jump value by two large steps to be a second test starting value of the signal source output signal, and then increasing one small step each time, wherein the output signal value of the signal source is the measurement result when the state jump occurs again.
Compared with the prior art, the invention has the beneficial effects that: the method comprises the steps of firstly determining the interval of the signal value output by a signal source when the output pin of the integrated circuit has state jump, then adjusting the output signal of the signal source at small step pitch in the interval until the output pin of the integrated circuit has state jump again, and further reducing the test time and improving the test efficiency while ensuring the test accuracy.
Drawings
The invention has the following drawings:
FIG. 1 is a schematic diagram of large step adjustment of a signal source according to the present invention;
fig. 2 is a schematic diagram of small step adjustment of a signal source according to the present invention.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
Example one
As shown in fig. 1-2, a method for testing an integrated circuit includes the steps of:
s1: the input pin of the integrated circuit is connected with a signal source, and the signal source is adjustable by using a signal input to the integrated circuit;
s2: the testing is started, the output signal value of the signal source is adjusted to the measuring initial value, then the signal value output by the signal source is adjusted in a large step, whether the output pin of the integrated circuit generates state jump or not is observed, if the state jump occurs, the size of the signal value output by the current signal source is recorded and recorded as a first jump value, and then the step S3 is carried out;
s3: backing the signal value output by the signal source by two large steps from the first jump value, and recording as a second measurement starting value;
s4: and testing again, adjusting the output signal value of the signal source to a second measurement initial value, then adjusting the signal value output by the signal source in a small step, observing whether the output pin of the integrated circuit generates state jump, if so, recording the signal value output by the current signal source, and stopping testing.
In this embodiment, the signal source outputs a voltage signal, the voltage amplitude is variable and adjustable, and a specific variation process is as shown in fig. 1, the voltage signal output by the signal source increases by one large step pitch each time, when the voltage signal increases to a, the output pin of the integrated circuit generates a state transition, at this time, the voltage signal is adjusted to a point B, that is, the voltage amplitude is retreated by two large steps, and then, the small step pitch adjustment is performed according to fig. 2. In fig. 2, the voltage signal is adjusted from B, one small step at a time, and if the voltage signal increases to C, a state transition occurs at the output pin of the integrated circuit, and the result is measured at C.
The voltage signal at the position A is backed by two large steps to the position B, so that the voltage signal is just in a critical state when the voltage signal is backed by one step.
Further, the small step is one tenth of the large step; the signal source can also be a current source, and the input pin of the integrated circuit can also input voltage or current signals with different frequencies and different duty ratios for testing, wherein the specific testing steps are as above.
Table 1 shows a conventional test method and a test data table of the present invention, in which the lower specification limit is a measurement start value and the upper specification limit is a measurement end value. As can be seen from table 1, when the measurement results are the same, the time used in the present invention is about one fourth of the time used in the existing test method, which reduces the test time and improves the test efficiency. The specific table is as follows:
TABLE 1
Example two
In this embodiment, the signal source is a voltage signal, the initial measurement value is 3.0V, the final measurement value is 5.0V, the initial measurement value is subtracted from the final measurement value, and the result is divided by twenty, so that the large step size is 0.1V, and the small step size is 0.01V. During the jump test, the voltage output by the signal source starts from 3.0V, 0.1V is increased every time, when the voltage output by the signal source is 4.0V, the state jump occurs on the output pin of the integrated circuit, the output voltage of the signal source is adjusted to 3.8V, and then 0.01V is increased every time until the state jump occurs on the output pin of the integrated circuit again. Compared with the method that the test is carried out by increasing 0.01V every time from 3.0V, the data interval of the signal source when the state jump occurs is determined in a large range, and then the specific voltage output value of the signal source when the state jump occurs is tested in a small range in the interval, so that the test time can be saved.
In light of the foregoing, it is to be understood that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (3)
1. An integrated circuit testing method, comprising: the method comprises the following steps:
s1: an input pin of the integrated circuit is connected with a signal source, and a signal input to the integrated circuit by the signal source is adjustable;
s2: when the test is started, adjusting the output signal value of the signal source to a measurement initial value, then adjusting the signal value output by the signal source in a large step, observing whether the output pin of the integrated circuit generates state jump or not, if the state jump occurs, recording the magnitude of the current signal value output by the signal source, recording the magnitude as a first jump value, and then entering the step S3;
s3: backing the signal value output by the signal source by two large steps from the first jump value, and recording as a second measurement starting value;
s4: testing again, adjusting the output signal value of the signal source to a second measurement initial value, then adjusting the signal value output by the signal source in small steps, observing whether the output pin of the integrated circuit generates state jump, if so, recording the magnitude of the current signal value output by the signal source, and stopping testing;
the large step in steps S2 and S3 is obtained by subtracting the measurement start value from the measurement end value of the signal source output signal and dividing by any integer from 15 to 20, and the small step in step S4 is one tenth of the large step.
2. The integrated circuit testing method of claim 1, wherein: the signal source comprises a voltage source or a current source.
3. The integrated circuit testing method of claim 1, wherein: the amplitude, the frequency and the duty ratio of the output signal of the signal source are adjustable.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113727104A (en) * | 2020-05-22 | 2021-11-30 | 北京小米移动软件有限公司 | Encoding method and apparatus, decoding method and apparatus, and storage medium |
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