JP3083033B2 - measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a measuring apparatus for measuring a waveform signal from an object to be measured, and in particular, to automatically calibrate deterioration of frequency characteristics caused by input capacitance mainly including stray capacitance such as wiring. The present invention relates to a measuring device having a function of performing

[0002]

2. Description of the Related Art Conventionally, when measuring an object to be measured (hereinafter abbreviated as DUT) using an oscilloscope, a probe is connected to
The frequency characteristics of the probe have been calibrated by connecting it to a UT, causing the probe to capture a square wave signal, and adjusting a trimmer capacitor provided on the probe. Here, it is necessary to calibrate the frequency characteristics of the signal line for measuring the DUT. Calibration of the frequency characteristics of the pins is performed by manually adjusting the trimmer capacitor of the measuring device. However,
Calibrating the frequency characteristics manually requires a lot of time and effort, and there is a problem that accurate measurement cannot be performed due to individual differences. The device that solves this problem is disclosed in
No. 069 and Japanese Utility Model Laid-Open No. 2-67283. However, in these devices, although the capacitance is changed by one variable capacitance diode, the capacitance of the variable capacitance diode changes due to the change in the voltage of the signal output from the DUT during measurement, and the frequency characteristics are poor. There was a problem that it would be.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to realize a measuring apparatus which has good frequency characteristics during measurement and performs automatic calibration.

[0004]

According to the present invention, there is provided a measuring apparatus for measuring a waveform signal from an object to be measured, a signal generating means for generating a waveform signal, and a signal path for inputting a signal from the object to be measured. A first variable capacitance diode provided between the ground potential point and a signal path for inputting a signal from the object to be measured and a second variable capacitance diode provided between the ground potential point; Waveform signals from the signal generation means are sent at different timings through the signal path.
And the first difference is determined by the amplitude difference between the measured waveforms.
A variable capacitance diode and the second variable capacitance diode;
And a reverse bias means for changing a reverse bias voltage applied to the input signal, and inputting a waveform signal from an object to be measured into a signal path during measurement.

[0005]

[0006]

According to the present invention, during calibration, the waveform from the signal generating means is measured via the signal path by the reverse bias means, and the first and second variable capacitance diodes are reverse biased based on the measurement result. Give voltage. The capacitances of the first and second variable capacitance diodes are changed by a change in a voltage value provided by the reverse bias means. The reverse bias means changes the reverse bias voltage applied to the first and second variable capacitance diodes based on the difference between the amplitudes of the waveforms measured at different timings.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a configuration diagram showing one embodiment of the present invention. In the figure,
Reference numeral 1 denotes an object to be measured (hereinafter abbreviated as DUT). 2 is a waveform generator for generating a waveform, R1 is a first resistor, and D1 is provided at one end.
A waveform signal from the UT 1 or the waveform generator 2 is input. When measuring the DUT1, the switch SW
Is open. When the frequency characteristic is calibrated, the DUT 1 is disconnected, the switch SW is connected, and the waveform generator 2 is connected to the resistor R1. C1 is a capacitor connected in parallel with the resistor R1.

D1 is a first variable capacitance diode, the cathode of which is connected to the ground potential via a capacitor C2;
The anode is connected to the other end of the resistor R1. And
The capacitor C2 allows the AC component of the current generated between the cathode and the ground potential point to flow to the ground potential point. D2 is a second variable capacitance diode whose anode is a capacitor C3.
And the cathode is connected to the other end of the resistor R1. The capacitor C3 allows the AC component of the current generated between the anode and the ground potential point to flow to the ground potential point. R2 is a second resistor having one end connected to the other end of the resistor R1 and the other end connected to a ground potential point. An amplifier 3 has one end connected to the resistor R1 and amplifies the waveform from the resistor R1.

Reference numeral 4 denotes a waveform measuring unit which is connected to the other end of the amplifier 3 and measures a waveform via the resistor R1 and the amplifier 3.
Reference numeral 5 denotes a CPU which is an arithmetic means, and obtains a reverse bias value to be applied to the variable capacitance diodes D1 and D2 optimal for compensating frequency characteristics based on a measurement result by the waveform measurement unit 4. 6
Denotes a memory serving as a storage unit, which stores a reverse bias value obtained by the CPU 5. Reference numeral 7 denotes a voltage supply unit that applies a positive voltage to the cathode of the variable capacitance diode D1 and a negative voltage to the anode of the variable capacitance diode D2 based on the reverse bias value obtained by the CPU 5.

In the voltage supply section 7, reference numeral 71 denotes a D / A conversion section, which converts the reverse bias value obtained by the CPU 5 into a voltage. Here, it is assumed that the D / A converter 71 can output 0 to 5V. Reference numeral 72 denotes an operational amplifier that performs addition by using the voltage from the D / A converter 71 and an offset voltage (here, 10 V), and applies a negative voltage to the anode of the variable capacitance diode D2. 73 is an inverting amplifier, and an operational amplifier 7
2 is inverted to apply a positive voltage to the cathode of the variable capacitance diode D1. Here, the reverse bias means includes the waveform measurement unit 4, the CPU 5, and the voltage supply unit 7.

For example, in an apparatus for measuring a driver of a liquid crystal display, a switch SW, resistors R1, R
2, a capacitor C1, C2, C3, a variable capacitance diode D1, D2, an amplifier 3, and a voltage supply unit 7 as one pin electronics card. A pin electronics card is provided for each driver pin of the liquid crystal display.

The operation of automatic calibration of the frequency characteristics of such an apparatus will be described below. The switch SW is connected with the DUT 1 removed. The waveform generator 2 outputs a square wave signal. Then, the waveform measuring unit 4 measures the square wave signal passing through the resistor R1 and the amplifier 3. Variable capacitance diode D for which CPU 5 can obtain a desired frequency characteristic based on the measurement result.
The reverse bias values of D1 and D2 are obtained, and a digital value based on the reverse bias value is sent to the D / A converter 71. Further, the reverse bias value is stored in the memory 6. The D / A conversion unit 71
Convert digital value to voltage value. And the operational amplifier 72
Performs addition of the voltage from the D / A converter 71 and the offset voltage. Here, an output voltage of -10 to -15 V is obtained. This voltage is applied to the anode of the variable capacitance diode D2. The output voltage of the operational amplifier 72 is inverted by the inverting amplifier 73, and a voltage of +10 to +15 V is applied to the cathode of the variable capacitance diode D1. The variable capacitance diodes D1 and D2 each receive a reverse bias voltage and change the capacitance. The above operation is repeated to obtain a desired frequency characteristic. Then, when the frequency characteristic is calibrated next time, the calibration is performed with a bias value that can obtain a desired frequency characteristic from the memory 6. When the calibration is completed, the switch SW is opened, the DUT 1 is connected, and the waveform output from the DUT 1 is measured.

Next, the variable capacitance diode D at the time of measurement
1 and D2 will be described. FIG. 2 is a diagram illustrating the operation of the variable capacitance diodes D1 and D2 during measurement.
For example, +10 V is applied to the cathode of the variable capacitance diode D1.
And -10 V is applied to the variable capacitance diode D2, and the frequency characteristic is calibrated. The attenuated waveform before the DC superimposed waveform is input to the resistor R1 and input to the amplifier for amplifying the waveform is referred to as waveforms A and B. Here, FIG. 3 shows the reverse bias voltage-capacitance characteristics of the variable capacitance diodes D1 and D2.

When no waveform is input, the capacitance is 17 pF as shown in FIG. 3 because a reverse bias voltage of 10 V is applied to both of the variable capacitance diodes D1 and D2. In total, the capacitance is 34 pF. When the waveform is input and becomes the waveform A, the capacitance of the variable capacitance diode D1 when the waveform A is 2 V is 20 pF from FIG. 3 because the reverse bias voltage is 8 V. Since the reverse bias voltage is 12 V, the capacitance of the variable capacitance diode D2 is 15 pF from FIG. Variable capacitance diode D
Since the sum of the capacitances of 1 and D2 is 35 pF, the capacitance hardly changes as a sum. Therefore, even if a DC superimposed waveform is input, the frequency characteristics do not deteriorate, and the waveforms A and B
As shown by the solid line, a waveform having good frequency characteristics can be obtained.

However, when the frequency characteristics are adjusted only by the variable capacitance diode D2, the waveforms A and B are as shown by broken lines. In other words, the voltage change of the input waveform
In the case of the waveform A, the capacitance is smaller than when the capacitance of the variable capacitance diode D2 adjusts the frequency characteristics, and the compensation becomes excessive. In the case of the waveform B, the capacitance of the variable capacitance diode D1 becomes large, and the compensation becomes too small.

As described above, the variable capacitance diodes D1, D
In step 2, the CPU 5 obtains a reverse bias value based on the result measured by the waveform measuring section 4. Then, the current supply unit 7 sets the variable capacitance diode D
1 and D2, the frequency characteristics can be automatically calibrated. In addition, since a positive voltage is applied to the cathode of the variable capacitance diode D1 and a negative voltage is applied to the anode of the variable capacitance diode D2, even when a DC superimposed waveform is input at the time of measurement, the waveform is maintained without deteriorating the frequency characteristics. Can be measured. Then, even when an overcurrent is input, the overcurrent flows through the variable capacitance diode D1 or the variable capacitance diode D2, so that there is no need to provide a protection circuit for the amplifier 3 against the overcurrent. Furthermore, since the variable capacitance diode D1 protects the amplifier 3 from a positive overvoltage and the variable capacitance diode D2 protects the amplifier 3 from a negative overvoltage, there is no need to provide a protection circuit for the amplifier 3 against overvoltage.

FIG. 4 is a block diagram showing a part of another embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, D3 is a first variable capacitance diode, whose anode is connected to the ground potential point, and whose cathode is connected to the other end of the resistor R1 via a capacitor C4. D4 is a second variable capacitance diode whose cathode is connected to the ground potential point and whose anode is connected to the other end of the resistor R1 via a capacitor C5. Here, the capacitors C4 and C5 cut DC components. Then, a positive voltage is applied from the voltage supply unit to the cathode of the variable capacitance diode D3 via the coil L1, and a negative voltage is applied to the anode of the variable capacitance diode D4 via the coil L2. Here, coil L
1, L2 cuts the AC component.

The same effect can be obtained by making the input portion of the waveform such a configuration. The combination of the variable capacitance diode of the device of FIG. 1 and the variable capacitance diode of the device of FIG. 4 is also included in the present invention. For example, the variable capacitance diode D1 and the variable capacitance diode D4 are used. The present invention also includes a configuration in which the CPU includes a signal generation unit and a reverse bias unit.

Hereinafter, actual variable capacitance diodes D1, D
The relationship between the total input capacitance of No. 2 and the input voltage will be described. FIG. 5 is a diagram showing the relationship between the total input capacitance of the variable capacitance diodes D1 and D2 and the input voltage. In FIG, Vin is an input voltage input to the resistor R1, V _B is the reverse bias voltage applied to the variable capacitance diode, Ca is the input voltage Vin is an input capacitance of the variable capacitance diodes D1, D2 when the 0. Cb is the input capacitance of the variable capacitance diode D1 when the input voltage Vin is V, or the input voltage Vin.
Is the input capacitance of the variable capacitance diode D2 when −V is −V. Cc is the input capacitance of the variable capacitance diode D2 when the input voltage Vin is V, or the input capacitance of the variable capacitance diode D1 when the input voltage Vin is -V.

When the input voltage Vin is 0, the total capacitance of the variable capacitance diodes D1 and D2 is 2Ca. And
Variable capacitance diode D1, when input voltage Vin is ± V
The total input capacitance of D2 is Cb + Cc. Here, FIG.
As is clear from FIG. 5, when the input voltage Vin changes, the total capacitance slightly differs but becomes substantially the same. In addition, if the range in which the input voltage Vin changes is reduced, the total amount of change in capacitance is reduced, and measurement with better frequency characteristics can be performed.

FIG. 6 shows the relationship between the input capacitance and the input voltage when the reverse bias voltage is different. The same components as those in FIG. 5 are denoted by the same reference numerals. Here, V ₁ <V ₂ <V ₃ (V ₁ , V
₂ , V ₃ : constant). As is apparent from the figure, if the reverse bias voltage increases, the total input capacitance of the variable capacitance diodes D1 and D2 hardly changes even if the input voltage Vin changes. Therefore, if the reverse bias voltage is set to a large value, measurement with better frequency characteristics can be performed even if the input voltage changes.

As another embodiment, an example in which the present invention is applied to an IC tester will be described below. FIG. 7 is a configuration diagram showing a first embodiment of an IC tester to which the present invention is applied. Hereinafter, the same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 10
Is a digital function module (hereinafter abbreviated as DFC), which is composed of a timing generator, a pattern generator, a pattern memory, and a fail memory, and outputs various digital signals. Reference numeral 20 denotes a performance board attached at the time of calibration, which is electrically connected to the DFC 10. At the time of measurement, the performance board 20 is removed and replaced with a performance board to which an IC to be measured (hereinafter abbreviated as DUT) is connected. Reference numeral 30 denotes a pin electronics section, which is electrically connected to the performance board 20. Then, when measuring the DUT, signals are exchanged with the DUT. A multiplexer 40 selects a signal from the pin electronics unit 30. A waveform digitizer (hereinafter abbreviated as WFD) 50 measures the waveform of a signal selected by the multiplexer 40. 60 is a digital signal processor (hereinafter D)
SP), the signal measured by the WFD 50 is analyzed. Reference numeral 70 denotes a test system controller (hereinafter abbreviated as TSC), which controls the entire IC tester. Reference numeral 80 denotes a memory for storing a calibration value finally given to the D / A converter 33 by the TSC 70.

In the performance board 20, 21
Is a signal conversion unit which converts the digital signal from the DFC 10 into a signal having a large amplitude with good rising characteristics and gives the signal to each pin electronics unit 30. Pin Electronics Department 3
At 0, reference numeral 31 denotes a variable capacitor, which is composed of variable capacitance diodes D1 and D2 and capacitors C2 and C3 as in FIG. A driver 32 corresponds to the amplifier 3. A D / A converter 33 receives a signal from the TSC 70 and applies a positive or negative reverse bias voltage to the variable capacitor 31. Here, the signal generation means is composed of the DFC 10 and the signal conversion unit 21, and the reverse bias means is composed of the WFD 50, the DSP 60, the TSC 70, and the D / A conversion unit 33.

The operation of such a device is described below.
FIG. 8 is a flowchart showing the operation of the apparatus shown in FIG. FIG. 9 is a diagram illustrating the calibration operation. In FIG. 9, (a) shows a case where the compensation of the variable capacitor 31 is too small.
(B) is a case where the compensation of the variable capacitor 31 is excessive.

The TSC 70 supplies CH1 to the multiplexer 40.
Is selected. And
D / A conversion section 3 of pin electronics section 30 of CH1
3 outputs the minimum positive and negative reverse bias voltages. Further, the digital signal is output from the DFC 10 and the signal is supplied from the signal conversion unit 21 to the pin electronics unit 30. And WFD50 is the pin electronics section 3
0, Measure the signal through the multiplexer 40. DS
P60 represents the amplitudes EA and B at the time A as shown in FIG.
Δ (= EA−EB) is calculated from the amplitude EB at the time point.

When EA> EB, that is,
In the case of (b), since the compensation is excessive, the capacity of the variable capacitor 31 must be increased. To this end, the capacitance can be increased by reducing the reverse bias voltage applied to the variable capacitance diode. However, the D / A converter 33
Since the minimum voltage value is given to the variable capacitor 31, the capacitance cannot be further increased. Therefore, the operator is notified that the calibration has failed. When EA <EB, maximum positive and negative reverse bias voltages are output to the variable capacitor 31 to the D / A converter 33. Then, when EA <EB, that is, when (a), the compensation is too small, so the capacitance of the variable capacitor 31 must be reduced. To achieve this, the capacity is reduced by increasing the reverse bias voltage applied to the variable capacitance diode, which is the opposite of the above. However, the D / A converter 33
Since the maximum voltage value is given to the variable capacitor 31, the capacitance cannot be further reduced. Therefore, the operator is notified that the calibration has failed. When EA> EB, the following operation is performed.

The TSC 70 outputs an intermediate voltage between the reverse bias voltages that the D / A converter 33 can output. And
The signal output from the pin electronics unit 30 is measured by the WFD 50 via the multiplexer 40,
Δ is obtained from 0, and it is confirmed whether δ ≦ ± 1 (a binary value of a computer). When δ ≦ ± 1, the TSC 70 stores an intermediate voltage value as a calibration value. And δ ≦ ± 1
In other cases, the TSC 70 determines whether the amplitude at the time A and the time B is (a) or (b) in FIG.

When EA> EB, that is, when (b), the compensation is excessive, and the capacitance of the capacitor 31 must be increased. Therefore, the D / A converter 3
3 may be reduced. When EA <EB, that is, when (a), the compensation is too small, so the capacitance of the capacitor 31 must be reduced. Therefore, the voltage value of the D / A converter 33 may be increased.

From the above, TSC1 is determined as follows: EA> EB
In the case of, a voltage value intermediate between the intermediate value of the voltage that can be output by the D / A converter 33 and the minimum voltage value is output. EA <EB
In the case of, a voltage value intermediate between the intermediate value of the voltage that can be output by the D / A converter 33 and the maximum voltage value is output. Then, a signal output from the pin electronics unit 30 is measured by the WFD 50 via the multiplexer 40, and
The DSP 60 calculates δ and confirms whether δ ≦ ± 1. When δ ≦ ± 1, the TSC 70 stores the voltage value as a calibration value. When δ ≦ ± 1, TSC 70 is A
Whether the amplitude between the time point and the time point B is (a) or (b) in FIG. 9 is determined again. Then, a binary search is performed in the same manner as described above.

The above binary search is performed until δ ≦ ± 1. The TSC 70 stores a reverse bias voltage value applied to the variable capacitor 31. Then, the TSC 70 selects the pin electronics section 30 of CH2 by the multiplexer 40, applies the minimum voltage and the maximum voltage to the variable capacitor 31, and checks whether or not a calibration failure occurs. Then, a reverse bias voltage value applied to the variable capacitor 31 is obtained by a binary search and stored. Such an operation is repeated up to the pin electronics section 30 of 256CH. When the calibration for all the pin electronics sections 30 is completed, the calibration values for all the pin electronics sections 30, that is, the reverse bias voltage values are stored in the memory 80.

The following configuration is also conceivable. FIG.
0 is a configuration diagram showing a second embodiment of the IC tester to which the present invention is applied. Hereinafter, the same components as those in FIG. 7 are denoted by the same reference numerals. In the figure, reference numeral 51 denotes a D / A converter, which outputs two kinds of desired voltages. A comparator 52 compares a signal output from the pin electronics unit 30 selected by the multiplexer 40 with a voltage output from the D / A conversion unit 51,
Output the comparison result. Reference numeral 61 denotes a DFC that stores the comparison result of the comparator 52 at a desired timing. here,
The reverse bias means includes D / A converters 33 and 51, a comparator 52, a DFC 61, and a TSC 70.

The operation of such a device selects the pin electronics section 30 to be calibrated by the multiplexer 40. Then, the digital signal is input from the DFC 10 to the pin electronics unit 30 via the signal conversion unit 21. The comparator 52 is connected to the pin electronics unit 30.
Are compared with the voltage output by the D / A converter 51. The DFC 61 stores the comparison result of the comparator 52. The TSC 70 determines whether to increase or decrease the voltage output by the D / A converter 33 based on the comparison result stored in the DFC 61. That is, if it is determined from the comparison result that it is the case of FIG. 9A, the TSC 70 increases the voltage of the D / A converter 33. Then, if it is determined that the case of FIG. 9B is used, the TSC 70 reduces the voltage of the D / A converter 33. The above operation is repeated until the signal output by the pin electronics unit 30 is input between the two types of voltages output by the D / A conversion unit 51. Then, another pin electronics section 30 is selected again by the multiplexer 40, and the above operation is performed. Thus, the frequency characteristics of the pin electronics unit 30 are calibrated.

Further, the embodiment in which the present invention is applied to an IC tester is not limited to the above-mentioned one. In the apparatus shown in FIG. 10, a D / A converter 51 and a comparator 52 are not used. May be provided for each pin electronics unit 30, and the outputs from all the comparators 52 may be received by the DFC 61. Although an example in which the present invention is applied to an IC tester is shown, the present invention may be applied to an oscilloscope.

[0034]

According to the present invention, since the reverse bias value obtained by the measuring and calculating means is given to the variable capacitance diode by the voltage supply means, the frequency characteristics can be automatically calibrated. Further, since the first variable capacitance diode and the second variable capacitance diode whose capacitance is changed by a voltage are provided, even when a DC superimposed waveform is input during measurement, waveform measurement can be performed without deteriorating frequency characteristics. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 shows variable capacitance diodes D1 and D2 during measurement.
It is a figure explaining operation of.

FIG. 3 is a diagram showing reverse bias voltage-capacitance characteristics of variable capacitance diodes D1 and D2.

FIG. 4 is a configuration diagram showing a part of another embodiment of the present invention.

FIG. 5 is a diagram showing the relationship between the total input capacitance of the variable capacitance diodes D1 and D2 and the input voltage.

FIG. 6 is a diagram showing the relationship between input capacitance and input voltage when the reverse bias voltage is different.

FIG. 7 is a configuration diagram showing a first embodiment of an IC tester to which the present invention is applied.

FIG. 8 is a flowchart showing the operation of the apparatus of FIG.

FIG. 9 is a diagram illustrating a calibration operation.

FIG. 10 is a configuration diagram showing a second embodiment of the IC tester to which the present invention is applied.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 measurement target 4 waveform measurement unit 5 CPU 7 voltage supply unit R1, R2 resistor C1 capacitor D1, D2 variable capacitance diode 10, 61 DFC 21 signal conversion unit 31 variable capacitor 32 driver 33, 51 D / A conversion unit 50 WFD 52 Comparator 60 DSP 70 TSC

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideo Doi 2-9-132 Nakamachi, Musashino City, Tokyo Yokogawa Electric Corporation (72) Inventor Kenji Uda 2-9-132 Nakamachi, Musashino City, Tokyo Inside Kawa Electric Co., Ltd. (72) Inventor Muneo Ishibachi 2-9-132 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Co., Ltd. Examiner Tadashi Shinozaki (56) References JP 5-218902 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 35/00 G01R 13/00-13/42

Claims (1)

(57) [Claims] 1. A measuring apparatus for measuring a waveform signal from an object to be measured, comprising: a signal generating means for generating a waveform signal; and a signal path for inputting a signal from the object to be measured and a ground potential point. A first variable capacitance diode provided; a second variable capacitance diode provided between a signal path for inputting a signal from the object to be measured and a ground potential point; and a waveform signal from a signal generating means during calibration. Via the signal path
Measurement at different timings, and
The first variable capacitance diode and the second
The reverse bias voltage applied to the variable capacitance diode
And a reverse bias means for converting the waveform signal from the object to be measured into a signal path at the time of measurement.