JP3198493B2 - IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an IC under test, for example,
The present invention relates to an IC tester for testing a driver of a liquid crystal display and the like, and more particularly to an IC tester having a function of automatically calibrating a deterioration of a rising characteristic of an input signal caused by an input capacitance mainly including a stray capacitance such as a wiring. is there.

[0002]

2. Description of the Related Art When testing an IC under test (hereinafter abbreviated as DUT) such as a driver of an STN type liquid crystal display having a high voltage, a high speed, and a high output impedance, an IC receiving an output from a pin of one DUT. In order to obtain DC accuracy, a high-resistance voltage-dividing resistor is placed at the input stage of the tester.
After voltage division, via buffer amplifier or comparator,
Input to the digital function module or waveform digitizer. Since the stray capacitance of the wiring connected to each pin of the DUT deteriorates the rising characteristics of the input signal, a capacitor is arranged to correct the rise and cancel the influence of the stray capacitance.

[0003]

In the device having such a configuration, the variation in the stray capacitance causes the variation between the pins of the IC tester, thereby deteriorating the accuracy. However, the test time is long until settling occurs. Become. Also, even if the capacitor is composed of a trimmer capacitor and the trimmer capacitor is manually adjusted, the number of pins is large, so manually adjusting the trimmer capacitor takes time and the required accuracy is not sufficient. there were.

An object of the present invention is to realize an IC tester capable of performing a high-speed and high-accuracy test by automatically calibrating an input capacitance.

[0005]

According to the present invention, there is provided an IC tester for testing an IC under test, comprising: a waveform signal generating means for generating a square wave; and an anode in a signal path for inputting a signal from the IC under test. a first variable capacitance diode for connecting said signal path for inputting a signal from the IC
A second variable capacitance diode connecting the cathode, and a capacitance adjusting means for applying a positive voltage to the cathode of the first variable capacitance diode and applying a negative voltage to the anode of the second variable capacitance diode to adjust the capacitance And inputting the square wave from the waveform signal generating means to the signal path in place of the signal from the IC under test, measuring two different points of the square wave, and minimizing the difference between the two points. The first and second variable capacitance diodes are adjusted by capacitance adjusting means.

[0006]

According to the present invention, during calibration, the square wave from the waveform signal generating means is measured by the capacity adjusting means, and the capacitances of the first and second variable capacitance diodes are adjusted based on the measurement result.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a configuration diagram showing a first embodiment of the present invention. In the figure, 10 is a digital function module (hereinafter D)
FC), which comprises a timing generator, a pattern generator, a pattern memory, and a fail memory, and outputs various digital signals. Reference numeral 20 denotes a performance board attached at the time of calibration, which is electrically connected to the DFC 10. At the time of testing, the performance board 20 is removed and replaced with a performance board to which a DUT is connected. Reference numeral 30 denotes a pin electronics section, which is electrically connected to the performance board 20. And
When testing the DUT, signals are exchanged with the DUT. A multiplexer 40 selects a signal from the pin electronics unit 30. Reference numeral 50 denotes a waveform digitizer (hereinafter abbreviated as WFD), and a multiplexer 40.
Measures the waveform of the selected signal. Reference numeral 60 denotes a digital signal processor (hereinafter abbreviated as DSP), which analyzes a signal measured by the WFD 50. Reference numeral 70 denotes a test system controller (hereinafter abbreviated as TSC), which controls the entire IC tester. Reference numeral 80 denotes a memory for storing a calibration value finally adjusted by the TSC 70.

In the performance board 20, 21
Is a signal conversion unit which converts the digital signal from the DFC 10 into a signal having a large amplitude with good rising characteristics and gives the signal to each pin electronics unit 30. Pin Electronics Department 3
At 0, R1 is a first resistor, to one end of which a waveform signal from the DUT or the signal converter 21 is input. C1 is a capacitor connected in parallel with the resistor R1. A variable capacitance diode 31 is provided between the other end of the resistor R1 and the ground potential point. A driver 32 has one end connected to the resistor R1 and amplifies the waveform from the resistor R1. A D / A converter 33 outputs a reverse bias voltage applied to the variable capacitance diode 31 by the TSC 70. Here, the waveform signal generation means is composed of the DFC 10 and the signal conversion unit 21, and the capacity adjustment means is the WFD 50 and the DS converter 10.
P60, TSC 70 and D / A converter 33.

The operation of such a device is described below.
FIG. 2 is a flowchart showing the operation of the apparatus shown in FIG. FIG. 3 is a diagram illustrating the calibration operation. 3A shows a case where the compensation of the variable capacitance diode 31 is too small, and FIG. 3B shows a case where the compensation of the variable capacitance diode 31 is too large.

The TSC 70 supplies CH1 to the multiplexer 40.
Is selected. And
D / A conversion section 3 of pin electronics section 30 of CH1
3 outputs the minimum reverse bias voltage. Also, DFC
The digital signal is output from the signal conversion unit 21 to the pin electronics unit 30. And
The WFD 50 measures a signal via the pin electronics unit 30 and the multiplexer 40. The DSP 60 calculates δ (= EA−EB) from the amplitude EA at the point A and the amplitude EB at the point B as shown in FIG.

Then, when EA> EB, that is,
In the case of (b), since the compensation is excessive, the capacitance of the variable capacitance diode 31 must be increased. To this end, the capacitance can be increased by reducing the reverse bias voltage applied to the variable capacitance diode 31. However, since the D / A converter 33 gives the minimum voltage value to the variable capacitance diode 31, the capacitance cannot be further increased. Therefore, the operator is notified that the calibration has failed. When EA <EB, the D / A converter 33
And outputs the maximum reverse bias voltage to the variable capacitance diode 31. When EA <EB, that is, when (a), the compensation is too small.
Must be reduced in capacity. In order to achieve this, the capacitance is reduced by increasing the reverse bias voltage applied to the variable capacitance diode 31, which is opposite to the above. However, D / A
Since the converter 33 gives the maximum voltage value to the variable capacitance diode 31, the capacitance cannot be further reduced. Therefore, the operator is notified that the calibration has failed. When EA> EB, the following operation is performed.

The TSC 70 outputs an intermediate voltage between the reverse bias voltages that the D / A converter 33 can output. And
The signal output from the pin electronics unit 30 is measured by the WFD 50 via the multiplexer 40,
Δ is obtained from 0, and it is confirmed whether δ ≦ ± 1 (a binary value of a computer). When δ ≦ ± 1, the TSC 70 stores an intermediate voltage value as a calibration value. And δ ≦ ± 1
In other cases, the TSC 70 determines whether the amplitude at the time A and the time B is (a) or (b) in FIG.

When EA> EB, that is, when (b), the compensation is excessive, so that the capacitance of the variable capacitance diode 31 must be increased. Therefore, D / A
What is necessary is just to make the voltage value of the conversion part 33 small. When EA <EB, that is, when (a), the compensation is too small.
The capacitance of the variable capacitance diode 31 must be reduced. Therefore, the voltage value of the D / A converter 33 may be increased.

From the above, TSC1 is determined as follows: EA> EB
In the case of, a voltage value intermediate between the intermediate value of the voltage that can be output by the D / A converter 33 and the minimum voltage value is output. EA <EB
In the case of, a voltage value intermediate between the intermediate value of the voltage that can be output by the D / A converter 33 and the maximum voltage value is output. Then, a signal output from the pin electronics unit 30 is measured by the WFD 50 via the multiplexer 40, and
The DSP 60 calculates δ and confirms whether δ ≦ ± 1. When δ ≦ ± 1, the TSC 70 stores the voltage value as a calibration value. When δ ≦ ± 1, TSC 70 is A
Whether the amplitude between the time point and the time point B is (a) or (b) in FIG. 9 is determined again. Then, a binary search is performed in the same manner as described above.

The above binary search is performed until δ ≦ ± 1. The TSC 70 stores a reverse bias voltage value applied to the variable capacitance diode 31. And TSC70 is CH2
The pin electronics section 30 is selected by the multiplexer 40, and the minimum voltage and the maximum voltage are applied to the variable capacitance diode 31 to check whether or not a calibration failure occurs. Then, a reverse bias voltage value applied to the variable capacitance diode 31 is obtained by a binary search and stored. Such an operation is performed by the pin electronics section 3 of 256CH.
When the calibration is repeated for all the pin electronics units 30, the calibration values for all the pin electronics units 30, that is, the reverse bias voltage values are stored in the memory 80.

As described above, by adjusting the capacitance of the variable capacitance diode 31, there is no variation between pins.
Since the input capacitance can be automatically calibrated, high-speed and high-accuracy testing can be performed.

Another embodiment will be described below. FIG. 4 is a configuration diagram showing a second embodiment of the present invention. Hereinafter, the same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 51 is D / A
The converter outputs two desired voltages. A comparator 52 compares a signal output from the pin electronics unit 30 selected by the multiplexer 40 with a voltage output from the D / A conversion unit 51, and outputs a comparison result. 61 is D
The FC stores the comparison result of the comparator 52 at a desired timing. Here, the capacity adjusting means includes the D / A converters 33 and 51, the comparator 52, the DFC 61 and the TSC7.
0.

The operation of such a device selects the pin electronics section 30 to be calibrated by the multiplexer 40. Then, the digital signal is input from the DFC 10 to the pin electronics unit 30 via the signal conversion unit 21. The comparator 52 is connected to the pin electronics unit 30.
Are compared with the voltage output by the D / A converter 51. The DFC 61 stores the comparison result of the comparator 52. The TSC 70 determines whether to increase or decrease the voltage output by the D / A converter 33 based on the comparison result stored in the DFC 61. That is, if it is determined from the comparison result that the case shown in FIG. 3A is satisfied, the TSC 70 increases the voltage of the D / A converter 33. Then, if it is determined that the case of FIG. 3B is used, the TSC 70 reduces the voltage of the D / A converter 33. The above operation is repeated until the signal output by the pin electronics unit 30 is input between the two types of voltages output by the D / A conversion unit 51. Then, another pin electronics section 30 is selected again by the multiplexer 40, and the above operation is performed. Thus, the input capacitance of the pin electronics unit 30 is calibrated.

FIG. 5 is a block diagram showing a third embodiment of the present invention. In the figure, reference numeral 1 denotes a DUT, and 2 denotes a waveform generator which is a waveform signal generator, which generates a waveform signal. R1
Is a first resistor, one end of which is a DUT 1 or a waveform generator 2
Is input. When the test of the DUT 1 is performed, the switch SW is open. When calibrating the input capacitance, DUT1 is removed and
The switch SW is connected and the waveform generator 2 is connected to the resistor R1. C1 is a capacitor connected in parallel with the resistor R1.

D1 is a first variable capacitance diode, the cathode of which is connected to the ground potential via a capacitor C2;
The anode is connected to the other end of the resistor R1. And
The capacitor C2 allows the AC component of the current generated between the cathode and the ground potential point to flow to the ground potential point. D2 is a second variable capacitance diode whose anode is a capacitor C3.
And the cathode is connected to the other end of the resistor R1. The capacitor C3 allows the AC component of the current generated between the anode and the ground potential point to flow to the ground potential point. R2 is a second resistor having one end connected to the other end of the resistor R1 and the other end connected to a ground potential point. An amplifier 3 has one end connected to the resistor R1 and amplifies the waveform from the resistor R1.

Reference numeral 4 denotes a waveform measuring unit which is connected to the other end of the amplifier 3 and measures a waveform via the resistor R1 and the amplifier 3.
Reference numeral 5 denotes a CPU serving as an arithmetic unit, which determines an optimal reverse bias value to be applied to the variable capacitance diodes D1 and D2 based on the measurement result by the waveform measurement unit 4. Reference numeral 6 denotes a memory serving as a storage unit.
The reverse bias value obtained by the CPU 5 is stored. Reference numeral 7 denotes a voltage supply unit that applies a positive voltage to the cathode of the variable capacitance diode D1 and a negative voltage to the anode of the variable capacitance diode D2 based on the reverse bias value obtained by the CPU 5.

In the voltage supply section 7, reference numeral 71 denotes a D / A conversion section, which converts the reverse bias value obtained by the CPU 5 into a voltage. Here, it is assumed that the D / A converter 71 can output 0 to 5V. Reference numeral 72 denotes an operational amplifier that performs addition by using the voltage from the D / A converter 71 and an offset voltage (here, 10 V), and applies a negative voltage to the anode of the variable capacitance diode D2. 73 is an inverting amplifier, and an operational amplifier 7
2 is inverted to apply a positive voltage to the cathode of the variable capacitance diode D1.

Here, the variable capacitance section is the variable capacitance diodes D1 and D2, and the capacitance adjusting means is the waveform measuring section 4, the CPU 5, and the voltage supply section 7.

An actual IC tester has a switch SW, resistors R1, R2, capacitors C1, C2, C3, variable capacitance diodes D1, D2, an amplifier 3, and a voltage supply unit 7 as one pin electronics card. A pin electronics card is provided for each output pin of the driver of the liquid crystal display.

The operation of automatic calibration of the input capacity of such a device will be described below. The switch SW is connected with the DUT 1 removed. The waveform generator 2 outputs a square wave signal. Then, the waveform measuring unit 4 measures the square wave signal passing through the resistor R1 and the amplifier 3. Variable capacitance diodes D1 and C5 in which CPU 5 obtains a desired input capacitance based on the measurement result.
The reverse bias value of D2 is obtained, and a digital value based on the reverse bias value is sent to the D / A converter 71. Further, the reverse bias value is stored in the memory 6. The D / A converter 71 converts the digital value to a voltage value. Then, the operational amplifier 72
The voltage from the / A conversion unit 71 and the offset voltage are added. Here, an output voltage of -10 to -15 V is obtained. This voltage is applied to the anode of the variable capacitance diode D2. The output voltage of the operational amplifier 72 is inverted by the inverting amplifier 73, and a voltage of +10 to +15 V is applied to the cathode of the variable capacitance diode D1. Variable capacitance diode D
1 and D2 receive the reverse bias voltage and change the capacitance. The above operation is repeated to obtain desired characteristics.
The next time the input capacity is calibrated, the memory 6
Calibration is performed with a bias value at which a desired characteristic can be obtained from. When the calibration is completed, connect DUT1 and
Perform 1 test.

Next, the variable capacitance diode D during the test
1 and D2 will be described. FIG. 6 is a diagram for explaining the operation of the variable capacitance diodes D1 and D2 during the test.
For example, +10 V is applied to the cathode of the variable capacitance diode D1.
And -10 V is applied to the variable capacitance diode D2, and the input capacitance is calibrated. The attenuated waveform before the DC superimposed waveform is input to the resistor R1 and input to the amplifier for amplifying the waveform is referred to as waveforms A and B. Here, FIG. 7 shows the reverse bias voltage-capacitance characteristics of the variable capacitance diodes D1 and D2.

When a waveform is not input, since the reverse bias voltage of 10 V is applied to both of the variable capacitance diodes D1 and D2, the capacitance is 17 pF from FIG. In total, the capacitance is 34 pF. When the waveform is input and becomes the waveform A, the capacitance of the variable capacitance diode D1 when the waveform A is 2V is 20 pF from FIG. 7 because the reverse bias voltage is 8V. The capacitance of the variable capacitance diode D2, a reverse bias voltage is because it is 12V, a 15pF from FIG. Variable capacitance diode D
Since the sum of the capacitances of 1 and D2 is 35 pF, the capacitance hardly changes as a sum. Therefore, even if a DC superimposed waveform is input, the input capacitance does not deteriorate, and a waveform having good characteristics as shown by the solid lines of the waveforms A and B can be obtained.

However, when the input capacitance is adjusted only by the variable capacitance diode D2, the waveforms A and B are as shown by broken lines. That is, due to the change in the voltage of the input waveform, the capacitance of the variable capacitance diode D2 is smaller in the waveform A than in the case where the input capacitance is adjusted, and the compensation is excessive. In the case of the waveform B, the capacitance of the variable capacitance diode D1 becomes large, and the compensation becomes too small.

As described above, since the positive voltage is applied to the cathode of the variable capacitance diode D1 and the negative voltage is applied to the anode of the variable capacitance diode D2, even if a DC superimposed waveform is input during the test, the input capacitance can be reduced. The test can be performed without making it worse. Then, even when an overcurrent is input, the overcurrent flows through the variable capacitance diode D1 or the variable capacitance diode D2, so that there is no need to provide a protection circuit for the amplifier 3 against the overcurrent. Further, the variable capacitance diode D1
Protects the amplifier 3 from a positive overvoltage and the variable capacitance diode D2 protects the amplifier 3 from a negative overvoltage, so that there is no need to provide a protection circuit for the amplifier 3 against overvoltage.

The actual variable capacitance diodes D1, D
The relationship between the total input capacitance of No. 2 and the input voltage will be described. FIG. 8 is a diagram showing the relationship between the total input capacitance of the variable capacitance diodes D1 and D2 and the input voltage. In FIG, Vin is an input voltage input to the resistor R1, V _B is the reverse bias voltage applied to the variable capacitance diode, Ca is the input voltage Vin is an input capacitance of the variable capacitance diodes D1, D2 when the 0. Cb is the input capacitance of the variable capacitance diode D1 when the input voltage Vin is V, or the input voltage Vin.
Is the input capacitance of the variable capacitance diode D2 when −V is −V. Cc is the input capacitance of the variable capacitance diode D2 when the input voltage Vin is V, or the input capacitance of the variable capacitance diode D1 when the input voltage Vin is -V.

When the input voltage Vin is 0, the total capacitance of the variable capacitance diodes D1 and D2 is 2Ca. And
Variable capacitance diode D1, when input voltage Vin is ± V
The total input capacitance of D2 is Cb + Cc. Here, FIG.
As is clear from FIG. 5, when the input voltage Vin changes, the total capacitance slightly differs but becomes substantially the same. In addition, if the range in which the input voltage Vin changes is reduced, the total amount of change in capacitance is reduced, and a test with better characteristics can be performed.

FIG. 9 shows the relationship between input capacitance and input voltage when the reverse bias voltage is different. The same components as those in FIG. 8 are denoted by the same reference numerals. Here, V ₁ <V ₂ <V ₃ (V ₁ , V
₂ , V ₃ : constant). As is apparent from the figure, if the reverse bias voltage increases, the total input capacitance of the variable capacitance diodes D1 and D2 hardly changes even if the input voltage Vin changes. Therefore, if the reverse bias voltage is set high, a test with better characteristics can be performed even if the input voltage changes.

FIG. 1 is a configuration diagram showing another variable capacitance section.
0 is shown. The same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, D3 is a first variable capacitance diode, whose anode is connected to the ground potential point, and whose cathode is connected to the other end of the resistor R1 via a capacitor C4. D4 is a second variable capacitance diode whose cathode is connected to the ground potential point and whose anode is connected to the other end of the resistor R1 via a capacitor C5. Here, the capacitors C4 and C5 cut DC components. Then, a positive voltage is applied from the voltage supply unit to the cathode of the variable capacitance diode D3 via the coil L1, and a negative voltage is applied to the anode of the variable capacitance diode D4 via the coil L2. Here, coil L
1, L2 cuts the AC component.

The same effect can be obtained by making the input portion of the waveform such a configuration. The combination of the variable capacitance diode of the device of FIG. 5 and the variable capacitance diode of the device of FIG. 10 is also included in the present invention. For example, the variable capacitance diode D1 and the variable capacitance diode D4 are used. The present invention also includes a configuration in which the CPU includes a waveform signal generating unit and a capacitance adjusting unit.

Further, the embodiment of the present invention is not limited to the above-described one. In the apparatus shown in FIG. 4, the D / A converter 51 and the comparator 52 are not provided with the multiplexer 40 but in the pin electronics section. Alternatively, the DFC 61 may receive the outputs from all the comparators 52.

Further, the variable capacitance section may be a switched capacitor, that is, a configuration in which the capacitance is changed with the frequency. Further, a configuration may be adopted in which a plurality of capacitors are selected and switched to change the capacitance.

[0037]

According to the present invention, the first and second capacitance adjusting means can be used .
By adjusting the capacitance of the second variable capacitance diode , the input capacitance can be automatically calibrated without variation for each pin, so that a high-speed and high-accuracy test can be performed. The first variable capacitance diode has a positive reverse
Negative voltage to the second variable capacitance diode
Because a bias voltage was applied, a DC superimposed waveform was input during the test.
Test without deteriorating input capacitance.
You. Then, even if an overcurrent is input, the first and second
Overcurrent flows through the variable capacitance diode of
There is no need to provide a protection circuit for this. In addition, the first
A variable capacitance diode protects against positive overvoltage and a second variable
Capacitive diodes protect against negative overvoltages,
There is no need to provide a protection circuit for

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the apparatus of FIG.

FIG. 3 is a diagram illustrating a calibration operation.

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing a third embodiment of the present invention.

FIG. 6 shows variable capacitance diodes D1 and D2 during a test.
It is a figure explaining operation of.

FIG. 7 is a diagram showing the reverse bias voltage-capacitance characteristics of the variable capacitance diodes D1 and D2.

FIG. 8 is a diagram showing the relationship between the total input capacitance of the variable capacitance diodes D1 and D2 and the input voltage.

FIG. 9 is a diagram showing the relationship between input capacitance and input voltage when the reverse bias voltage is different.

FIG. 10 is a configuration diagram showing another variable capacitance unit.

[Explanation of symbols]

 Reference Signs List 1 DUT 4 Waveform measurement unit 5 CPU 7 Voltage supply unit D1, D2, 31 Variable capacitance diode 10, 61 DFC 21 Signal conversion unit 33, 51 D / A conversion unit 50 WFD 52 Comparator 60 DSP 70 TSC

Continued on the front page (72) Inventor Hideo Doi 2-9-132 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Corporation (72) Inventor Kenji Uda 2-9-132 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Co., Ltd. In-company (72) Inventor Muneo Ishibachi 2-93-2 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Corporation Inspector Yasuhiro Koshikawa (56) References JP-A-59-137867 (JP, A) JP-A Sho 55-147368 (JP, A) Japanese Utility Model 2-1469 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28 G01R 15/00-17/22 G01R 27 / 00-27/32

Claims (4)

(57) [Claims] 1. A IC tester for testing of the IC, and the waveform signal generating means for generating a square wave, anode in a signal path for inputting a signal from the IC to be tested
A first variable capacitance diode which connects de, cathodic said signal path for inputting a signal from the IC
A second variable capacitance diode for connecting a diode, a positive voltage is applied to a cathode of the first variable capacitance diode , and a negative voltage is applied to an anode of the second variable capacitance diode to adjust the capacitance. A square wave from the waveform signal generating means is input to the signal path instead of the signal from the IC under test, and two points having different square waves are measured. An IC tester wherein the first and second variable capacitance diodes are adjusted by capacitance adjusting means so as to minimize the difference between the first and second variable capacitance diodes. 2. An IC tester for testing an IC under test.
There are a waveform signal generating means for generating a square wave, a signal path for inputting a signal from the tested IC, con
Connect the cathode through a capacitor and connect the anode to the ground potential point.
A first variable capacitance diode for connecting a circuit and a signal path for inputting a signal from the IC under test.
Connect the anode through a capacitor and connect the cathode to the ground potential point.
A positive voltage is applied to a second variable capacitance diode for connecting a diode and a cathode of the first variable capacitance diode.
And a negative voltage on the anode of the second variable capacitance diode.
And a capacitance adjusting means for adjusting the capacitance , wherein the square wave from the waveform signal generating means is
When the signal is input to the signal path instead of the signal from the IC,
Then, measure two different points of the square wave and minimize the difference between the two points.
So that the first and second variable capacitance diodes are
An IC tester characterized by adjusting by an adjusting means. 3. An IC tester for testing an IC under test.
And a signal path for inputting a signal from the IC under test
A first variable-capacitance diode connected to the circuit and a signal path for inputting a signal from the IC under test.
A second variable capacitance diode which connects de, a positive voltage to the cathode of said first variable capacitance diode
And a negative voltage on the anode of the second variable capacitance diode.
IC tester being characterized in that provided a voltage supply unit, a giving. 4. An IC under test is a liquid crystal display driver.
4. A method according to claim 1, wherein
The described IC tester.