KR0165698B1 - Ic tester - Google Patents

Abstract

[Objective] It is a relatively simple configuration to realize an IC tester that can be tested with an IC that outputs multiple level signals with high accuracy in a short time.

[Configuration] In an IC tester for testing ICs that output various levels of signals, a signal generator for inputting a test signal to the IC under test, a pin electronics portion connected to the output system of the IC under test, and this pin electronics And a selector for selecting a signal from the input, a digitizer for sampling and digitally inputting the output signal of the selector, and a data processor for performing measurement processing based on the data of the digitizer.

Description

IC tester

1 is a block diagram of one embodiment of the present invention.

2 is a timing chart for explaining the operation of FIG.

3 is a diagram showing a specific configuration of an electric circuit accommodated in a test head portion of the IC tester of the present invention.

4 is a diagram showing a specific configuration of the IC tester main body of the present invention.

FIG. 5 is a diagram showing a specific configuration of the attenuator 31 used in the pin electronic portion 30 of FIG.

6 is a flowchart showing the operation of the apparatus of FIG.

7 is a diagram for explaining a calibration operation.

8 is a block diagram showing another embodiment of an apparatus for calibrating an input capacitance.

9 is a diagram showing another specific configuration example of the variable capacitance portion.

FIG. 10 is a diagram for explaining the operation of the variable capacitance diodes D1 and D2 during the test. FIG.

11 shows reverse bias voltage-capacitance characteristics of the variable capacitance diodes D1 and D2.

12 is a diagram showing the relationship between the input capacitance and the input voltage of the variable capacitance diodes D1 and D2.

13 is a diagram showing a relationship between an input capacitance and an input voltage when the reverse bias voltages are different.

14 is a configuration diagram showing another variable capacitance portion.

FIG. 15 is a diagram showing an embodiment of an apparatus that does not require calibration of input capacitance. FIG.

FIG. 16 is a diagram showing a relationship between a control signal of the control unit 15 and a voltage output from the power supply unit 14. FIG.

17 is a block diagram of an example of a conventional liquid crystal step control driving IC tester.

* Explanation of symbols for main parts of the drawings

1: DUT 2: Digital Driver

3: power supply circuit 4: measuring circuit

5 controller 6 signal generator

10: DFC 11: waveform generator

12: waveform measurement unit 13: measurement operation unit

14: power supply unit 15: control unit

20, 30: pin electronics 21: signal converter

31, 35: attenuator 32, 34, 42: buffer amplifier

33,501: D / A converter 40: scanner, multiplexer

41: analog multiplexer 50: scan control unit

51: counter unit 52: counter control unit

60: digitizer (WFD unit) 61: A / D conversion unit

62, 100: memory 63: control unit

70: data processing unit (DSP unit) 71: data memory

72: DSP 73: code memory

80: test system controller 81: module controller

82: main CPU 90: performance board

91: signal conversion unit 310: variable capacitance diodes (D1, D2)

331: D / A converter 332: Operational Amplifier

333: inverting amplifier 502: comparator

600: Digital Function Module (DFC) C1 to C5: Capacitor

DUT: Liquid Crystal Phase Control Driving IC DNL: Differential Linearity

EA, EB: Amplitude INL: Integral linearity

L1, L2: coil R1, R2: resistance

SW: switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for testing ICs for outputting various levels of signals, i.e., an IC for driving the liquid crystal phase control, and more particularly to a novel apparatus capable of high-speed and high-precision testing.

Fig. 17 is a block diagram showing an example of an IC tester for testing a conventional liquid crystal phase control driving IC.

In Fig. 17, reference numeral 1 denotes a liquid crystal phase control driving IC (hereinafter referred to as a DUT) to be an IC under test, and shows an example of an analog switch system used for horizontal driving in driving an active matrix of a liquid crystal panel. . The DUT 1 has, for example, 160 system outputs, for example, inputs 3 bits of display data, and operates from 8 voltage levels for driving a liquid crystal based on a combination of eight types of bits of the display data. A corresponding level is selectively output to each output system. In this example, the liquid crystal is displayed with eight levels of adjustment. 2 is a digital driver, which supplies three bits of display data for test, a data input control signal, and the like to the DUT 1. 3 is a power supply circuit for driving the liquid crystal, and in this example, 8 power supply voltages having different voltage levels are supplied. 4 is a measurement circuit, and a comparator is provided in each output system, in order to determine the output level of each output system individually in parallel. 5 is a control part, and controls each part, receiving data between the digital driver 2 and the measurement circuit 4. As shown in FIG.

In such a configuration, the DUT 1 selects the power supply voltage applied from the power supply circuit 3 in accordance with the display data input from the digital driver 2 under the control of the control unit 5 and simultaneously outputs the respective output systems. Output in parallel. The measurement circuit 4 measures whether the output voltage of the DUT 1 is at a predetermined level corresponding to the display data output from the digital driver 2 under the control of the control unit 5, and then controls the control unit ( Output to 5). Such measurement is performed for all levels, and the control unit 5 determines the quantity and defect of the DUT 1 based on these measurement results. However, according to such a conventional configuration, the reference level of the comparator must be changed in accordance with the voltage level output from the DUT, resulting in complicated circuit configuration and control.

And, since the measurement resolution is limited to the performance of the comparator, high resolution is difficult to obtain when the number of step adjustments is increased.

In addition, since the measurement circuits are individually connected to the respective output systems of the DUT, there is also a problem that the apparatus size becomes large and the cost increases.

SUMMARY OF THE INVENTION The present invention solves such a conventional problem, and its object is to realize an IC tester which can be tested with high accuracy in a short time by a test of an IC which outputs various level signals with a relatively simple configuration.

In order to solve such a problem, the present invention provides an IC tester for testing an IC that outputs various levels of signals, wherein the signal generator is configured to input a test signal to an IC under test, and is connected to an output system of the IC under test. A pin electronics unit, a selector for selecting a signal from the pin electronics unit, a digitizer for sampling and digitally inputting an output signal of the selector, and data for measurement processing based on the data of this digitizer A processing unit is provided.

The IC under test outputs a predetermined analog output signal to each output system based on the test signal input from the signal generator. The analog output signal of each output system of the IC under test is selectively input to the digitizer through the pin electronics section and the selector section. The digitizer samples the analog signal of the selector and inputs it digitally. Based on the measurement data input by the digitizer, the data processing unit performs measurement processing such as the quantity of the measurement target IC, the defect determination, or various statistical calculations.

EXAMPLE

Embodiments of the present invention will be described below using the drawings.

1 is a block diagram of an embodiment of the present invention, in which parts identical to those in FIG. In FIG. 1, 6 is a signal generator, and when the DUT 1 is an analog switch type, it is a test signal for step adjustment driving, similar to the digital driver 2 of FIG. 17, for example, a 3-bit waveform as shown in FIG. Data or control signals are output, and when the DUT 1 is an analog operation ampoule system, it outputs analog data as shown in FIG. 2B and a sample fold control signal (not shown). 40 is an optional scanner (multiplexer section), which is connected to the output system of the DUT 1 via the pin electronics unit 30, and selectively digitizes the output V _OUT equal to the second c degree of any limit cylinder. Output to the A / D converter used as). The digitizer 60 samples the output signal of this scanner 40, converts it into a digital signal, and sends it to the digital signal processor used as the data processing unit 70. The data processing unit 70 performs various measurement processing based on the output data of the digitizer 60. The signal generator 6 also supplies a timing signal for operating the scanner 40, the digitizer 60, and the data processor 70 in synchronization.

The operation of such a device will be described.

2 is a timing chart showing an example of the relationship between the input and the output of the DUT 1 as described above. FIG. 2A shows the 3-bit waveform data D _{0 to} D ₂ input from the signal generator 6 in the case where the DUT 1 is an analog switch system, and FIG. 2B shows that the DUT 1 performs analog operations. The analog data input from the signal generator 6 in the case of the muffler type is shown. FIG. 2C shows the output of the DUT 1 when these waveform data D _{0 to} D ₂ or analog data are input. The example is a state in which the voltage V _OUT is changed and the three system outputs of R, G, and B are sequentially converted into the scanner 40 and measured. In FIG. 2, when the 64-step adjustment output is input in a time relationship of 1-step adjustment / ㎲, the 64-step adjustment output of three systems of R, G, and B can be input as about 12.5 1.

As the selection mode of the output system of the DUT 1 by the scanner 40,

① A method of converting and selecting the output system sequentially while maintaining the output voltage V _OUT shown in FIG. 2C at a constant value.

② For each output system, there are two ways to change the output voltage V _OUT from 0 to the maximum level and convert to the next output system as shown in Fig. 2c. Several measurement data are entered according to the step adjustment number.

The digitizer 60 converts the output voltage V _OUT output from the scanner 40 to the data processing unit 70 regardless of the selection mode of the scanner 40 as described above. In the sampling, each output voltage level of each output system is performed several times.

As a result, the data processor 70 receives various measurement data for each step control output pressure for each output system. The data processing unit 70 executes various arithmetic processing based on the measured data input in this way. The types of arithmetic processing are largely related to statistical processing such as averaging or histogramming the measurement data itself, and to evaluating the characteristics of the DUT 1 taking measurement data based on statistical processing results.

These characteristics evaluation items include the presence or absence of disconnection of each output system, the dispersion of the step-control output voltage between each output system, the integral linearity (INL), the differential linearity (DNL), the γ compensation amount, and the rising and falling characteristics resulting from the conversion. have. In the determination of the quality and defect of the DUT 1, for example, the data processing unit 70 stores the allowable range data of each characteristic evaluation item in advance, and can determine whether or not the measurement result is within the allowable range.

In this way, high-precision various characteristic evaluation can be performed at high speed with a relatively simple structure compared with the conventional one.

In FIG. 1, an example in which only one measurement system is used has been described, but the same measurement system is formed in each of three colors of R, G, and B, so that the test of the color display driver IC can be efficiently performed. In this way, it is possible to measure crosstalk or interference between R, G, and B by forming measurement systems of various systems.

In addition, since the resolution of the step adjustment becomes stepless in the analog operation method of the DUT, the effect of the test apparatus according to the above embodiment is effectively exhibited. That is, the output voltage of the DUT continuously changes in accordance with the input analog picture signal. Therefore, by digitizing with a sampling period sufficiently shorter than the period of the analog image signal, the correspondence between the analog image signal and the output voltage of each output system can be measured at high speed, high resolution, and high accuracy. By studying the analog image signal waveforms input from the signal generator to the DUT, various analog measurements, which were not possible with conventional comparator methods such as linearity test and distortion test, can be performed.

Next, a specific configuration of the IC tester will be described below.

3 is a diagram showing a specific configuration of an electric circuit accommodated in the test head portion of the IC tester of the present invention.

4 is a diagram showing a specific configuration of the IC tester main body of the present invention.

In Fig. 3, 20 is a pin electronics unit, which is a digital function module (hereinafter, abbreviated as DFC and not shown), which is a signal generator, and interfaces with the DUT 1, and has a driver and a comparator.

The pin electronics section 30 is an interface between the output pin of the DUT 1 and the multiplexer section 40 serving as the selection section. The pin electronics unit 30 is connected to the attenuator 31 and the load resistor R, respectively, via relays RL1 and RL2 that do not connect the DUT 1. The attenuator 31 is connected to the multiplexer section 40 through the buffer amplifier 32.

The load resistor R is connected to a common DC measuring unit (not shown) of the pin electronics unit 20.

The multiplexer 40 is composed of an analog multiplexer 41 and a buffer amplifier 42.

Reference numeral 50 denotes a scan controller, which controls the analog multiplexer 41. The scan / control section 50 is composed of a counter section 51 and a counter control section 52. Only the signals of the pins designated by the counter clock synchronized with the digital pattern output by the DFC are sequentially raised. The signal is selected by the analog multiplexer 41 arbitrarily in descending order.

In FIG. 4, a waveform digitizer (hereinafter, referred to as a WFD section) is used as the digitizer 60. The output signal selected by the analog / multiplexer 41 of FIG. 3 is sampled through the buffer amplifier 42. To enter. The WFD unit 60 is composed of an A / D conversion unit 61, a memory 62, and a controller 63. The A / D converter 61 controlled by the controller 63 converts the output signal of the output system selected by the analog multiplexer 41 into digital data and stores it in the memory 62. . Synchronization with a digital pattern is possible, and voltage measurement is realized after a designated time after the DUT 1 outputs a signal. Since only the necessary portion is stored in the memory 62, even if the output pin of the DUT 1 is several pins (200 pins or more), a large capacity memory is not required.

The DSP unit 70, which is a data processing unit, performs measurement processing based on the data stored in the memory 62. The DSP unit 70 is composed of a data memory 71, a DSP 72, and a code memory 73.

80 is a test system controller (hereinafter, abbreviated as TSC) and is composed of a module controller unit 81 and a main CPU 82.

The module controller unit 81 controls the WFD unit 60 and the DSP unit 70.

The main CPU 82 controls the entire apparatus.

The operation of such a device is described below.

Through the driver of the pin electronics unit 20 from the DFC, a digital pattern as shown in FIG. 2A is input to each input pin of the DUT 1. The DUT 1 outputs a signal as shown in FIG. 2C from each output pin based on the digital pattern. The output signal is input to the multiplexer 40 through the pin electronic unit 30. The multiplexer section 40 selects the output system of the DUT 1 in the order controlled by the scan / control section 50. The WFD unit 60 converts the signal from the multiplexer unit 40 by the A / D conversion unit 61, and causes the memory 62 to gear as digital data. Data is transferred from the memory 62 to the memory 71 through a dynamic memory access controller (not shown). The DSP 72 extracts data from the data memory 71 and performs measurement processing designated by the code memory 73. The measurement process, for example, classifies the data into large order and small order. The main CPU 82 receives the result processed by the DSP unit 70 through the module controller 81, and determines whether the signal output from the DUT 1 is within the specified voltage based on the processing result. .

In this way, the signal generator may be a DFC outputting only a digital signal or a device outputting only an analog signal.

Then, the input capacitance calibration in the above apparatus will be described below.

5 is a diagram showing a specific configuration of the attenuator 31 used in the pin electronic portion 30 of FIG.

In the drawing, reference numeral 10 denotes a DFC as a timing generator, a pattern generator, a pattern memory, and a fail memory, and outputs various digital signals. 90 is a performance board mounted during calibration, and is electrically connected to the DFC 10 and the pin electronics unit 30. During the test, the performance board 90 is disconnected and the performance board connecting the DUT is replaced. Is a memory, and stores the calibration value finally adjusted by the TSC 80.

In the performance board 90, 91 is a signal conversion section, and the digital signal from the DFC 10 is converted into a large amplitude signal having a good synergistic characteristic and applied to each pin electronic section 30.

In the attenuator 31, C1 is a condenser and is connected in parallel with the resistor R1. 310 is a variable capacitance diode which is a variable capacitance portion and is provided between the other end of the resistor R1 and the ground potential potential point.

One end of the buffer amplifier 32 is connected to the resistor R1 and outputs a waveform from the resistor R1. 33 denotes a D / A converter, which outputs a reverse bias voltage applied to the variable capacitor diode 310 by the TSC 80.

Here, the signal generator to be calibrated is composed of a DFC (10) and a signal converter 21, the capacitance adjusting means is WFD 60, DSP 70, TSC 80 and D / A converter ( 33).

The operation of calibration of such a device is described below.

6 is a flowchart showing the operation of the apparatus of FIG.

7 is a diagram for explaining the operation of the calibration.

FIG. 7A is a case of compensating the variable capacitance diode 310, and FIG. 7B is a case of compensating excessive compensation of the variable capacitor diode 310. FIG.

The TSC 80 selects the multiplexer 40 to select the pin electronics 30 of CH1. The minimum reverse bias voltage is output to the D / A converter 33 of the pin electronics unit 30 of CH1. In addition, a digital signal is output to the DFC 10 to provide a signal from the signal converter 91 to the pin electronics 30. The WFD unit 60 measures signals through the pin electronic unit 30 and the multiplexer unit 40. The DSP unit 70 calculates δ (= EA-EB) from the amplitude EA at time A and the amplitude EB at time B as shown in FIG.

In the case of EAEB, that is, in FIG. 7B, the compensation is excessive, so the capacitance of the variable capacitance diode 310 must be increased. To this end, the capacitance is increased when the reverse bias voltage applied to the variable capacitor diode 310 is reduced. However, since the D / A converter 33 gives the minimum voltage value to the variable capacitor diode 310, this abnormal capacitance cannot be increased. Thus notifying the operator that the calibration has failed.

In the case of EAEB, the maximum reverse bias voltage is output to the variable capacitance diode 310 by the D / A converter 33. In the case of EAEB, that is, the compensation is too small in FIG. 7A, the capacitance of the variable capacitance diode 310 must be reduced.

To this end, if the reverse bias voltage applied to the variable capacitor diode 310 is increased inversely to the above, the capacitance becomes small.

However, since the D / A converter 33 gives the maximum voltage value to the variable capacitor diode 310, it is impossible to reduce the capacitance.

Thus notifying the operator that the calibration has failed.

In EAEB, the following operations are performed.

The TSC 80 outputs a voltage in the middle of the reverse bias voltage that the D / A converter 33 can output.

Then, the signal output from the pin electronics unit 30 is measured by the WFD unit 60 through the multiplexer unit 40, δ is obtained by the DSP unit 70, and δ ≦ ± 1 (binary value of the calculator). Check whether it is approved. When? ≤ ± 1, the TSC 80 stores the intermediate voltage value as a correction value. When the time is other than δ ≦ ± 1, the TSC 80 determines whether the amplitudes of the time A and the time B are 7a or 7b.

In the case of EAEB, that is, in FIG. 7B, the compensation is excessive, so the capacitance of the variable capacitance diode 310 must be increased. Therefore, the voltage value of the D / A converter 33 may be reduced.

In the case of EAEB, that is, in FIG. 7A, since the compensation is too small, the capacitance of the variable capacitance diode 310 must be reduced. Therefore, the voltage value of the D / A converter 33 may be increased.

By the above, the TSC 80 outputs the voltage value between the middle voltage of the D / A converter 33 and the minimum voltage value when the EAEB is used. In the case of EAEB, the D / A converter 33 outputs the voltage value between the middle voltage and the maximum voltage value that can be output.

Then, the signals output from the pin electronics unit 30 are measured by the WFD unit 60 through the multiplexer unit 40, and δ is obtained by the DSP unit 70 to check whether δ ≦ ± 1. When? ≤ ± 1, the TSC 80 stores the voltage value as a correction value. When?? +1, the TSC 80 calculates again whether the amplitude of the A time point and the B time point is in FIG. 7a or 7b. Then, binary search is performed as described above.

The above binary search is performed up to? The TSC 80 stores the reverse bias voltage value applied to the variable capacitor diode 310.

The TSC 80 selects the pin electronics 30 of CH 2 by the multiplexer 40, and applies a minimum voltage and a maximum voltage to the variable capacitance diode 310 to determine whether or not a calibration failure occurs. do. The reverse bias voltage value applied to the variable capacitor diode 310 is obtained and stored by the binary search.

This operation is repeated to the pin electronics unit 30 of 256CH, and when the calibration for all the pin electronics units 30 is completed, the calibration values for all the pin electronics units 30 in the memory 100, In other words, the reverse bias voltage value is stored.

By adjusting the capacitance of the variable capacitance diode 310 in this way, there is no dispersion for each pin and calibration of the input capacitance is performed automatically, so that a high precision test can be performed at high speed.

Other embodiments of the apparatus for calibrating the input capacitance as described above will be described below.

8 is a block diagram showing another embodiment of an apparatus for calibrating an input capacitance. The same reference numerals as those in FIG.

In the figure, 501 is a D / A conversion section, and outputs two kinds of desired voltages. 502 is a comparator, and compares the signal output from the pin electronics 30 selected by the multiplexer 40 with the voltage output from the D / A converter 501 to output a comparison result. 600 is a DFC and stores the comparison result of the comparator 502 at a desired timing.

Here, the capacity adjusting means is composed of the D / A converters 33 and 501, the comparator 502, the DFC 600, and the TSC 80.

The operation of such a device selects the pin electronics portion 30 to be calibrated by the multiplexer portion 40. The digital signal from the DFC 10 is input to the pin electronics 30 through the signal converter 91. The comparator 502 compares the signal output from the pin electronics unit 30 with the voltage output from the D / A converter 501. The DFC 600 stores the comparison result of the comparator 502. The TSC 80 determines whether to increase or decrease the voltage output by the D / A converter 33 based on the comparison result stored in the DFC 600. That is, when it is determined that the case of FIG. 7A is determined by the comparison result, the TSC 80 increases the voltage of the D / A converter 33. If it is determined that the case of FIG. 7B, the TSC 80 makes the voltage of the D / A converter 33 small. The above operation is repeated until a signal output from the pin electronics unit 30 is input between two types of low voltages output from the D / A converter 501. The other pin electronics 30 are again selected by the multiplexer 40 to perform the above operation. In this way, the input capacitance of the pin electronics unit 30 is calibrated.

In the apparatus shown in FIG. 8, the D / A converter 501 and the comparator 502 are provided for each of the pin electronics 30 instead of the multiplexer 40. The comparator 502 The output from the DFC 600 may be configured.

In more detail, the specific configuration of the variable capacitance portion is shown below.

9 is a diagram showing another specific configuration example of the variable capacitance portion.

In FIG. 11, the waveform generator is a signal generator, and generates a waveform signal.

In the attenuator 31, the waveform signal from the DUT 1 or the waveform generator 11 is input to the first resistor R1 at one end. When the DUT 1 is tested, the switch SW is open.

When the input capacitance is calibrated, the DUT 1 is disconnected, the switch SW is connected, and the waveform generator 2 is connected to the resistor R1. The capacitor C1 is connected in parallel to the resistor R1.

D1 is a first variable capacitance diode, the cathode of which is connected to the ground potential point through the capacitor C2 and the anode of which is connected to the other end of the resistor R1. The condenser C2 flows the current flow component of the current generated between the cathode and the ground potential point to the ground potential. D2 is a second variable capacitance diode, whose anode is connected to the ground potential point via a capacitor C3, and the cathode is connected to the other end of the resistor R1. The capacitor C3 flows the AC component of the current generated between the anode and the ground potential point to the ground potential point. One end of the second resistor R2 is connected to the other end of the resistor R1, and the other end thereof is connected to the ground potential point.

12 is a waveform measuring unit, which is connected to the other end of the buffer amplifier 32 and measures the waveform through the resistor R1 and the buffer amplifier 32. The TSC 80, which is an arithmetic means, calculates an inverse bias value applied to the optimum variable capacitance diodes D1 and D2 based on the measurement result by the waveform measuring unit 12. The memory 100 serving as the storage unit stores the reverse bias value obtained by the TSC 80. The D / A converter 33 applies a positive voltage to the cathode of the variable capacitance diode D1 based on the reverse bias value obtained by the TSC 80, and gives the anode of the variable capacitance diode D2 to the anode. Give negative voltage.

In the D / A converter 33, 331 is a D / A converter, and converts the reverse bias value obtained by the TSC 80 into a voltage. The D / A converter 331 is assumed to be capable of outputting 0 to 5V. 332 denotes an operational amplifier, which is added by the low voltage from the D / A converter 331 and the offset voltage (here, 10V), and a negative voltage is applied to the anode of the variable capacitance diode D2. Grant. 333 is an inverting amplifier, which inverts the output from the operational amplifier 332 and applies a positive voltage to the cathode of the variable capacitance diode D1.

Here, the variable capacitors are the variable capacitor diodes D1 and D2, and the capacitance adjusting means is the waveform measuring unit 12, the TSC 80, and the A / D conversion unit 33. In addition, although only one pin electronic part 30 is shown in figure, in fact, it is provided for every pin of the DUT1.

The multiplexer section selects the pin electronics section 30 and the waveform measuring section 12 performs the measurement.

The automatic calibration operation of the input capacitance of such a device is described below.

The switch SW is connected while the DUT 1 is disconnected. The waveform generator 11 outputs a square wave signal. The waveform measuring unit 12 measures the square wave signal passing through the resistor R1 and the buffer amplifier 32. The TSC 80 obtains the reverse bias value of the variable capacitance diodes D1 and D2 from which the desired input capacitance is obtained based on the measurement result, and sends the digital value based on the reverse bias value to the D / A converter 331. In addition, the reverse bias value is stored in the memory 100. The D / A converter 331 uses digital values as voltage values. The operational amplifier 332 then adds the voltage from the D / A converter 331 to the offset voltage. Here, an output voltage of -10 to 15V is obtained. This voltage is applied to the anode of the variable capacitance diode D2. The inverting amplifier 333 inverts the output voltage of the operational amplifier 332 and applies a voltage of +10 to + 15V to the cathode of the variable capacitance diode D1. The variable capacitance diodes D1 and D2 receive reverse bias voltages, respectively, to change capacitance.

The above operation is repeated to obtain desired characteristics. The next time the input capacitance is calibrated, the calibration is performed with a bias value from which the desired characteristic is obtained from the memory 100.

When the calibration is completed, the DUT 1 is connected and the DUT 1 is tested.

Next, the operation of the variable capacitance diodes D1 and D2 during the test will be described.

10 is a diagram for explaining the operation of the variable capacitance diodes D1 and D2 during the test.

For example, ± 10 V is applied to the cathode of the variable capacitance diode D1 and −10 V is applied to the variable capacitance diode D2, so that the input capacitance is corrected. The attenuated waveform before the DC superimposed waveform is input to the resistor R1 and input to the amplifier for amplifying the waveform is referred to as waveforms A and B. FIG.

11 shows reverse bias voltage-capacitance characteristics of the variable capacitance diodes D1 and D2.

When no waveform is input, since both of the variable capacitance diodes D1 and D2 are subjected to a reverse bias voltage of 10 V, the capacitance becomes 17 pF in FIG. In total, the capacity is 34 pF.

When the waveform is input and becomes the waveform A, the capacitance of the variable capacitance diode D1 when the waveform A is 2V becomes 20pF in FIG. 11 because the reverse bias voltage is 8V. In addition, since the reverse bias voltage is 12V, the capacitance of the variable capacitance diode D2 becomes 15 pF in FIG. Since the total capacitance of the variable capacitance diodes D1 and D2 is 35 pF, the capacitance hardly changes as a sum.

Therefore, even when the DC superimposed waveform is input, the input capacitance does not deteriorate, and a waveform having good characteristics such as solid lines of waveforms A and B is obtained.

However, when the input capacitance is adjusted only by the variable capacitance diode D2, the waveforms A and B become like broken lines. That is, when the capacitance of the variable capacitance diode D2 adjusts the input capacitance due to the voltage change of the input waveform, the capacitance becomes smaller when the waveform is A, and the compensation is excessive. In the case of waveform B, the capacitance of the variable capacitance diode D1 becomes large, and the compensation becomes too small.

In this way, a positive voltage is applied to the cathode of the variable capacitor diode D1 and a negative voltage is applied to the anode of the variable capacitor diode D2, so that the input capacitance is not deteriorated even when a DC overlapping waveform is input during the test. You can test without it.

Since overcurrent flows through the variable capacitance diode D1 or the variable capacitance diode D2 even when the overcurrent is input, it is not necessary to provide a code circuit of the buffer amplifier 32 for the overcurrent.

In addition, the variable capacitance diode D1 protects the buffer amplifier 32 from positive overvoltage, and the variable capacitance diode D2 protects the buffer amplifier 32 from negative overvoltage, thereby protecting the buffer amplifier 32 against overvoltage. There is no need to install a circuit.

The relationship between the input capacitance of the sum of the actual variable capacitance diodes D1 and D2 and the input voltage will be described below.

FIG. 12 is a diagram showing the relationship between the input capacitance of the sum of the variable capacitance diodes D1 and D2 and the input voltage.

In the drawing, Vin denotes an input voltage input to the resistor R1, Va denotes a reverse bias voltage applied to the variable capacitance diode, and Ca denotes an input capacitance of the variable capacitance diodes D1 and D2 when the input voltage Vin is zero. Cb is the input capacitance of the variable capacitance diode D1 when the input voltage Vin is V, or the input capacitance of the variable capacitance diode D2 when the input voltage Vin is -V. C _C is the input capacitance of the variable capacitance diode D2 when the input voltage Vin is V, or the input capacitance of the variable capacitance diode D1 when the input voltage Vin is -V.

When the input voltage Vin is zero, the total capacity of the variable capacitance diodes D1 and D2 is 2Ca. When the input voltage Vin is ± V, the total input capacitance of the variable capacitance diodes D1 and D2 is Cb + C _C.

Here, as is apparent from FIG. 12, when the input voltage Vin changes, the total capacitance is slightly different, but is approximately the same. In addition, if the range in which the input voltage Vin changes is small, the amount of change in the total capacitance becomes small, so that a test having better characteristics can be performed.

Therefore, Fig. 13 shows the relationship between the input capacitance and the input voltage when the reverse bias voltages are different. The same thing as FIG. 12 attaches | subjects the same code | symbol.

Here, V ₁ V ₂ V ₃ (V ₁ , V ₂ , V ₃ : integer) has a relationship.

As is apparent from the figure, when the reverse bias voltage increases, the input capacitance of the sum of the variable capacitance diodes D1 and D2 hardly changes even when the input voltage Vin changes.

Therefore, if the reverse bias voltage is set large, better characteristics can be tested even if the input voltage changes.

14 is a block diagram showing another variable capacitor.

The same symbols as in Fig. 9 are given the same reference numerals.

In the figure, D ₃ is the first variable capacitance diode, and the anode is connected to the ground potential point and the cathode is connected to the other end of the resistor R1 through the capacitor C4. D4 is the second variable capacitance diode, the cathode is connected to the ground potential point, and the anode is connected to the other end of the resistor R1 through the capacitor C5. Here, the capacitors C4 and C5 cut the direct current component. A positive voltage is applied to the cathode of the variable capacitor diode D3 through the coil L1 from the voltage supply unit, and a negative voltage is applied to the anode of the variable capacitor diode D4 through the coil L2. Here, the coils L1 and L2 cut the AC component. By configuring the input portion of the waveform in such a configuration, the same effect can be obtained. Also included in the present invention is a combination of the variable capacitance diode of the device of FIG. 9 and the variable capacitance diode of the device of FIG. For example, the variable capacitance diode D1 and the variable capacitance diode D4 are configured.

The variable capacitor may be configured to change the capacitance with a switch capacitor, that is, a frequency. In addition, a configuration may be employed in which a plurality of capacitors are selected and converted to change the capacitance.

In addition, the apparatus which does not require correction of the above input capacitance is demonstrated below.

FIG. 15 is a configuration diagram showing an embodiment of the apparatus that does not require calibration of the input capacitance.

In the drawing, 34 in the pin electronics unit 30 is a buffer amplifier and inputs a signal output from the DUT 1. 35 is an attenuator, is made of low resistance, and attenuates the signal from the buffer amplifier 34.

13 is a measurement operation unit which is a test unit and tests the DUT 1 by a signal from the attenuator 35. Numeral 14 denotes a power supply unit and applies a voltage corresponding to the output voltage range of the signal output from the DUT 1 to the buffer amplifier 34. 15 is a control part, and outputs a voltage to the power supply part 14 in correspondence with the DUT 1. Then, the power supply unit 14 provides the measurement computing unit 13 with the midpoint front position of the potential applied to the buffer amplifier 34.

In the attenuator 35, the resistors R3 and R4 are resistors of several hundreds of kΩ. One end of the resistor R3 is connected to the buffer amplifier 34, and the other end thereof is connected to the measurement operation unit 13. The resistor R4 has one end connected to the other end of the resistor R3, and the other end is grounded.

Here, similarly to FIG. 9, in the drawing, only one pin electronic unit 30 is shown, but is actually provided at each pin of the DUT 1. The multiplexer section selects the pin electronics section 30, and the measurement calculation section 13 performs the measurement.

The operation of such a device is described below.

FIG. 16 is a diagram illustrating a relationship between a control signal of the controller 15 and a voltage output from the power supply unit 14.

Here, as the DUT 1, three types of liquid crystal drivers having an output voltage of ± 10 V, 0 to +20 V, and -20 to 0 V are fixed.

① Output voltage is ± 10V.

The control part 15 gives the power supply part 14 the signals 0 and 0 of control signals CTRL2 and CTRL1, respectively, and notifies the measurement calculation part 13 to 0V of the intermediate point all positions. The power supply unit 14 applies a voltage of -15V and + 15V to the buffer amplifier 34. As a result, the buffer amplifier 34 can input a signal in the range of -15V to + 15V. In practice, you can input a voltage of about ± 12V. A signal is supplied from the signal generator (not shown) to the DUT 1, and the DUT 1 outputs a signal corresponding to the input signal. The measurement operation unit 13 measures this signal through the buffer amplifier 34 and the attenuator 35, and performs calculation based on the measurement result and all positions of the intermediate point to determine the quantity and defect of the DUT 1.

② When output voltage is 0 ~ ± 20V.

The control part 15 gives the power supply part 14 the signal whose control signals CTRL2 and CTRL1 are 0 and 1, respectively, and informs the measurement calculation part 13 of the intermediate point whole position + 10V. The power supply unit 14 applies a voltage of -5V and + 25V to the buffer amplifier 34. As a result, the buffer amplifier 34 can input a signal in the range of -5 to + 25V. In practice, a voltage of about -2 to 22V can be input. Similarly, a signal is supplied from the signal generator to the DUT 1, and the DUT 1 outputs a signal corresponding to the input signal. The measurement operation unit 13 measures this signal through the buffer amplifier 34 and the attenuator 35, and performs calculation based on the measurement result and all positions of the midpoint, and determines whether the DUT 1 is good or bad.

③ When output voltage is -20 ~ 0V.

The control part 15 gives the power supply part 14 the signal of control signals CTRL2 and CTRL1 to 1 and 0, respectively, and notifies the intermediate point all position -10V. The power supply unit 14 applies a voltage of -25V and + 5V to the buffer amplifier 34. As a result, the buffer amplifier 34 can input a signal in the range of -25 to + 5V. In practice, a voltage of about -22 to 2V can be input. Similarly, a signal is supplied from the signal generator to the DUT 1, and the DUT 1 outputs a signal corresponding to the input signal. The measurement operation unit 13 measures this signal through the buffer amplifier 34 and the attenuator 35, and performs calculation based on the measurement result and all positions of the midpoint, and determines the quantity and defect of the DUT 1.

In this way, since the power supply unit 14 applies the voltage to the buffer amplifier 34 according to the type of the DUT 1, the capacity of the buffer amplifier 34 can be utilized to the full, and the attenuator 35 is the rear end of the buffer amplifier 34. Can be installed on That is, since the attenuator 35 can be formed with a low resistance of several hundreds of microseconds, even if there are several pF of floating capacitance around the attenuator 35, the time constant of the CR circuit composed of the resistance of the attenuator 35 and the floating capacitance is It becomes several hundred ns, and does not have a practical influence on the sampling time and frequency characteristic of the signal from the DUT 1. Therefore, capacity correction is unnecessary, and a high precision test can be performed.

In the embodiment, the measurement operation unit 13 inputs a signal from the DUT 1 to the A / D converter, and the DUT 1 outputs a desired voltage based on the data from the A / D converter and all positions of the intermediate point. It is constituted by a digitizer and a data processing unit, and a configuration of a test unit that determines a comparison with a desired voltage by a comparator.

As described above, the present invention has the following effects.

(a) An IC tester can be realized in which a test of an IC under test that outputs multiple level signals in a relatively simple configuration can be performed with high accuracy in a short time.

(b) By adjusting the capacity of the variable capacitor, there is no dispersion for each pin and calibration of the input capacitor is possible automatically, so that high precision test can be performed at high speed.

(c) According to the type of IC under test, the power supply unit applies a voltage to the buffer amplifier, and an attenuator composed of low resistance is provided at the rear of the buffer amplifier.

(d) Since the first variable capacitor diode and the second variable capacitor diode whose capacitance is changed by voltage are provided, the test of the IC under test can be performed without deteriorating the frequency characteristic even when the DC superimposed waveform is input at the time of measurement. can do.

Claims (7)

An IC tester for testing an IC in which a plurality of output terminals output signals of various levels, the IC tester comprising: a signal generator which is electrically connected to an input terminal of an IC under test and outputs a test signal to the IC under test, and the output of the IC under test A pin electronics section electrically connected to the system, a selection section electrically connected to the pin electronics section, for selecting a signal from the pin electronics section, and an output from the selection section, electrically connected to the selection section An IC tester comprising: a digitizer for sampling and digitally inputting a signal; and a data processor connected to the digitizer and performing measurement processing based on output data of the digitizer. 2. The pin electronics unit according to claim 1, wherein the pin electronics unit has a variable capacitor unit electrically connected to each signal path for inputting a signal from the output terminal of the IC under test, and the waveform signal from the signal generator is replaced with the signal from the IC under test. And measuring the waveform signal at the same time as inputting to the signal path, and adjusting the capacitance of the variable capacitance part based on the measurement result. 2. The pin electronics unit according to claim 1, wherein the pin electronics unit is electrically connected to an output terminal of the IC under test, and comprises a buffer amplifier and a low resistance for inputting a signal output from the IC under test, and is electrically connected to the output terminal of the buffer amplifier. And an attenuator for attenuating the signal from the buffer amplifier, and having a power supply unit electrically connected to the buffer amplifier and applying an operating voltage corresponding to the output voltage range of the signal output from the IC under test to the buffer amplifier. IC tester. An IC tester for testing an IC in which a plurality of output terminals output several level signals, the IC tester comprising: a first pin electronic portion electrically connected to a terminal to which a digital signal of an IC under test is input and outputting a digital signal; And a second pin electronics portion electrically connected to an output terminal of the IC under test and attenuating a signal output from the IC under test, and a second signal in synchronization with a digital signal output by the first pin electronics portion. A multiplexer section electrically connected to the pin electronics section of the electronic device and selecting a signal from the second pin electronics section, and electrically connected to the multiplexer section to sample and digitally input a signal from the multiplexer section. Digital signal connected to the digitizer section and performing signal processing based on data from the digitizer section An IC tester having a processor unit. An IC tester for testing an IC under test, which is electrically connected to an input terminal of the IC under test, and electrically connected to a signal generator for generating a waveform signal and each signal path for inputting a signal from the IC under test. And a capacitance adjusting means for adjusting the capacitance of the variable capacitance portion, inputting the waveform signal from the signal generation portion to the signal path instead of the signal from the IC under test, and simultaneously receiving the waveform signal. And measuring and adjusting the capacity of the variable capacitance part by a capacity adjusting means based on the measurement result. 6. The variable capacitance unit according to claim 5, wherein the variable capacitance unit comprises: a first variable capacitance diode electrically connected to a signal path for inputting a signal from an IC under test and an anode, and electrically connected to a battery potential point and a cathode; A signal path for inputting a signal from the IC and a second variable capacitance diode electrically connected to the cathode and electrically connected to the battery potential point and the anode; An IC tester characterized by applying a desired reverse bias voltage to a variable capacitor diode and a second variable capacitor diode. In an IC tester for testing an IC under test, an input terminal is electrically connected to only an output terminal of the IC under test, a buffer amplifier for inputting a signal output from the IC under test, and a low resistance. An attenuator electrically connected to an output terminal of the attenuator, the attenuator for attenuating a signal from the buffer amplifier, an attenuator electrically connected to the attenuator, and performing a test of the IC under test by a signal from the attenuator; And a power supply unit electrically connected to the buffer amplifier to supply an operating voltage corresponding to the output voltage range of the signal output from the IC under test.