JPH10293154A - Bias power source circuit for semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bias power source circuit which does not cause ringing nor oscillation when the level of a bias power source fluctuates even when a large-capacitance electrolytic capacitor for low frequency is connected to a device to be measured at the time of conducting AC tests on the device. SOLUTION: When AC tests are performed on a device 12 to be measured, an electrolytic capacitor 10 for low frequency is connected to the device 12 in addition to a by-pass capacitor 9 for high frequency by turning on a switch 11 and, at the same time, a capacitor 7 for a compensating phase is connected to the device 12 in addition to a capacitor 6 for compensating phase connected between the output terminal and inverted input terminal of an amplifier 1 by turning on a switch 8. In this case, the occurrence of ringing or oscillation is suppressed when the level of a bias power source fluctuates by making the resultant capacitance of the capacitors 6 and 7 for compensating phase the optimum when the by-pass capacitor 9 and electrolytic capacitor 10 are connected to the device 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device to be measured (hereinafter referred to as a DU) in which a large load current is taken by an IC tester.
T) during DC and AC tests, even if the capacitive load connected to the output end of the amplifier that supplies the power supply current to the DUT changes, the ringing or oscillation occurs when the bias power supply level of the IC tester changes. The present invention relates to a bias power supply circuit for a semiconductor test device that suppresses the generation of a bias.

[0002]

2. Description of the Related Art When a DC test or an AC test of a device under test is performed by an IC tester, a bias power supply circuit for semiconductor test is used. The bias power supply circuit for semiconductor test supplies a power supply current from the IC tester to a DUT. The output terminal of the amplifier to be supplied is connected to the power supply pin of the DUT. To stabilize the bias power level of the IC tester, a high-frequency bypass capacitor and a large-capacity electrolytic capacitor as a low-frequency capacitor are connected to this power supply pin. Is connected.

However, when performing a DC test of the DUT, it is necessary to perform the test with higher accuracy. In order to disconnect the electrolytic capacitor having a large leak current from the power supply pin, a switch is provided between the electrolytic capacitor and the power supply pin. By inserting and turning off this switch, the electrolytic capacitor is disconnected from the power supply pin.

Further, in order to prevent ringing or oscillation when the power supply level fluctuates, a phase compensation capacitor is connected between the output terminal of the amplifier and the inverting input terminal (the power supply input terminal from the IC tester). ing.

FIG. 2 is a circuit diagram showing a configuration of a conventional bias power supply circuit for semiconductor test. In FIG. 2, the amplifier 1 is a DU
The power supply current is supplied from an IC tester (not shown) to T12, and its inverting input terminal is connected to the input terminal 2 via the input resistor 3. The input terminal 2 is an input terminal for supplying a power supply voltage from the IC tester to the amplifier 1. The output terminal of the amplifier 1 is connected to the power supply pin 12a of the DUT 12 via the current detection resistor 5.

A feedback resistor 4 is connected between the power supply pin 12a and the inverting input terminal of the amplifier 1. Power supply pin 12
A high-frequency bias capacitor 9 for stabilizing the bias power supply level of the IC tester is connected between a and ground, and a series circuit of a switch 11 and a large-capacity low-frequency electrolytic capacitor 10 is connected. I have. Further, a phase compensation capacitor 6 is connected between the inverting input terminal and the output terminal of the amplifier 1.

Next, the operation of the semiconductor test bias power supply circuit shown in FIG. In the DC test, a power supply voltage is supplied from the IC tester to the inverting input terminal of the amplifier 1 via the input terminal 2 and the input resistor 3, thereby supplying a power supply current from the amplifier 1 to the power supply pin 12 a of the DUT 12 through the current detection resistor 5. .

At this time, the power supply current flows through the current detecting resistor 5, and a voltage drop occurs between both ends of the resistor, and the potential difference between both ends is measured. At this time, a leak current is eliminated and high-precision measurement is performed. To turn off switch 11,
The low-frequency electrolytic capacitor 10 is kept disconnected.
As a result, no current flows through the low-frequency electrolytic capacitor 10, and a highly accurate power supply current can be measured.

Next, when an AC test of the DUT 12 is performed, the level of the bias power supply of the IC tester due to the load current of the DUT 12 is suppressed.
Is turned on and the low frequency electrolytic capacitor 10 is connected to the power pin 1
2a. In this state, the power supply voltage is supplied from the IC tester to the amplifier 1 via the input terminal 2 and the input resistor 3, and
Further, the DUT 12 passes through the current detection resistor 5 from the amplifier 1.
A power supply current is supplied to the power supply pin 12a.

At this time, the combined capacitance of the low-frequency electrolytic capacitor 10 and the high-frequency bypass capacitor 9 is connected between the power supply pin 12a and the ground.
The fluctuation in the level of the bias power supply of the IC tester due to the load current is suppressed.

[0011]

However, in the conventional bias power supply circuit for semiconductor testing as shown in FIG. 2, the phase compensating capacitor 6 connected between the output terminal and the inverting input terminal of the amplifier 1 is not connected. Since it is selected to be an appropriate value when the capacitance of the high frequency bypass capacitor 9 is connected,
Low frequency electrolytic capacitor 10 during AC test of DUT 12
When a large-capacity load like this is connected, there is a problem that ringing or oscillation occurs when the bias power supply level fluctuates.

The present invention provides a bias power supply circuit for a semiconductor test apparatus in which ringing or oscillation does not occur when a bias power supply level changes even if a large-capacity low-frequency electrolytic capacitor is connected to a power supply pin of the DUT during an AC test of the DUT. The purpose is to provide.

[0013]

In order to achieve this object, a bias power supply circuit for a semiconductor test apparatus according to the present invention comprises:
An amplifier 1 for inputting a voltage for determining an output voltage to the inverting input terminal via the input resistor 3 and supplying a power supply current to the device under test 12, and between the inverting input terminal of the amplifier 1 and the power supply pin of the device under test 12 , A current detection resistor 5 connected between the output terminal of the amplifier 1 and the power supply pin of the device under test 12, and a feedback resistor 4 connected between the inverting input terminal and the output terminal of the amplifier 1. Phase compensating capacitor 6 and a phase compensating capacitor connected between an inverting input terminal and an output terminal of amplifier 1 via switch 8 which is turned off during a DC test of device under test 12 and turned on during an AC test. 7, a high-frequency bypass capacitor 9 connected to the power supply pin of the device under test 12, and a switch that is turned off during the DC test of the device under test 12 and turned on during the AC test. Low-frequency electric field capacitor through a pitch 11 which is connected to the power pins of the device under test 12 1
0.

[0014]

Next, an embodiment of a bias power supply circuit for a semiconductor test apparatus according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. 1. In FIG. 1, the same components as those in FIG. 2 are denoted by the same reference numerals for the sake of simplicity, to avoid repeated description, and mainly different portions from FIG.

As is clear from the comparison of FIG. 1 with FIG. 2, in FIG. 1, a first phase compensating capacitor 6 is connected between the output terminal and the inverting input terminal of the amplifier 1 and a switch is provided. 8 and a series circuit of a phase compensation capacitor 7 are connected. Other configurations are the same as those in FIG.
In the embodiment, the switch 11 is referred to as a switch 11 for convenience of description because the first switch 8 is added.

Next, the operation of this embodiment configured as described above will be described. During the DC test of the DUT 12, both the switch 8 and the switch 11 are turned off. Since the switches 8 and 11 are off, the second
Of the phase compensation capacitor 7 and the electrolytic capacitor 10 for low frequency are not connected to each other.
Only the high frequency bypass capacitor 9 is connected to the power supply pin 12a of the DUT 12.

In this state, a power supply current is supplied from the input terminal 2 via the input resistor 3 to the amplifier 1 from the IC tester, and a power supply current is supplied from the amplifier 1 to the power supply pin 12a of the DUT 12 through the current detection resistor 5.

At this time, a voltage drop occurs in the current detection resistor 5, and the potential difference between both ends of the current detection resistor 5 is measured. In order to measure this potential difference with high accuracy, the switch 8 and the switch 8 are connected as described above. Since switch 11 is off,
Phase compensation capacitor 7 and low frequency electrolytic capacitor 10
Are not connected, only the high-frequency bypass capacitor 9 is connected, and leakage current is eliminated.

The capacitance value of the phase compensating capacitor 6 is selected so that the capacitance value of the phase compensating capacitor 6 becomes optimum when only the high-frequency bypass capacitor 9 is connected.

Next, a case where an AC test of the DUT 12 is performed will be described. In this case, the switch 11 is turned on to suppress the level change of the bias power supply due to the load current of the DUT 12, and the low-frequency electrolytic capacitor 10 is connected to the power supply pin 12a of the DUT 12.

As a result, the combined capacitance of the high-frequency bypass capacitor 9 and the large-capacity low-frequency electrolytic capacitor 10 is connected to the power supply pin 12a.
Although the level variation of the bias power supply is caused by the load current 12 and ringing or oscillation is generated, in this embodiment, the switch 8 is turned on simultaneously with the switch 11 being turned on.

Therefore, the phase compensating capacitor 7 is also connected between the output terminal of the amplifier 1 and the inverting input terminal, and the phase compensating capacitor 6 is connected between the output terminal of the amplifier 1 and the inverting input terminal. This means that the combined capacitance with the compensation capacitor 7 has been added.

By selecting the combined capacitance value of the phase compensating capacitor 6 and the phase compensating capacitor 7 to be optimum under the condition where the high frequency bypass capacitor 9 and the low frequency electrolytic capacitor 10 are connected, the DUT 12 Ringing or oscillation does not occur when the level of the bias power supply fluctuates during the AC test.

[0023]

According to the bias power supply circuit for a semiconductor test apparatus of the present invention, a large-capacity low-frequency electrolytic capacitor is connected to a power supply pin of the DUT together with a high-frequency bypass capacitor during an AC test of the DUT, and an amplifier is connected to the power supply pin. The first and second phase compensation capacitors are connected between the output terminal and the inverting input terminal so that the combined capacitance value thereof becomes optimal under the connection condition between the high frequency bypass capacitor and the low frequency electrolytic capacitor. Since the value is set to a value, an AC test of the DUT can be performed in a state where ringing or oscillation does not occur when the bias power supply level changes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a bias power supply circuit for a semiconductor test apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional bias power supply circuit for a semiconductor test device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Amplifier 2 Input terminal 3 Input resistance 4 Feedback resistance 5 Current detection resistance 6 Phase compensation capacitor 7 Phase paving capacitor 8 Switch 9 High frequency bypass capacitor 10 Low frequency electrolytic capacitor 11 Switch 12 DUT 12a Power supply pin

Claims (1)

[Claims] An amplifier (1) for inputting a voltage for determining an output voltage to an inverting input terminal via an input resistor (3) and supplying a power supply current to a device under test (12); Of the device under test (1
A feedback resistor (4) connected between the power supply pin of (2), and a current detection resistor (5) connected between the output terminal of the amplifier (1) and the power supply pin of the device under test (12). A first phase compensation capacitor (6) connected between the inverting input terminal and the output terminal of the amplifier (1); and A second phase compensation capacitor (7) connected between an inverting input terminal and an output terminal of the amplifier (1) via a first switch (8) that is turned on; ) And a second switch (11) that is turned off during a DC test and turned on during an AC test of the device under test (12). A low frequency electric field capacitor (10) connected to the power supply pin of the measuring device (12). Bias supply circuit for a semiconductor test apparatus according to claim.