JP2537030Y2 - LSI tester - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI tester for measuring an LSI in which an analog circuit and a digital circuit are mixed. The present invention relates to an LSI tester that can measure a signal quality with high accuracy.

[0002]

2. Description of the Related Art As the number of LSIs in which analog and digital circuits are mixed increases, an LSI tester capable of simultaneously performing analog measurement and digital measurement is required. In conventional LSI testers, if analog and digital measurements are to be performed simultaneously, the two circuits of the tester may affect each other. Is devised so as not to be damaged.

[0003]

[Problems to be Solved by the Invention] Such a conventional LS
In order to maintain the quality of the measurement signal, the I-tester has dedicated measurement output pins for analog and digital, so the number of measurement output pins becomes very large. The structure was not suitable.

The present invention has been made in view of the above-described circumstances, and an analog signal and a digital signal are transmitted to and received from a DUT through the same input / output path while maintaining the quality of a measurement signal. Reduce output pins and multi-pin LS
It is an object of the present invention to provide an LSI tester capable of measuring I.

[0005]

An SA board on which a DUT is mounted and a test signal are transmitted and received via a common source line and a common sense line, and the analog circuit and the digital circuit are mixed.
An LSI tester for inspecting a UT, wherein an analog test signal is supplied to the SA board via the source, and a signal under test output from the DUT based on the analog test signal is supplied to the sense line. And a digital test signal supplied to the SA board via the force line, and a signal under test output from the DUT based on the digital test signal is supplied to the foreground. A digital signal measuring unit to be input via a source line, and a relay for arbitrarily selecting and switching any of the signals transmitted and received between the SA board, the analog signal measuring unit, and the digital signal measuring unit. And a resistor provided between the sense line and the force line connected in the SA board, so that the influence of the sense line is exerted on the force line. It is characterized in that to measure the Rukoto without the DUT.

[0006]

The components of the present invention have the following functions. The analog signal measuring section is connected to the SA board through a common sense line and a common sense line, and exchanges test signals with an analog circuit of the LSI. The digital signal measuring section is connected to the SA board through a common foreline, and sends and receives test signals to and from a digital circuit of the LSI. The relay switches signals transmitted and received between the SA board and the analog signal measuring section and the digital signal measuring section. The resistance cancels the wiring capacitance of the sense line and maintains the quality of the digital signal measured via the force signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a measuring unit of an LSI tester according to an embodiment of the present invention. In the figure, 1 is DU
T and 2 are pin electronics boards provided in the test head for transmitting and receiving test signals to and from the SA board 5 on which the DUT 1 is mounted via a common fore line 3 and a sense line 4. R connects the source line 3 and the sense line 4 to the SA board 5
The resistors connected above have a resistance value of, for example, about 10 KΩ.

The pin electronics board 2 is a DUT
The analog measuring section 6 and the digital measuring section 7 are provided for each pin. Reference numeral 61 denotes an analog signal generator which is connected to the SA board 5 via the first switch SW1 and the force line 3, and has a DUT
1 supplies a DC voltage and a current for measuring the analog circuit. Reference numeral 62 denotes an analog signal measuring section which is connected to the SA board 5 via the second switch SW2 and the sense line 4, and which the DUT 1 outputs based on the analog test signal S1 supplied from the analog signal generating section 61. It has a four-wire system for inputting and measuring the signal under test S2.

A driver 71 is a third switch SW3.
And a digital inspection signal S3 output to the DUT 1 based on the format data D1 output from the formatter unit 72. The driver 71 determines the high-level potential and the low-level potential of the format data D1 by the signals S4 and S5 output from the reference generator 74, and converts the digital inspection signal S3 by the enable signal S6 from the formatter 72. Output.

Reference numeral 75 denotes a first comparator which is connected to the SA board 5 via the fourth switch SW4 and the force line 4 and has another pin electronics board which is similarly constructed. The high-level voltage of the signal under test S7 output from the DUT 1 is compared with the first comparison potential VrefH input from the reference generator 74 based on the digital test signal S3 supplied from the driver of the output channel. 76 is a second comparator, which is a fourth switch SW
4 and a digital test signal S3 connected to the SA board 5 via the foreline 4 and supplied from the driver 71.
Is compared with the low level potential of the signal under test S7 output from the DUT 1 and the second comparison potential VrefL input from the reference generator 74. The first and second comparators 75 and 76 output the comparison result to the formatter 72.
Output to

The formatter section 72 stores the comparison results input from the first and second comparators 75 and 76 in a format.
The data is latched by the edge and compared with the expected data value D2 to determine pass / fail. The pass / fail judgment is stored in a fail memory (not shown).
Parsed by PU. Reference numeral 78 denotes an interface unit of the CPU, which sends and receives formatter setting data to and from the formatter unit 72 and outputs data such as a high-level potential, a low-level potential, and comparison potentials VrefH and VrefL to the reference generation unit 74. . The digital measuring section 7 operates based on the rate clock input to the formatter section 72.

Next, a description will be given of how the digital measurement can be performed without being affected by the sense lines and without deteriorating the quality of the digital signal in such a circuit configuration. The sense line 4 is connected to an analog signal generator 61 having an input resistance of several tens of MΩ.
It has a wiring capacitance of about F. Since the wiring capacitance disrupts the waveform of the digital pulse, a resistor R of about 10 KΩ is provided between the force lines to cancel the influence.

By providing the 10 KΩ resistor as described above, the wiring capacitance of 20 pF is 800 KHz at -3 dB (70% cut), and apparently becomes zero pF at frequencies higher than this. That is, it can be ignored in a high frequency region of 100 MHz for measuring a digital circuit of an LSI. The resistance R of 10 KΩ is 50 to 75 of the force wire.
It is large enough for Ω, and the effects of branching can be neglected. In addition, the value is sufficiently small for the analog signal generator 61, and there is no problem when measuring the analog signal.

[0014]

[Effect of the Invention] As described in detail above, the L of the present invention
The SI tester transmits and receives analog signals and digital signals through a common sense line and foreground line. The number of output pins for measurement is reduced, and a digital circuit and an analog circuit are mixed to increase the number of pins. LSI can also be easily measured. Further, the deterioration of the signal quality of the digital signal due to the wiring capacitance of the sense line can be canceled by providing a resistor between the sense line and the force line, so that digital measurement can be performed without deteriorating the signal quality.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a measurement unit of an LSI tester showing an embodiment of the present invention.

[Explanation of symbols]

 2 Performance board 3 Force line 4 Sense line 5 SA board 7 Digital signal measuring unit 8 Analog signal measuring unit R Resistance

Claims (1)

(57) [Scope of request for utility model registration] An LS is connected to a common forcing line and a sensing line.
A test signal is transmitted to and received from a socket adapter board (hereinafter abbreviated as SA board) on which I (object to be measured, abbreviated as DUT hereinafter) is mounted, and an analog circuit and a digital circuit are mixedly mounted. An LSI tester for inspecting a DUT, wherein an analog test signal is supplied to the SA board through the force line, and a signal to be measured output from the DUT is output based on the analog test signal. An analog signal measuring unit input via the sense line and a digital test signal are supplied to the SA board via the forcing line, and the D signal is supplied based on the digital test signal.
A digital signal measuring section for inputting a signal to be measured output from the UT via the foreline, and any one of the signals transmitted and received between the SA board, the analog signal measuring section and the digital signal measuring section. And a resistor provided between the force line and the sense line connected in the SA board, and the influence of the sense line is controlled by the foreground. An LSI tester characterized in that the DUT can be measured without giving a test line.