JPH04124479U - LSI tester - Google Patents

Abstract

(57) [Summary] [Purpose] An LSI tester that can measure digital signals without compromising signal quality. [Configuration] Analog test signal is sent to SA via force line.
An analog signal measurement section that supplies the signal to the board and inputs the signal under test output from the DUT based on the analog test signal via the sense line, and a digital test signal that supplies the signal to the SA board via the force line. a digital signal measuring unit that inputs the signal under test output from the DUT based on the digital test signal via a force line, and a relay that arbitrarily selects and switches one of the signals;
An LSI tester configured with a force line connected on an SA board and a resistor provided between a sense line.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is an LSI technology that measures LSIs with mixed analog and digital circuits. For more details on the star, see Analog and digital signals on the same input/output path. Therefore, it is an LSI that can communicate with the DUT and perform highly accurate measurements with stable signal quality. Regarding testers.

0002

[Conventional technology]

As the number of LSIs with mixed analog and digital circuits increases, analog measurement There is a need for an LSI tester that can perform both digital and digital measurements at the same time. Conventional LSI testers attempt to perform analog and digital measurements at the same time. , since the tester's circuits influence each other, the analog and digital circuits influence each other. A dedicated measurement output pin is provided for this purpose to ensure that the quality of the measurement signal is not compromised. being done.

0003

[Problem that the idea aims to solve]

These conventional LSI testers use analog and Since a dedicated measurement output pin is provided for each digital signal, the measurement output pin This resulted in a very large number of devices, making the structure unsuitable for measuring LSIs with a large number of pins.

0004 The present invention was developed in consideration of these points, and is designed to maintain the quality of the measurement signal while maintaining the quality of the measurement signal. 1) Send and receive analog and digital signals to and from the DUT through the same input/output path In this way, LSI can reduce the number of measurement output pins and measure LSIs with many pins. The purpose is to provide an SI tester.

[0005]

[Means to solve the problem]

SA board with DUT mounted and test signal via common force line and sense line An LSI that transmits and receives data and inspects DUTs that have mixed analog and digital circuits. A tester, supplying an analog test signal to the SA board via the force; , the signal under test outputted by the DUT based on this analog test signal is transmitted to the sensor. an analog signal measurement section that inputs via a line; A digital test signal is supplied to the SA board via the force line, and , the signal under test outputted by the DUT based on this digital test signal is - a digital signal measuring section input via a ground line; Information exchanged between the SA board and the analog signal measurement section and digital signal measurement section. a relay that arbitrarily selects and switches any one of the signals to be transmitted; provided between the force line and the sense line connected on the SA board. with resistance, the DUT without affecting the sense line on the force line. It is characterized by being able to measure

[0006]

[Effect]

Each component of the present invention operates as follows. The analog signal measurement section is connected to the SA board with a common sense line and force line. It sends and receives test signals to and from the analog circuit of the LSI. The digital signal measurement section is connected to the SA board by a common force line, and Exchanges test signals with the SI digital circuit. The relay is exchanged between the SA board and the analog signal measurement section and digital signal measurement section. Switch each signal. The resistor cancels the wiring capacitance of the sense line and allows the device to be measured via the force signal. Maintains the integrity of digital signals.

[0007]

【Example】

An embodiment of the present invention will be described in detail below with reference to the drawings. Figure 1 shows one part of the present invention. FIG. 2 is a configuration block diagram of a measuring section of an LSI tester showing an embodiment. In the diagram, 1 is the DUT , 2 is a pin electronics board installed in the test head, with a common The SA board 5 on which the DUT 1 is mounted and the test signal are connected via the force line 3 and the sense line 4. Give and receive. R is a resistor connecting force line 3 and sense line 4 on SA board 5. For example, one with a resistance value of about 10KΩ is used.

[0008] The pin electronics board 2 is provided corresponding to each pin of the DUT 1. It is mainly composed of an analog measuring section 6 and a digital measuring section 7. 61 is an analog signal generator, which generates signals via the first switch SW1 and the force line 3. It is connected to SA board 5 and provides direct current to DUT 1 for measuring analog circuits. Supply voltage and current. 62 is an analog signal measuring section, which measures S through the second switch SW2 and the sense line 4. The analog signal connected to the A board 5 and supplied from the analog signal generator 61 Input and measure the signal under test S2 output by DUT1 based on the test signal S1 It has a 4-wire configuration.

[0009] 71 is a driver that connects the SA board via the third switch SW3 and the force line 3. 5 and outputs the format data D1 from the formatter section 72. Based on this, a digital test signal S3 is output to the DUT1. The driver 71 is driven by the signal S4,5 output from the reference generator 74. The high level potential and low level potential of the format data D1 are determined, and the format data D1 is determined. In response to the enable signal S6 from the controller section 72, a digital test signal S3 is output.

0010 75 is the first comparator, which is connected to the fourth switch SW4 and the force line 4. Other similarly configured pin electronics connected to SA board 5 Based on the digital test signal S3 supplied from the driver of the output channel of the subboard. Next, the high level voltage of the signal under test S7 outputted by DUT1 and the reference generation It is compared with the first comparison potential VrefH inputted from the section 74. 76 is a second comparator, which is connected via the fourth switch SW4 and the force line 4. Digital test signal connected to SA board 5 and supplied from driver 71 The low-level potential of the signal under test S7 output by DUT1 based on S3 and the reference It is compared with the second comparison potential VrefL inputted from the error generating section 74. The first and second comparators 75 and 76 send the comparison results to the formatter section 72. Output.

[0011] The formatter section 72 receives the input from the first and second comparators 75 and 76. The comparison result is latched by the strobe edge and compared with the expected data value D2. Makes a pass/fail decision. The pass/fail judgment is stored in a fail memory (not shown) and later transferred to the CP. Parsed by U. Reference numeral 78 denotes a CPU interface section, which communicates with the formatter section 72 and formatter setting data. At the same time, the reference generator 74 receives high-level potential and low-level potential. Data such as potential and comparison potentials VrefH and VrefL are output. Note that the digital measuring section 7 uses the rate clock input to the formatter section 72. It operates based on the standard.

0012 Next, in such a circuit configuration, digital measurements are not affected by the sense line. We will explain how it is possible to measure digital signals without degrading their quality. The sense line 4 is connected to an analog signal generator 61 having an input resistance of several tens of MΩ. In this case, the wiring capacitance is about 20 pF. This wiring electrostatic Capacitance destroys the waveform of digital pulses, so to offset this effect, A resistor R of about 10KΩ is provided between the force lines.

[0013] As mentioned above, by providing a 10KΩ resistor, the wiring capacitance of 20pF becomes , -3dB (70% cut) is 800 KHz, so at frequencies higher than this, has an apparent zero pF, and is a high frequency of 100 MHz for measuring LSI digital circuits. It can be ignored in the wave domain. Note that the resistance R of 10KΩ is sufficiently large compared to the force wire of 50 to 75Ω, and the The effect of branching can be ignored. In addition, for the analog signal generation section 61, This is a small value, so there is no problem when measuring analog signals.

[0014]

[Effect of the idea]

As explained in detail above, the LSI tester of the present invention uses a common sense line and – A device that sends and receives analog and digital signals through a Reduces the number of standard output pins, and mixes digital and analog circuits to increase the number of pins. It is also possible to easily measure LSIs that are In addition, the digital signal due to the wiring capacitance of the sense line By installing a resistor between the sense line and the force line to offset the deterioration in the signal quality of the signal, Digital measurements can be made without sacrificing quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a measuring section of an LSI tester showing an embodiment of the present invention.

[Explanation of symbols]

2 Performance board 3 Force line 4 sense line 5 SA board 7 Digital signal measurement section 8 Analog signal measurement section R resistance

Claims (1)

[Scope of utility model registration request] [Claim 1] LS via a common force line and sense line.
It transmits and receives test signals to and from the socket adapter board (hereinafter referred to as the SA board) on which the I (object under test, hereinafter referred to as DUT) is mounted, and analog and digital circuits are mixedly mounted. The LSI tester is an LSI tester for testing a DUT, which supplies an analog test signal to the SA board via the force line, and also outputs a signal under test output from the DUT based on the analog test signal. An analog signal measuring section that inputs an input via the sense line, and a digital test signal that is input to the SA board via the force line, and a
A digital signal measurement section that inputs the signal under test outputted by the UT via the force line, and any of the signals exchanged between the SA board, the analog signal measurement section, and the digital signal measurement section. and a resistor provided between the force line and the sense line connected on the SA board, the effect of the sense line is reduced by the force line. An LSI tester characterized in that the DUT can be measured without applying any voltage to the power supply line.