CN103576080A - Chip scanning voltage testing method - Google Patents
Chip scanning voltage testing method Download PDFInfo
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- CN103576080A CN103576080A CN201310574110.4A CN201310574110A CN103576080A CN 103576080 A CN103576080 A CN 103576080A CN 201310574110 A CN201310574110 A CN 201310574110A CN 103576080 A CN103576080 A CN 103576080A
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Abstract
The invention provides a chip scanning voltage testing method. The method comprises the steps of conducting chip scanning voltage testing within the larger range through larger stepping (namely the first stepping), obtaining a leaping voltage (namely the first leaping voltage) with the lower precision degree, conducting chip scanning voltage testing within the smaller range through smaller stepping (namely the second stepping), obtaining a leaping voltage (namely the second leaping voltage) with the higher precision degree, and therefore completing the whole chip scanning testing process. The testing result obtained by the scanning voltage testing method is accurate, and the required testing time is shorter.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly a kind of chip scanning voltage test method.
Background technology
Due to the rapid introducing of day by day complicated integrated circuit, material and technique, hardly may the requirement up to specification of each chip in the silicon chip of today is manufactured.For correcting the problem in manufacturing process, and guarantee that defective chip can not be sent in client's hand, in ic manufacturing process, introduced chip testing (CP, Circuit Probing).Chip testing is that the electrical parameter carrying out on silicon chip level integrated circuit in order to check the consistance of specification is measured and functional test.Test can check out each chip whether to have acceptable electric property and complete function, and the electricity specification of using in its test process is different with the difference of test purpose.If chip testing imperfection, just may cause more product to lose efficacy, finally to chip maker, bring serious consequence in client's use procedure.In the manufacture process of integrated circuit, introduce and can find early technological problems and the select chip testing of bad chip is absolutely necessary for this reason.
Chip test system generally includes: tester (Tester), probe (Probe Card) and probe station (Prober), wherein, tester is the aut.eq. that can fast, accurately, repeatedly measure submicron level electric current and millivolt step voltage on test structure; Probe is the coupling arrangement between tester and device under test; Probe station, can be in the position of X, Y and Z direction adjustment device under test also referred to as chip positioning device.During test, tester is input to curtage signal in the measured device (DUT, Device Under Test) on probe station via probe, and then this measured device is turned back to tester for the accordingly result of input signal.
In prior art, for some chip (device under test), need to do scanning voltage test, the voltage of the input signal providing to chip for reducing gradually, the leaping voltage while jumping vanishing in order to the output voltage of detection chip.In prior art, when chip is done to scanning voltage test, often there is test result not accurately or test long problem of used time.
Summary of the invention
The object of the present invention is to provide a kind of chip scanning voltage test method, to solve in prior art, when chip is done to scanning voltage test, often have test result not accurately or test long problem of used time.
For solving the problems of the technologies described above, the invention provides a kind of chip scanning voltage test method, described chip scanning voltage test method comprises:
From the first starting potential, with first step heading chip, provide the voltage reducing gradually, obtain the first leaping voltage of chip;
From the second starting potential, with second step heading chip, provide the voltage reducing gradually, obtain the second leaping voltage of chip;
Wherein, the second starting potential is that the first leaping voltage adds the first stepping, and the first stepping is greater than the second stepping, and the second leaping voltage is that chip scanning voltage tester is tested the voltage obtaining.
Optionally, in described chip scanning voltage test method, described the first stepping is 5 times～1000 times of the second stepping.
Optionally, in described chip scanning voltage test method, described the first stepping is 5mV～1V.
Optionally, in described chip scanning voltage test method, described the second stepping is 1mV～10mV.
Optionally, in described chip scanning voltage test method, described the first starting potential is 5V～10V.
Optionally, in described chip scanning voltage test method, when the chip of simultaneously testing is a slice, described the first leaping voltage is the leaping voltage of this slice chip.
Optionally, in described chip scanning voltage test method, when the chip of simultaneously testing is multi-disc, of the magnitude of voltage maximum that described the first leaping voltage is leaping voltage in this multi-plate chip.
In chip scanning voltage test method provided by the invention, by a larger stepping (i.e. the first stepping), carry out in the larger context chip scanning voltage tester, obtain the leaping voltage that a degree of accuracy is lower (i.e. the first leaping voltage); By a less stepping (i.e. the second stepping), in less scope, carry out chip scanning voltage tester again, obtain the leaping voltage that a degree of accuracy is higher (i.e. the second saltus step transformation), complete thus whole chip scanning test process.Accurate by the resulting test result of this scanning voltage method of testing, and the needed test duration is also shorter.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the chip scanning voltage test method of the embodiment of the present invention.
Embodiment
Chip scanning voltage test method the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 1, the schematic flow sheet of the chip scanning voltage test method that it is the embodiment of the present invention.As shown in Figure 1, described chip scanning voltage test method comprises:
Step S10: from the first starting potential, provide with the first step heading chip voltage reducing gradually, obtain the first leaping voltage of chip;
Step S11: from the second starting potential, provide with second step heading chip the voltage reducing gradually, obtain the second leaping voltage of chip;
Wherein, the second starting potential is that the first leaping voltage adds the first stepping, and the first stepping is greater than the second stepping, and the second leaping voltage is that chip scanning voltage tester is tested the voltage obtaining.
In the present embodiment, by a larger stepping (i.e. the first stepping), carry out in the larger context chip scanning voltage tester, obtain the leaping voltage that a degree of accuracy is lower (i.e. the first leaping voltage); By a less stepping (i.e. the second stepping), in less scope, carry out chip scanning voltage tester again, obtain the leaping voltage that a degree of accuracy is higher (i.e. the second saltus step transformation), complete thus whole chip scanning test process.Accurate by the resulting test result of this scanning voltage method of testing, and the needed test duration is also shorter.
Common, described the first starting potential is 5V～10V; In the present embodiment, described the first starting potential is 5V; In other embodiment of the application, described the first starting potential can be also 6V, 7V, 8V, 9V or 10V etc.
Preferably, described the first stepping is 5 times～1000 times of the second stepping.Further, described the first stepping is 5mV～1V, and described the second stepping is 1mV～10mV.For example, described the first stepping can be 5mV, 10mV, 20mV, 50mV, 70mV, 100mV, 150mV, 200mV, 300mV, 500mV, 800mV or 1V etc.; Described the second stepping can be 1mV, 2mV, 3mV, 4mV, 5mV, 6mV, 7mV, 8mV, 9mV or 10mV etc.Concrete, when described the first stepping is 5mV, described the second stepping can be 1mV; When described the first stepping is 20mV, described the second stepping can be 2mV; When described the first stepping is 100mV, described the second stepping can be 3mV; When described the first stepping is 1V, described the second stepping can be 5mV etc.
Further, when the chip of simultaneously testing is a slice, described the first leaping voltage is the leaping voltage of this slice chip.For example, the same time, only a slice chip is carried out to chip scanning voltage tester, during test, the first starting potential is 5V, the first stepping is 100mV, in the process that the voltage reducing is gradually provided to chip, (voltage providing to chip is 5V, 4.9V, 4.8V, 4.7V, 4.6V, 4.5V ... the rest may be inferred, until under an input voltage, the output voltage of chip is 0V, and saltus step occurs), obtain the leaping voltage of this slice chip, for example, the leaping voltage of this slice chip is 2.5V, and also the first leaping voltage is 2.5V.
By this first leaping voltage, add the first stepping, just can obtain the second leaping voltage, in this case 2.6V.At this, suppose that the second stepping is 3mV, the second step heading chip of then take provides the voltage reducing gradually, and (voltage providing to chip is 2.6V, 2.597V, 2.594V, 2.591V, 2.588V, 2.585V ... the rest may be inferred, until under an input voltage, the output voltage of chip is 0V, there is saltus step), just can obtain the second leaping voltage of chip, be for example 2.567V.Visible, this second leaping voltage (being that chip scanning voltage tester is tested the voltage obtaining) is higher than the degree of accuracy of the first leaping voltage; Meanwhile, because this second leaping voltage is to obtain in second starting potential that is 2.6V in starting potential, for the first starting potential 5V, the required test duration also can be shorter.
Further, when the chip of testing is during to multi-disc simultaneously, of the magnitude of voltage maximum that described the first leaping voltage is leaping voltage in this multi-plate chip.For example, the same time, three chips are carried out to chip scanning voltage tester, during test, the first starting potential is 5V, and the first stepping is 100mV, and the leaping voltage that obtains these three chips is respectively 2.4V, 2.4V and 2.5V, and the first leaping voltage is 2.5V.
By this first leaping voltage, add the first stepping, just can obtain the second leaping voltage, in this case 2.6V.At this, suppose that the second stepping is 3mV, then with second step heading chip, provide the voltage reducing gradually, just can obtain the second leaping voltage of chip.Suppose that, in this process, the leaping voltage of three chips is respectively 2.447V, 2.453V and 2.564V, now the second leaping voltage is three, is respectively 2.447V, 2.453V and 2.564V.Can find equally, this second leaping voltage (being that chip scanning voltage tester is tested the voltage obtaining) is higher than the degree of accuracy of the first leaping voltage; Meanwhile, because this second leaping voltage is to obtain in second starting potential that is 2.6V in starting potential, for the first starting potential 5V, the required test duration also can be shorter.
As fully visible, in the chip scanning voltage test method providing in the embodiment of the present invention, by a larger stepping (i.e. the first stepping), carry out in the larger context chip scanning voltage tester, obtain the leaping voltage that a degree of accuracy is lower (i.e. the first leaping voltage); By a less stepping (i.e. the second stepping), in less scope, carry out chip scanning voltage tester again, obtain the leaping voltage that a degree of accuracy is higher (i.e. the second saltus step transformation), complete thus whole chip scanning test process.Accurate by the resulting test result of this scanning voltage method of testing, and the needed test duration is also shorter.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection domain of claims.
Claims (7)
1. a chip scanning voltage test method, is characterized in that, comprising:
From the first starting potential, with first step heading chip, provide the voltage reducing gradually, obtain the first leaping voltage of chip;
From the second starting potential, with second step heading chip, provide the voltage reducing gradually, obtain the second leaping voltage of chip;
Wherein, the second starting potential is that the first leaping voltage adds the first stepping, and the first stepping is greater than the second stepping, and the second leaping voltage is that chip scanning voltage tester is tested the voltage obtaining.
2. chip scanning voltage test method as claimed in claim 1, is characterized in that, described the first stepping is 5 times～1000 times of the second stepping.
3. chip scanning voltage test method as claimed in claim 1, is characterized in that, described the first stepping is 5mV～1V.
4. chip scanning voltage test method as claimed in claim 3, is characterized in that, described the second stepping is 1mV～10mV.
5. chip scanning voltage test method as claimed in claim 1, is characterized in that, described the first starting potential is 5V～10V.
6. the chip scanning voltage test method as described in any one in claim 1～5, is characterized in that, when the chip of simultaneously testing is a slice, described the first leaping voltage is the leaping voltage of this slice chip.
7. the chip scanning voltage test method as described in any one in claim 1～5, is characterized in that, when the chip of simultaneously testing is multi-disc, and of the magnitude of voltage maximum that described the first leaping voltage is leaping voltage in this multi-plate chip.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110383089A (en) * | 2018-02-12 | 2019-10-25 | 深圳市汇顶科技股份有限公司 | Grid capacitive plate and chip detecting method |
| CN110927560A (en) * | 2019-12-16 | 2020-03-27 | 无锡矽鹏半导体检测有限公司 | Integrated circuit testing method |
| CN111610433A (en) * | 2020-06-17 | 2020-09-01 | 江西联智集成电路有限公司 | Chip power-on and power-off reset test method and device |
| CN114062905A (en) * | 2022-01-17 | 2022-02-18 | 绍兴中芯集成电路制造股份有限公司 | Chip abrupt voltage testing method and device and storage medium |
| CN116008770A (en) * | 2023-03-28 | 2023-04-25 | 合肥新晶集成电路有限公司 | Scan test method, scan test device, and computer-readable storage medium |
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| CN114062905A (en) * | 2022-01-17 | 2022-02-18 | 绍兴中芯集成电路制造股份有限公司 | Chip abrupt voltage testing method and device and storage medium |
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| CN116008770A (en) * | 2023-03-28 | 2023-04-25 | 合肥新晶集成电路有限公司 | Scan test method, scan test device, and computer-readable storage medium |
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Application publication date: 20140212 |