CN110383089B - Matrix capacitor plate and chip testing method - Google Patents
Matrix capacitor plate and chip testing method Download PDFInfo
- Publication number
- CN110383089B CN110383089B CN201880000177.8A CN201880000177A CN110383089B CN 110383089 B CN110383089 B CN 110383089B CN 201880000177 A CN201880000177 A CN 201880000177A CN 110383089 B CN110383089 B CN 110383089B
- Authority
- CN
- China
- Prior art keywords
- channel
- current test
- capacitance
- test channel
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
A matrix capacitor plate and a chip testing method are provided, the matrix capacitor plate comprises: the first signal lines and the second signal lines are arranged on the substrate, and the capacitor matrix is formed by capacitors arranged at the intersection of the first signal lines and the second signal lines and comprises at least two capacitors; the chip testing method comprises the steps that at least two capacitances with capacitance values are arranged in a capacitance matrix of a matrix capacitance plate, so that the functions of a normal state (namely an untouched state) and a touch state can be simulated, and the testing of different performance conditions of a chip can be realized based on the functions of the matrix capacitance plate.
Description
Technical Field
The application relates to the technical field of testing, in particular to a matrix capacitor plate and a chip testing method.
Background
With the wide application of touch screens in the fields of smart phones, automobiles, household appliances and the like, the demand of touch chips is also increased explosively. For the touch chip, the functionality and stability are very important, so in a mass production test, the performance of the touch chip needs to be tested. Currently, in a touch chip test, an Automatic built-in self test (Abist) loop is used to test whether each channel of the touch chip is normal.
The inventor finds that the prior art has at least the following problems: in the prior art, when testing whether each path of a touch chip is normal through an Abist loop, some paths cannot be covered by the Abist loop, and the deviation between the test state and the actual state of the touch chip is large, so that the test coverage rate is insufficient.
Disclosure of Invention
An object of some embodiments of the present application is to provide a matrix capacitor plate and a chip testing method, in which at least two capacitors with different capacitance values are set in a capacitor matrix of the matrix capacitor plate, so as to realize a function of simulating a normal state (i.e., an untouched state) and a touched state, and to realize testing of different performance conditions of a chip based on the function of the matrix capacitor plate.
The embodiment of the application provides a matrix capacitor plate, includes: the first signal lines and the second signal lines are arranged on the substrate, and the capacitance matrix is formed by the capacitance at the intersection of each first signal line and each second signal line; the capacitance matrix comprises at least two capacitance values of capacitance.
The embodiment of the application also provides a chip testing method, which comprises the steps of providing the matrix capacitor plate and connecting the matrix capacitor plate to a chip to be tested; one signal line of the first signal line and the second signal line is used as a transmitting channel, and the other signal line is used as a receiving channel; sequentially applying a scanning voltage to each transmitting channel and receiving an output voltage from each receiving channel; and analyzing the performance condition of the chip according to the output voltage received by each receiving channel.
The embodiment of the application also provides a chip testing method, which comprises the steps of providing the matrix capacitor plate and connecting the matrix capacitor plate to a chip to be tested; taking the first signal line or the second signal line as a current test channel; sequentially applying scanning voltage to each current test channel, and receiving output voltage from each current test channel; and analyzing the performance condition of the chip according to the output voltage received by each current test channel.
Compared with the prior art, the embodiment of the application has the advantages that at least two capacitances with capacitance values are arranged in the capacitance matrix of the matrix capacitance plate, so that the functions of simulating a normal state (namely an untouched state) and a touch state can be realized, and the test on different performance conditions of a chip can be realized based on the functions of the matrix capacitance plate; the chip test is designed by utilizing the function of the matrix capacitor plate, and the working environment of the touch chip can be highly simulated, so that the test coverage rate is improved, and the test speed is also improved.
In addition, in the matrix capacitor plate, the capacitance values of the capacitors sequentially arranged on each first signal line form a capacitance value distribution pattern corresponding to the first signal line; the capacitance values of the capacitors sequentially arranged on each second signal line form a capacitance value distribution pattern corresponding to the second signal line; the capacitance value distribution pattern corresponding to each first signal line meets a first preset condition; or the capacitance value distribution pattern corresponding to each second signal line meets a second preset condition; or the capacitance value distribution pattern corresponding to each first signal line meets a first preset condition and the capacitance value distribution pattern corresponding to each second signal line meets a second preset condition. The present embodiment provides different designs of the capacitor matrix.
In addition, in the matrix capacitor plate, the first preset condition is: the capacitance value distribution patterns corresponding to the first signal lines are different; the second preset condition is as follows: the capacitance value distribution patterns corresponding to the second signal lines are different. The embodiment provides a specific content of the preset condition, that is, a specific design manner of the capacitor matrix.
In addition, each capacitor on the diagonal line and on one side of the diagonal line of the capacitor matrix has a first capacitance value, and each capacitor on the other side of the diagonal line has a second capacitance value. The present embodiment provides another specific design of the capacitor matrix.
In addition, the number of the first signal lines is equal to the number of the second signal lines.
In addition, in the matrix capacitor plate, the first preset condition is: the volume value distribution patterns corresponding to m first signal lines which are continuously arranged are all different, wherein m is an integer which is more than or equal to 2, and m is less than the total number of the first signal lines; the second preset condition is as follows: the volume value distribution patterns corresponding to the n second signal lines which are continuously arranged are all different; wherein n is an integer greater than or equal to 2 and n is less than the total number of the second signal lines. The present embodiment provides another specific content of the preset condition, that is, provides another specific design manner of the capacitor matrix.
In addition, in the matrix capacitor plate, the capacitors with different capacitance values. The embodiment provides a specific selection mode of different capacitance values, so that the functions of a normal state (namely, an untouched state) and a touched state can be simulated more accurately.
In addition, in the matrix capacitor plate, the capacitor matrix comprises two capacitance values of the capacitor, and the two capacitance values are respectively 1.5 picofarads and 1.0 picofarads.
In addition, in the chip test method, each transmitting channel corresponds to a set of output voltages and the set of output voltages are output voltages received from the receiving channels when the transmitting channels are applied with the scan voltage; taking the transmitting channel as a current testing channel; analyzing the performance condition of the chip according to the output voltage received by each receiving channel, wherein the performance condition comprises the following steps: for each current test channel, taking the voltage value of each output voltage in a group of output voltages corresponding to the current test channel as a voltage distribution pattern corresponding to the current test channel; judging whether the voltage distribution pattern corresponding to the current test channel is matched with the capacity value distribution pattern corresponding to the current test channel; the capacitance values of the capacitors sequentially arranged on the current test channels form a capacitance value distribution pattern corresponding to the current test channels; and if the judgment result of each current test channel is matched, judging that the touch detection function of the chip is normal. The embodiment provides a specific implementation mode for detecting whether the touch detection function of the chip is normal.
In addition, in the chip testing method, the matrix capacitor plate is the matrix capacitor plate, and the capacitance value distribution pattern corresponding to each first signal line meets a first preset condition and the capacitance value distribution pattern corresponding to each second signal line meets a second preset condition; each transmitting channel corresponds to a group of output voltages, and the group of output voltages are output voltages received from all receiving channels when the transmitting channels are applied with scanning voltages; taking the transmitting channel as a current testing channel; analyzing the performance condition of the chip according to the output voltage received by each receiving channel, wherein the performance condition comprises the following steps: for each current test channel, identifying a theoretical test channel according to a group of output voltages corresponding to the current test channel; judging whether the theoretical test channel is consistent with the current test channel; and if the two pins are not consistent, judging that routing abnormality exists in the pins of the chip corresponding to the current test channel. The embodiment provides a specific implementation mode for detecting whether the chip has routing abnormality.
In addition, the theoretical test channel is identified according to a group of output voltages corresponding to the current test channel, and the method comprises the following steps: for each current test channel, taking the voltage value of each output voltage in a group of output voltages corresponding to the current test channel as a voltage distribution pattern corresponding to the current test channel; and obtaining the theoretical test channel corresponding to the voltage distribution pattern corresponding to the current test channel according to the preset corresponding relation between the voltage distribution pattern and the theoretical test channel. The embodiment provides a specific implementation manner for obtaining a theoretical test channel corresponding to a voltage distribution pattern corresponding to a current test channel.
In addition, in the chip testing method, the performance condition of the chip is analyzed according to the output voltage received by each current testing channel, and the method comprises the following steps: for each current test channel, judging whether the output voltage received from the current test channel is matched with the sum of the capacitance values of all capacitors on the current test channel; and if the judgment results corresponding to each current test channel are matched, judging that the touch detection function of the chip is normal. The embodiment provides a specific implementation mode for detecting whether the touch detection function of the chip is normal.
In addition, in the chip testing method, the matrix capacitor plate is the matrix capacitor plate, and the capacitance value distribution pattern corresponding to each first signal line meets a first preset condition and the capacitance value distribution pattern corresponding to each second signal line meets a second preset condition; analyzing the performance condition of the chip according to the output voltage received by each current test channel, wherein the performance condition comprises the following steps: for each current test channel, judging whether the output voltage received from the current test channel is matched with the sum of the capacitance values of all capacitors on the current test channel; and if not, judging that routing abnormality exists inside the pin of the chip corresponding to the current test channel. The embodiment provides a specific implementation mode for detecting whether the chip has routing abnormality.
In addition, in the chip testing method, whether the output voltage received from the current testing channel is matched with the sum of the capacitance values of the capacitors on the current testing channel includes: inquiring a preset corresponding relation between the output voltage and the sum of the capacitance values, and acquiring the sum of the capacitance values corresponding to the output voltage; inquiring a preset corresponding relation between the test channel and the sum of the capacity values, and acquiring the sum of the capacity values corresponding to the current test channel; judging whether the sum of the capacitance values corresponding to the output voltage is consistent with the sum of the capacitance values corresponding to the current test channel; and if the voltage values are consistent, the output voltage received from the current testing channel is matched with the sum of the capacitance values of all capacitors on the current testing channel. The embodiment provides a specific implementation manner for judging whether the output voltage received by the current test channel is matched with the sum of the capacitance values of the capacitors on the current test channel.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a matrix capacitor plate according to a first embodiment of the present application, wherein the matrix capacitor plate includes capacitors of two capacitance values;
FIG. 2 is a schematic diagram of a matrix capacitor plate according to a first embodiment of the present application, wherein the matrix capacitor plate includes three capacitance values;
fig. 3 is a schematic diagram of a matrix capacitor plate according to a second embodiment of the present application, in which capacitance distribution patterns corresponding to the first signal lines are different;
FIG. 4 is a schematic diagram of a matrix capacitor plate according to a second embodiment of the present application, in which the capacitance distribution patterns of the second signal lines are different;
fig. 5A is a schematic diagram of a matrix capacitor plate in which capacitance distribution patterns corresponding to each first signal line and capacitance distribution patterns corresponding to each second signal line both satisfy a preset condition according to a second embodiment of the present disclosure, where the number of the first signal lines is greater than the number of the second signal lines;
fig. 5B is a schematic diagram of a matrix capacitor plate in which a capacitance distribution pattern corresponding to each first signal line and a capacitance distribution pattern corresponding to each second signal line both satisfy a preset condition according to a second embodiment of the present disclosure, where the number of the second signal lines is greater than the number of the first signal lines;
fig. 6 is a schematic diagram of a matrix capacitor plate in which capacitors on diagonal lines and on one side of the diagonal lines of a capacitor matrix are all of a first capacitance value and capacitors on the other side of the diagonal lines are all of a second capacitance value according to a second embodiment of the present application, where the number of first signal lines is greater than the number of second signal lines;
FIG. 7 is a diagram of a capacitor plate of a matrix having capacitors on diagonal lines and on one side of the diagonal lines with a first capacitance value and capacitors on the other side of the diagonal lines with a second capacitance value according to a second embodiment of the present disclosure, wherein the number of first signal lines is equal to the number of second signal lines;
fig. 8A is a schematic diagram of a matrix capacitor plate according to a third embodiment of the present application, in which capacitance distribution patterns corresponding to 2 first signal lines arranged in series are all different;
fig. 8B is a schematic diagram of a matrix capacitor plate according to a third embodiment of the present disclosure, in which capacitance value distribution patterns corresponding to 2 continuously arranged first signal lines are all different, and capacitance value distribution patterns corresponding to 2 continuously arranged second signal lines are all different;
FIG. 9 is a detailed flowchart of a chip testing method according to a fourth embodiment of the present application;
FIG. 10 is a circuit diagram of a mutual capacitance detection model according to a fourth embodiment of the present application;
fig. 11 is a detailed flowchart of a chip testing method according to a fourth embodiment of the present application, wherein the method is used for detecting a touch detection function of a touch chip;
FIG. 12 is a detailed flowchart of a chip testing method according to a fifth embodiment of the present application;
FIG. 13 is a flowchart showing a chip test method according to a sixth embodiment of the present application;
FIG. 14 is a circuit diagram of a self-contained test model in a sixth embodiment according to the present application;
fig. 15 is a detailed flowchart of a chip testing method according to a sixth embodiment of the present application, wherein the method is used for detecting a touch detection function of a touch chip;
FIG. 16 is a detailed flowchart of a chip testing method according to a seventh embodiment of the present application;
FIG. 17 is a flowchart illustrating a method for determining whether the output voltage received from the current test channel matches the sum of the capacitance values of the capacitors on the current test channel according to a seventh embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
In order to make the objects, technical solutions and advantages of the present application more apparent, some embodiments of the present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
A first embodiment of the present application relates to a matrix capacitor plate, the matrix capacitor plate comprising: the capacitance matrix comprises a plurality of first signal lines, a plurality of second signal lines and a capacitance matrix formed by capacitances arranged at the intersection of the first signal lines and the second signal lines; in this embodiment, the first signal lines are parallel to each other, the second signal lines are parallel to each other, and the first signal lines and the second signal lines are perpendicular to each other and intersect each other. It should be noted that, when the matrix capacitor plate is connected to the chip, one of the first signal line and the second signal line may be used as a transmitting channel of the matrix capacitor plate, and the other one may be used as a receiving channel; in this embodiment, a description will be given by taking the first signal line as a transmission channel (TX channel) and the second signal line as a reception channel (RX channel).
In this embodiment, the capacitance matrix includes at least two capacitances. In one example, referring to fig. 1, the capacitance matrix includes two capacitances, and the two capacitances are 1.5 picofarads and 1.0 picofarads, the capacitance matrix includes 5 first signal lines (TX0 to TX4) and 5 second signal lines (RX0 to RX4), the capacitance of the capacitance at the intersection of RX0, RX1 and each first signal line (TX0 to TX4) is 1.0 picofarad, and the capacitance of the capacitance at the intersection of RX2 to RX4 and each first signal line (TX0 to TX4) is 1.5 picofarads.
In another example, as shown in fig. 2, the capacitance matrix includes three capacitances (three are taken as an example, but not limited thereto), and the three capacitances are 2.0 picofarads, 1.5 picofarads, and 1.0 picofarads (taken as an example, but not limited thereto), the capacitance matrix includes 5 first signal lines (TX0 to TX4) and 5 second signal lines (RX0 to RX4), the capacitances at the intersections of TX0, TX1 and the second signal lines (RX0 to RX4) are 1.0 picofarads, the capacitances at the intersections of TX2, 3 and the second signal lines (RX0 to RX4) are 1.5 picofarads, and the capacitances at the intersections of TX4 and the second signal lines (RX0 to RX4) are 2.0 picofarads.
It should be noted that, in fig. 1 and fig. 2, the capacitor matrix includes 5 first signal lines and 5 second signal lines as an example, but the number of the first signal lines and the second signal lines is not limited in this embodiment.
In a conventional capacitive touch screen, the capacitance value of the capacitance in a touched area is reduced in a touched state. The matrix capacitor plate in the embodiment can simulate a capacitive touch screen, and a capacitor matrix of the matrix capacitor plate comprises at least two capacitors with capacitance values, so that the capacitor with the smaller capacitance value can simulate a touched area, namely a function of simulating a touch state; the capacitance with larger capacitance value can simulate the function of an untouched area, namely a simulated normal state (namely a touch state).
Preferably, the capacitances with different capacitance values satisfy the following conditions: the capacitance value difference of any two capacitance values is greater than or equal to one third of the larger capacitance value, so that the functions of a normal state (namely, an untouched state) and a touched state can be simulated more accurately.
Compared with the prior art, the embodiment has the advantages that the capacitance matrix of the matrix capacitance plate is provided with at least two capacitance values, so that the function of simulating a normal state (namely, an untouched state) and a touch state can be realized, and the test of different performance conditions of a chip can be realized based on the function of the matrix capacitance plate; the chip test is designed by utilizing the function of the matrix capacitor plate, and the working environment of the touch chip can be highly simulated, so that the test coverage rate is improved, and the test speed is also improved.
The second embodiment of the present application relates to a matrix capacitor plate, which is an improvement on the first embodiment, and the main improvement is that: a specific design scheme of the matrix capacitor plate is provided, and the first preset condition is as follows: the capacitance value distribution patterns corresponding to the first signal lines are different; the second preset condition is as follows: the capacitance value distribution patterns corresponding to the second signal lines are different.
In this embodiment, the capacitance values of the capacitors sequentially arranged on each first signal line form a capacitance value distribution pattern corresponding to the first signal line; the capacitance values of the capacitors sequentially arranged on each second signal line form a capacitance value distribution pattern corresponding to the second signal line.
In this embodiment, three design schemes of a matrix capacitor plate are provided, specifically as follows:
first, the capacitance distribution pattern corresponding to each first signal line satisfies a first preset condition.
Secondly, the capacitance value distribution pattern corresponding to each second signal line meets a second preset condition.
And thirdly, the capacity value distribution pattern corresponding to each first signal line meets the first preset condition and the capacity value distribution pattern corresponding to each second signal line meets the second preset condition.
Wherein the first preset condition is as follows: the capacitance value distribution patterns corresponding to the first signal lines are different; the second preset condition is as follows: the capacitance value distribution patterns corresponding to the second signal lines are different, and based on the three design schemes, the following matrix capacitor plate can be obtained.
First, capacitance distribution patterns corresponding to the first signal lines meet a first preset condition, that is, the capacitance distribution patterns corresponding to the first signal lines are different, please refer to fig. 3, the capacitance matrix includes 5 first signal lines (TX0 to TX4) and 7 second signal lines (RX0 to RX6), and the capacitance distribution patterns corresponding to TX0 to TX4 are different. As shown in fig. 3, capacitances of capacitors sequentially arranged on the first signal line TX0 are 1.5pF, 1.0 pF; that is, the capacitance distribution pattern corresponding to the first signal line TX0 is: (3, 2, 2, 2, 2); the capacity value distribution pattern is expressed by a ratio of the capacity values, but is not limited thereto. In this way, a capacitance distribution pattern corresponding to each of the first signal lines (TX0 to TX4) is obtained, see table 1 below.
TABLE 1
Secondly, the capacitance distribution patterns corresponding to the second signal lines satisfy a second predetermined condition, that is, the capacitance distribution patterns corresponding to the second signal lines are all different, please refer to fig. 4, the capacitance matrix includes 7 first signal lines (TX0 to TX6) and 5 second signal lines (RX0 to RX4), and the capacitance distribution patterns corresponding to TX0 to TX7 are all different.
And thirdly, the capacity value distribution pattern corresponding to each first signal line meets a first preset condition and the capacity value distribution pattern corresponding to each second signal line meets a second preset condition, namely, the capacity value distribution patterns corresponding to the first signal lines are different and the capacity value distribution patterns corresponding to the second signal lines are different. Referring to fig. 5A (an example), the number of the first signal lines is smaller than the number of the second signal lines; the capacitance matrix comprises 5 first signal lines (TX 0-TX 4) and 7 second signal lines (RX 0-RX 6), wherein capacitance value distribution patterns corresponding to the first signal lines (TX 0-TX 4) are different, and capacitance value distribution patterns corresponding to the second signal lines (RX 0-RX 6) are different. Referring to fig. 5B (another example), the number of the first signal lines is greater than the number of the second signal lines; the capacitance matrix comprises 7 first signal lines (TX 0-TX 6) and 5 second signal lines (RX 0-RX 4), wherein capacitance value distribution patterns corresponding to the first signal lines (TX 0-TX 6) are different, and capacitance value distribution patterns corresponding to the second signal lines (RX 0-RX 4) are different.
In one example, the capacitor matrix includes two capacitors with two capacitance values, and the two capacitance values are respectively a first capacitance value and a second capacitance value, each capacitor on a diagonal line and on one side of the diagonal line of the capacitor matrix is a first capacitance value, each capacitor on the other side of the diagonal line is a second capacitance value, referring to fig. 6, the capacitor matrix includes 5 first signal lines (TX0 to TX4) and 7 second signal lines (RX0 to RX6), the capacitance value distribution patterns corresponding to each first signal line (TX0 to TX4) are all different, the dotted line is the diagonal line of the capacitor matrix, each capacitor on the diagonal line and on one side of the diagonal line is 1.5pF, each capacitor on the other side of the diagonal line is a second capacitance value of 1.0pF, as can be seen, the capacitance value distribution patterns corresponding to the first signal lines in the figure satisfy a first preset condition, that is, the capacitance value distribution patterns corresponding to the first signal lines are all different; correspondingly, the second signal lines are used as the transmitting channels, and the first signal lines are used as the receiving channels, so that the capacitance value distribution patterns corresponding to the second signal lines can meet a second preset condition, that is, the capacitance value distribution patterns corresponding to the second signal lines are different, and further description is omitted here.
Preferably, the number of the first signal lines is equal to the number of the second signal lines, please refer to fig. 7, the capacitance matrix includes 5 first signal lines (TX0 to TX4) and 5 second signal lines (RX0 to RX4), the first capacitance value is 1.5 picofarads, the second capacitance value is 1.0 picofarads (for example, but not limited thereto), the dotted line is a diagonal line of the capacitance matrix, each of the capacitances located on the diagonal line and one side of the diagonal line of the capacitance matrix is the first capacitance value of 1.5 picofarads, each of the capacitances located on the other side of the diagonal line of the capacitance matrix is the second capacitance value of 1.0 picofarads, the capacitance distribution patterns corresponding to the first signal lines (TX0 to TX4) are different, and the capacitance distribution patterns corresponding to the second signal lines (RX0 to RX4) are different.
In this embodiment, different design schemes of the capacitor matrix are provided, and the matrix capacitor plates satisfying the first preset condition and the second preset condition are provided, compared with the first embodiment.
The third embodiment of the present application relates to a matrix capacitor plate, which is an improvement on the basis of the first embodiment, and the main improvement is that: in this embodiment, the first preset condition is: the volume value distribution patterns corresponding to the m first signal lines which are continuously arranged are all different; the second preset condition is as follows: the capacitance value distribution patterns corresponding to the n second signal lines which are continuously arranged are all different.
In this embodiment, the first preset condition is: the volume value distribution patterns corresponding to m first signal lines which are continuously arranged are all different, wherein m is an integer which is more than or equal to 2, and m is less than the total number of the first signal lines; the second preset condition is as follows: the volume value distribution patterns corresponding to the n second signal lines which are continuously arranged are all different; wherein n is an integer greater than or equal to 2 and n is less than the total number of the second signal lines. Based on the three designs in the second embodiment, the following matrix capacitor plate can be obtained.
Firstly, in the capacitance value distribution patterns corresponding to each first signal line, the capacitance value distribution patterns corresponding to m continuously arranged first signal lines are different; referring to fig. 8A, the capacitor matrix includes 6 first signal lines (TX0 to TX5) and 4 second signal lines (RX0 to RX3), and the capacitance value distribution patterns corresponding to the 2 first signal lines arranged consecutively are all different, that is, the capacitance value distribution patterns corresponding to TX0 and TX1 are all different, the capacitance value distribution patterns corresponding to TX2 and TX3 are all different, and the capacitance value distribution patterns corresponding to TX4 and TX5 are all different; the capacitance value distribution patterns corresponding to TX0 and TX1, TX2 and TX3, and the capacitance value distribution patterns corresponding to TX4 and TX5 are the same, but not limited thereto, the capacitance value distribution patterns corresponding to TX0 and TX1, the capacitance value distribution patterns corresponding to TX2 and TX3, and the capacitance value distribution patterns corresponding to TX4 and TX5 may be different.
Secondly, in the capacitance distribution patterns corresponding to each second signal line, the capacitance distribution patterns corresponding to n first signal lines that are continuously arranged are all different, and the specific matrix capacitor plate is similar to fig. 8A, and only the second signal line is required to be used as a transmitting channel and the first signal line is required to be used as a receiving channel, which is not described herein again.
Thirdly, the capacitance value distribution patterns corresponding to m first signal lines arranged continuously are different, and the capacitance value distribution patterns corresponding to n first signal lines arranged continuously are different, please refer to fig. 8B, the capacitance matrix includes 6 first signal lines (TX0 to TX5) and 4 second signal lines (RX0 to RX3), the capacitance value distribution patterns corresponding to 2 first signal lines arranged continuously are different, the capacitance value distribution patterns corresponding to 2 second signal lines arranged continuously are different, that is, the capacitance value distribution patterns corresponding to TX0 and TX1 are different, the capacitance value distribution patterns corresponding to TX2 and TX3 are different, the capacitance value distribution patterns corresponding to TX4 and TX5 are different, the capacitance value distribution patterns corresponding to RX0 and RX1 are different, and the capacitance value distribution patterns corresponding to RX2 and RX3 are different.
It should be noted that, in the embodiment, the capacitor matrix includes two capacitance values of the capacitor, and the two capacitance values of the capacitor are 1.5 picofarads and 1.0 picofarads respectively, but the embodiment does not limit the types of the capacitance values of the capacitor included in the capacitor matrix and the magnitude of the capacitance values.
It should be noted that, the present embodiment only schematically describes the number of the first signal lines and the second signal lines included in the capacitor matrix, but the present embodiment does not limit this, and may be specifically set according to actual needs.
In this embodiment, compared to the first embodiment, the matrix capacitor plate satisfying the first and second predetermined conditions is provided.
The fourth embodiment of the application relates to a chip testing method, which is applied to testing a touch chip; as shown in fig. 9: the chip testing method comprises the following steps: step 101: providing a matrix capacitor plate as in any one of the first to third embodiments, and connecting the matrix capacitor plate to a chip to be tested; one signal line of the first signal line and the second signal line is used as a transmitting channel, and the other signal line is used as a receiving channel; step 102: sequentially applying a scanning voltage to each transmitting channel and receiving an output voltage from each receiving channel; step 103: and analyzing the performance condition of the chip according to the output voltage received by each receiving channel.
Compared with the prior art, the embodiment has the advantages that the capacitance matrix of the matrix capacitance plate is provided with at least two capacitance values, so that the function of simulating a normal state (namely, an untouched state) and a touch state can be realized, and the test of different performance conditions of a chip can be realized based on the function of the matrix capacitance plate; the chip test is designed by utilizing the function of the matrix capacitor plate, and the working environment of the touch chip can be highly simulated, so that the test coverage rate is improved, and the test speed is also improved.
The following describes implementation details of the chip testing method of the present embodiment in detail, and the following description is only provided for facilitating understanding of the implementation details and is not necessary for implementing the present embodiment. The embodiment is specifically used for detecting the touch detection function of the touch chip.
The chip testing method in this embodiment is based on a mutual capacitance model, please refer to fig. 10, which is a circuit diagram of a mutual capacitance detection model, Cx represents a capacitance value of a capacitor on a matrix capacitor plate, VTXRepresenting the input signal, W representing the frequency of the input signal, VRXRepresenting the output signal, R represents the resistance of the circuit, the following can be shown:
VRX＝R*W*Cx*VTXformula (1)
Wherein the input signal is constant, i.e. W, VTXThe resistance R of the circuit is unchanged; from equation (1), the output signal VRXProportional to the capacitance Cx on the matrix capacitor plate.
Since the chip testing method of this embodiment is implemented based on the principle of mutual capacitance model, the output signal V isRXThe capacitance Cx is in direct proportion to the capacitance Cx on the matrix capacitance plate and can be used as a principle basis for subsequent chip test analysis.
Please refer to fig. 9 and fig. 11 for a specific flow of the chip testing method of the present embodiment.
In step 101, a matrix capacitor plate as in the first embodiment or the second embodiment is provided and connected to a chip to be tested. The matrix capacitor plate is provided in any one of the first to third embodiments.
Specifically, each first signal line and each second signal line are respectively connected to each pin of the touch chip, and each signal line is connected to one pin. One signal line of a first signal line and a second signal line in a capacitance matrix of the matrix capacitance plate is used as a transmitting channel, and the other signal line is used as a receiving channel; that is, the pins of the touch chip connected to the first signal lines are pins for transmitting scanning signals, and the pins of the touch chip connected to the second signal lines are pins for receiving output signals.
In step 102, a scan voltage is sequentially applied to each transmit channel and an output voltage is received from each receive channel.
Specifically, the touch chip sequentially applies a scan voltage to each transmission channel through a pin connected to the transmission channel, and receives an output voltage through a pin connected to the reception channel.
and a substep 1031, regarding each emission channel, using the voltage value of each output voltage in a group of output voltages corresponding to the emission channel as the voltage distribution pattern corresponding to the emission channel.
Specifically, for one transmission channel, a set of voltage values of the output voltages may be obtained, and the voltage values of the set of output voltages are taken as the voltage distribution pattern corresponding to the transmission, and the voltage values of 5 sets of output voltages corresponding to 5 transmission channels (TX0 to TX4) are taken as 5 voltage distribution patterns corresponding to 5 transmission channels, taking the matrix capacitor plate of fig. 1 as an example.
And a sub-step 1032 of determining whether the voltage distribution pattern corresponding to the transmitting channel matches the capacitance distribution pattern corresponding to the transmitting channel.
Specifically, taking the transmission channel TX0 as an example, the touch chip applies a scanning voltage to the transmission channel TX0, and uses a voltage value of each output voltage in a group of output voltages corresponding to the transmission channel TX0 as a voltage distribution pattern corresponding to the transmission channel TX0, where if the received voltage values of each output voltage are: (4V, 6V), the voltage distribution pattern corresponding to the transmission channel TX0 is (2, 2, 3, 3, 3); as can be seen from fig. 1, the capacitance distribution pattern corresponding to the transmission channel TX0 is (2, 2, 3, 3, 3); by comparison, the voltage distribution pattern corresponding to the transmission channel TX0 matches the capacitance value distribution pattern corresponding to the transmission channel TX 0; if the voltage values of the received output voltages are respectively: (4V, 6V), the voltage distribution pattern corresponding to the transmit channel TX0 is (2, 2, 2, 3, 3), and it can be known by comparison that the voltage distribution pattern corresponding to the transmit channel TX0 does not match the capacitance distribution pattern corresponding to the transmit channel TX 0. Based on a similar principle, whether the voltage distribution pattern corresponding to each transmitting channel is matched with the capacitance value distribution pattern can be judged. For the convenience of observation, the voltage distribution pattern and the capacitance distribution pattern corresponding to the emission channel are expressed in a proportional form.
And a substep 1033, if the judgment result of each emission channel is matched, judging that the touch detection function of the chip is normal.
Specifically, when the voltage distribution pattern corresponding to each transmitting channel is matched with the capacitance value distribution pattern corresponding to each transmitting channel, it is indicated that the touch detection function of the touch chip is normal; when the voltage distribution pattern corresponding to one or more transmitting channels is not matched with the corresponding capacitance value distribution pattern, the touch detection function of the touch chip is abnormal.
The fifth embodiment of the present application relates to a chip testing method, which is substantially the same as the fourth embodiment, and mainly differs therefrom in that: in a third embodiment, a touch detection function of a touch chip is detected; in this embodiment, whether a routing abnormality exists inside a pin of the touch chip is detected.
In this embodiment, a specific flow of the chip testing method is shown in fig. 12. The matrix capacitor plate is the matrix capacitor plate in the second embodiment or the matrix capacitor plate in the third embodiment, and the capacitance distribution pattern corresponding to each first signal line meets the first preset condition and the capacitance distribution pattern corresponding to each second signal line meets the second preset condition.
The main difference between step 201 and step 202 is that the transmitting channel is used as the current testing channel, and step 203 in this embodiment analyzes the performance status of the chip according to the output voltage received by each receiving channel, and specifically includes:
Specifically, for each current test channel, the voltage value of each output voltage in a group of output voltages corresponding to the current test channel is used as the voltage distribution pattern corresponding to the current test channel. And according to the preset corresponding relation between the voltage distribution pattern and the theoretical test channel, the theoretical test channel corresponding to the voltage distribution pattern corresponding to the current test channel can be obtained.
The concrete mode is as follows: comparing each output voltage in a group of output voltages corresponding to the current test channel, identifying a voltage jump point in the group of output voltages, and determining a capacitance value jump position of a capacitor represented by the voltage jump point; and then, according to the preset corresponding relation among the capacity value jump position, the capacity value distribution pattern and the theoretical test channel, the theoretical test channel corresponding to the capacity value jump position can be obtained. Taking the matrix capacitor plate in fig. 7 as an example, as shown in table 2 below, a preset correspondence table of capacitance jump positions, capacitance distribution patterns, and theoretical test channels is shown.
TABLE 2
It should be noted that, if there are a plurality of voltage jump points in a group of output voltages corresponding to a current test channel, capacitance jump positions corresponding to the plurality of voltage jump points need to be identified, so that a corresponding capacitance distribution pattern can be obtained according to the plurality of capacitance jump positions, and then theoretical test channels corresponding to the capacitance distribution pattern can be obtained, that is, theoretical test channels corresponding to the current test channel are obtained, taking the matrix capacitor plate of fig. 3 as an example, if there are 2 capacitance jump positions, and a fourth capacitor and a fifth capacitor are respectively used, capacitance distribution patterns corresponding to the 2 two capacitance jump positions are (3, 3, 3, 3, 2, 3, 3, 3), and the theoretical test channel corresponding to the capacitance distribution pattern is TX3, that is, the theoretical test channel corresponding to the current test channel is TX 3.
And substep 2032, determining whether the theoretical test channel is consistent with the current test channel.
Specifically, when the theoretical test channel and the current test channel are the same transmission channel, that is, the two channels are the same, it indicates that there is no routing abnormality inside the pin of the touch chip corresponding to the current test channel.
Specifically, when the theoretical test channel and the current test channel are different emission channels, that is, they are not the same, it indicates that routing abnormality exists inside the pin of the touch chip corresponding to the current test channel, that is, routing abnormality exists between the external pin of the chip and the Pad inside the chip.
Compared with the fourth embodiment, the present embodiment provides a specific implementation manner for detecting whether a routing abnormality exists inside a pin of a touch chip.
The sixth embodiment of the present application relates to a chip testing method, which is applied to testing a touch chip; as shown in fig. 13, the chip testing method includes: step 301, providing a matrix capacitor plate according to any one of the first to third embodiments, and connecting the matrix capacitor plate to a chip to be tested; step 302, sequentially applying a scanning voltage to each current test channel, and receiving an output voltage from each current test channel; step 303, analyzing the performance status of the chip according to the output voltage received by each current test channel.
Compared with the prior art, the embodiment has the advantages that the capacitance matrix of the matrix capacitance plate is provided with at least two capacitance values, so that the function of simulating a normal state (namely, an untouched state) and a touch state can be realized, and the test of different performance conditions of a chip can be realized based on the function of the matrix capacitance plate; the chip test is designed by utilizing the function of the matrix capacitor plate, and the working environment of the touch chip can be highly simulated, so that the test coverage rate is improved, and the test speed is also improved.
The following describes implementation details of the chip testing method of the present embodiment in detail, and the following description is only provided for facilitating understanding of the implementation details and is not necessary for implementing the present embodiment. The embodiment is specifically used for detecting the touch detection function of the touch chip.
The chip testing method in this embodiment is based on the self-capacitance detection model, please refer to fig. 14, which is a circuit diagram of the self-capacitance detection model, CTxRepresenting the sum of the capacitances of one transmit channel on the matrix capacitor plate, VTXRepresenting the input signal, W representing the frequency of the input signal, VRXRepresenting the output signal, R represents the resistance of the circuit, the following can be shown:
VRX＝VTX/(1+R*W*CTx) Formula (2)
Wherein the input signal is constant, i.e. W, VTXThe resistance R of the circuit is unchanged; from equation (2), the output signal VRXAnd a capacitor C on the matrix capacitor plateTxIn a proportional relationship.
Since the chip testing method of this embodiment is implemented based on the principle of the self-capacitance model, the output signal V is outputRXAnd the sum C of the capacitance values of the capacitances of one transmitting channel on the matrix capacitor plateTxThe proportional relation is used as a principle basis for subsequent chip test analysis.
Please refer to fig. 13 and fig. 15 for a specific flow of the chip testing method of the present embodiment.
In step 301, a matrix capacitor plate as in the first to third embodiments is provided and connected to a chip to be tested. The matrix capacitor plate is provided in any one of the first to third embodiments.
Specifically, a first signal line or a second signal line in a capacitance matrix of the matrix capacitor plate is used as a current test channel, the current test channel is respectively connected to pins of the touch chip, and each signal line is connected to one pin.
In step 302, a scan voltage is sequentially applied to each current test channel and an output voltage is received from each current test channel.
Specifically, the touch chip sequentially applies a scan voltage to each current test channel through a pin connected to each current test channel, and receives an output voltage from each current test channel through a pin connected to each current test channel.
In step 303, the performance status of the chip is analyzed according to the output voltage received by each receiving channel, please refer to fig. 15, which specifically includes the following sub-steps:
Specifically, a preset corresponding relation between a voltage value of the output voltage and the sum of the capacitance values is prestored in the touch chip; for each current test channel, obtaining a voltage value of an output voltage, and judging whether the voltage value of the output voltage received from the current test channel is matched with the sum of the capacitance values of all capacitors on the current test channel according to a preset corresponding relation between the voltage value of the output voltage and the sum of the capacitance values, wherein the specific judgment mode is as follows: at an input voltage VTXThe sum C of the capacitance values of the capacitors on the current test channelTXCorresponding output voltage of VRXIf the voltage value of the output voltage received from the current test channel is not equal to VRXIf so, the voltage value of the output voltage received from the current test channel is not matched with the sum of the capacitance values of all capacitors on the current test channel; otherwise, the two are matched.
And a substep 3032, if the judgment results corresponding to each current test channel are matched, judging that the touch detection function of the chip is normal.
Specifically, when the output voltage received by each test channel is matched with the sum of the capacitance values of the capacitors on each test channel, the touch detection function of the touch chip is judged to be normal; and when the output voltage received by one or more test channels is not matched with the sum of the capacitance values of the capacitors on the corresponding test channels, judging that the touch detection function of the touch chip is abnormal.
The seventh embodiment of the present application relates to a chip testing method, which is substantially the same as the sixth embodiment, and mainly differs therefrom in that: in a third embodiment, a touch detection function of a touch chip is detected; in this embodiment, whether a routing abnormality exists inside a pin of the touch chip is detected.
In this embodiment, a specific flow of the chip testing method is shown in fig. 16. The matrix capacitor plate is the matrix capacitor plate in the second embodiment or the matrix capacitor plate in the third embodiment, and the capacitance distribution pattern corresponding to each first signal line meets the first preset condition and the capacitance distribution pattern corresponding to each second signal line meets the second preset condition.
The main difference between step 401 and step 402 is that step 301 and step 302 are substantially the same, and in this embodiment, step 403 analyzes the performance status of the chip according to the output voltage received by each receiving channel, which specifically includes:
Specifically, a preset corresponding relationship between the output voltage and the sum of the capacitance values is prestored in the touch chip, the preset corresponding relationship between the output voltage and the sum of the capacitance values is inquired according to the output voltage received from the current test channel, and the sum of the capacitance values corresponding to the output voltage received from the current test channel can be obtained.
Specifically, the preset corresponding relationship between the test channel and the sum of the capacitance values is prestored in the touch chip, and the preset corresponding relationship between the test channel and the sum of the capacitance values is queried, so that the sum of the capacitance values corresponding to the current test channel can be obtained.
And a substep 40313 for determining whether the sum of the capacitance values corresponding to the output voltage is consistent with the sum of the capacitance values corresponding to the current test channel.
Specifically, whether the sum of the capacitance values corresponding to the output voltage received from the current testing channel is equal to the sum of the capacitance values corresponding to the current testing channel is judged, and when the sum of the capacitance values is equal to the sum of the capacitance values corresponding to the output voltage received from the current testing channel, the output voltage received from the current testing channel is represented to be matched with the sum of the capacitance values of each capacitor on the current testing channel; if the two are not the same, the output voltage received from the current testing channel is not matched with the sum of the capacitance values of the capacitors on the current testing channel, and the operation proceeds to step 4032.
And a substep 4032, if not, determining that routing abnormality exists inside the pin of the chip corresponding to the current test channel.
Specifically, if the output voltage received from the current test channel is not matched with the sum of the capacitance values of the capacitors on the current test channel, it is indicated that routing abnormality exists inside the pin of the chip corresponding to the current test channel, namely routing abnormality exists between the external pin of the chip and the Pad inside the chip; based on the principle, whether routing abnormity exists in each pin of the touch chip or not can be detected, namely whether routing abnormity exists between each external pin of the touch chip and each Pad in the chip or not can be detected.
Compared with the sixth embodiment, the present embodiment provides a specific implementation manner for detecting whether a routing abnormality exists inside a pin of a touch chip.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.
Claims (11)
1. A matrix capacitor plate, comprising: the signal line comprises a plurality of first signal lines, a plurality of second signal lines and a capacitance matrix formed by capacitances arranged at the intersection of the first signal lines and the second signal lines;
the capacitance matrix comprises capacitances with at least two capacitance values;
capacitance values of the capacitors sequentially arranged on each first signal line form a capacitance value distribution pattern corresponding to the first signal line; capacitance values of the capacitors sequentially arranged on each second signal line form a capacitance value distribution pattern corresponding to the second signal line;
the volume value distribution pattern corresponding to each first signal line meets a first preset condition; or the capacitance value distribution pattern corresponding to each second signal line meets a second preset condition; or the capacitance value distribution pattern corresponding to each first signal line meets the first preset condition and the capacitance value distribution pattern corresponding to each second signal line meets the second preset condition;
wherein the first preset condition is as follows: the capacitance value distribution patterns corresponding to m continuously arranged first signal lines are different, wherein m is an integer greater than or equal to 2 and is less than the total number of the first signal lines; the second preset condition is as follows: the capacitance value distribution patterns corresponding to the n second signal lines which are continuously arranged are all different; wherein n is an integer greater than or equal to 2 and n is less than the total number of the second signal lines;
alternatively, the first and second electrodes may be,
the first preset condition is as follows: the capacitance value distribution patterns corresponding to the first signal lines are different;
the second preset condition is as follows: the capacitance value distribution patterns corresponding to the second signal lines are different.
2. The matrix capacitor plate of claim 1 wherein, at the first predetermined condition: the capacitance value distribution patterns corresponding to the first signal lines are different; the second preset condition is as follows: the capacitance value distribution patterns corresponding to the second signal lines are different;
the capacitors on the diagonal line and on one side of the diagonal line of the capacitor matrix have a first capacitance value, and the capacitors on the other side of the diagonal line have a second capacitance value.
3. The matrix capacitor plate of claim 2 wherein the number of first signal lines is equal to the number of second signal lines.
4. The matrix capacitor plate of claim 1 wherein the capacitances of different capacitance values satisfy the following condition: the capacity value difference of any two capacity values is greater than or equal to one third of the larger capacity value.
5. The matrix capacitor plate of claim 1 wherein the capacitor matrix includes capacitors of two capacitance values, and wherein the two capacitance values are 1.5 picofarads and 1.0 picofarads, respectively.
6. A method for testing a chip, comprising:
providing a matrix capacitor plate according to any one of claims 1 to 5 and connecting the matrix capacitor plate to a chip to be tested; one signal line of the first signal line and the second signal line is used as a transmitting channel, and the other signal line is used as a receiving channel;
sequentially applying a scan voltage to each of the transmit channels and receiving an output voltage from each of the receive channels;
analyzing the performance condition of the chip according to the output voltage received by each receiving channel;
each transmitting channel corresponds to a set of output voltages, and the set of output voltages are output voltages received from the receiving channels when the scanning voltage is applied to the transmitting channel; taking the transmitting channel as a current testing channel;
analyzing the performance status of the chip according to the output voltage received by each receiving channel, including:
for each current test channel, taking the voltage value of each output voltage in a group of output voltages corresponding to the current test channel as a voltage distribution pattern corresponding to the current test channel;
judging whether the voltage distribution pattern corresponding to the current test channel is matched with the capacitance value distribution pattern corresponding to the current test channel; the capacitance values of the capacitors sequentially arranged on the current test channels form a capacitance value distribution pattern corresponding to the current test channels;
and if the judgment result of each current test channel is matched, judging that the touch detection function of the chip is normal.
7. The chip testing method according to claim 6, wherein the matrix capacitor plate is the matrix capacitor plate according to any one of claims 1 to 3, and the capacitance value distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the capacitance value distribution pattern corresponding to each of the second signal lines satisfies the second preset condition;
each transmitting channel corresponds to a set of output voltages, and the set of output voltages are output voltages received from the receiving channels when the scanning voltage is applied to the transmitting channel; taking the transmitting channel as a current testing channel;
analyzing the performance status of the chip according to the output voltage received by each receiving channel, wherein the analyzing comprises the following steps:
for each current test channel, identifying a theoretical test channel according to a group of output voltages corresponding to the current test channel;
judging whether the theoretical test channel is consistent with the current test channel;
and if the chip is inconsistent with the current test channel, judging that routing abnormity exists inside the pin of the chip corresponding to the current test channel.
8. The chip testing method of claim 7, wherein the identifying a theoretical test channel according to a set of output voltages corresponding to the current test channel comprises:
for each current test channel, taking the voltage value of each output voltage in a group of output voltages corresponding to the current test channel as a voltage distribution pattern corresponding to the current test channel;
and acquiring a theoretical test channel corresponding to the voltage distribution pattern corresponding to the current test channel according to the preset corresponding relation between the voltage distribution pattern and the theoretical test channel.
9. A method for testing a chip, comprising:
providing a matrix capacitor plate according to any one of claims 1 to 5 and connecting the matrix capacitor plate to a chip to be tested; taking the first signal line or the second signal line as a current test channel;
sequentially applying a scanning voltage to each current test channel, and receiving an output voltage from each current test channel;
analyzing the performance condition of the chip according to the output voltage received by each current test channel;
analyzing the performance status of the chip according to the output voltage received by each current test channel, including:
for each current test channel, judging whether the output voltage received from the current test channel is matched with the sum of the capacitance values of all capacitors on the current test channel;
and if the judgment results corresponding to the current test channels are matched, judging that the touch detection function of the chip is normal.
10. The chip testing method according to claim 9, wherein the matrix capacitor plate is the matrix capacitor plate according to any one of claims 1 to 3, and the capacitance value distribution pattern corresponding to each of the first signal lines satisfies the first preset condition and the capacitance value distribution pattern corresponding to each of the second signal lines satisfies the second preset condition;
analyzing the performance status of the chip according to the output voltage received by each current test channel, wherein the analysis comprises the following steps:
for each current test channel, judging whether the output voltage received from the current test channel is matched with the sum of the capacitance values of the capacitors on the current test channel;
and if not, judging that routing abnormality exists inside the pin of the chip corresponding to the current test channel.
11. The method for chip testing according to claim 10, wherein said determining whether the output voltage received from the current test channel matches a sum of capacitance values of the capacitors on the current test channel comprises:
inquiring a preset corresponding relation between the output voltage and the sum of the capacitance values, and acquiring the sum of the capacitance values corresponding to the output voltage;
inquiring a preset corresponding relation between a test channel and a capacity value sum, and acquiring the capacity value sum corresponding to the current test channel;
judging whether the sum of the capacitance values corresponding to the output voltage is consistent with the sum of the capacitance values corresponding to the current testing channel; and if the output voltage is consistent with the capacitance value sum of the capacitors on the current testing channel, the output voltage received from the current testing channel is characterized to be matched with the capacitance value sum of the capacitors on the current testing channel.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/076498 WO2019153343A1 (en) | 2018-02-12 | 2018-02-12 | Matrix capacitor board and chip test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110383089A CN110383089A (en) | 2019-10-25 |
| CN110383089B true CN110383089B (en) | 2021-11-05 |
Family
ID=67547813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880000177.8A Active CN110383089B (en) | 2018-02-12 | 2018-02-12 | Matrix capacitor plate and chip testing method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110383089B (en) |
| WO (1) | WO2019153343A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001311757A (en) * | 2000-04-28 | 2001-11-09 | Nec Corp | Inspecting device for array type electronic component |
| CN202600083U (en) * | 2012-04-27 | 2012-12-12 | 深圳市瑞思科科技有限公司 | Device and system for testing flexible circuit board assembly |
| CN102866317A (en) * | 2012-09-24 | 2013-01-09 | 广东欧珀移动通信有限公司 | Method and system for quick test of mobile terminal capacitive touch screen |
| CN102981059A (en) * | 2012-08-29 | 2013-03-20 | 北京集创北方科技有限公司 | Method for detecting defects of capacitive touch screen device |
| CN103576080A (en) * | 2013-11-15 | 2014-02-12 | 上海华岭集成电路技术股份有限公司 | Chip scanning voltage testing method |
| CN107238788A (en) * | 2016-03-29 | 2017-10-10 | 深圳市汇顶科技股份有限公司 | Touch chip test system and its method of testing based on grid capacitive plate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10010888B4 (en) * | 2000-03-06 | 2004-02-12 | Infineon Technologies Ag | Circuit arrangement and method for evaluating capacities in matrices |
| US6600325B2 (en) * | 2001-02-06 | 2003-07-29 | Sun Microsystems, Inc. | Method and apparatus for probing an integrated circuit through capacitive coupling |
| US8692777B2 (en) * | 2008-02-08 | 2014-04-08 | Apple Inc. | Method for rapidly testing capacitance sensing array fault conditions using a floating conductor |
| CN106093662B (en) * | 2016-07-27 | 2020-06-19 | 深圳精智达技术股份有限公司 | Touch display module and electrical performance detection device and method thereof |
-
2018
- 2018-02-12 CN CN201880000177.8A patent/CN110383089B/en active Active
- 2018-02-12 WO PCT/CN2018/076498 patent/WO2019153343A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001311757A (en) * | 2000-04-28 | 2001-11-09 | Nec Corp | Inspecting device for array type electronic component |
| CN202600083U (en) * | 2012-04-27 | 2012-12-12 | 深圳市瑞思科科技有限公司 | Device and system for testing flexible circuit board assembly |
| CN102981059A (en) * | 2012-08-29 | 2013-03-20 | 北京集创北方科技有限公司 | Method for detecting defects of capacitive touch screen device |
| CN102866317A (en) * | 2012-09-24 | 2013-01-09 | 广东欧珀移动通信有限公司 | Method and system for quick test of mobile terminal capacitive touch screen |
| CN103576080A (en) * | 2013-11-15 | 2014-02-12 | 上海华岭集成电路技术股份有限公司 | Chip scanning voltage testing method |
| CN107238788A (en) * | 2016-03-29 | 2017-10-10 | 深圳市汇顶科技股份有限公司 | Touch chip test system and its method of testing based on grid capacitive plate |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019153343A1 (en) | 2019-08-15 |
| CN110383089A (en) | 2019-10-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101050786B1 (en) | Production test of capacitive touch sensing devices | |
| CN107238788B (en) | Touch chip test system based on matrix capacitor plate and test method thereof | |
| CN101750580B (en) | Test method of functional module chip in integrated circuit | |
| US9495038B2 (en) | Detection of a conductive object during an initialization process of a touch-sensing device | |
| US10430008B2 (en) | Methods and apparatus for a 3-dimensional capacitive sensor having multi-operation electrodes | |
| US8204733B2 (en) | Power testing apparatus for universal serial bus interface | |
| US20090112505A1 (en) | Method and system for providing test and measurement guidance | |
| CN104597324B (en) | A kind of determination method of via parameters and through hole impedance value on circuit board | |
| CN102959390A (en) | Detecting a dielectric article | |
| CN110383089B (en) | Matrix capacitor plate and chip testing method | |
| CN104199581B (en) | One kind is based on big CTP, little CTPCapacitive detection circuit and capacitance detecting device | |
| JP5154196B2 (en) | Circuit board inspection equipment | |
| CN105373270A (en) | Touch control device | |
| CN106093662B (en) | Touch display module and electrical performance detection device and method thereof | |
| US8832638B2 (en) | Package test devices having a printed circuit board | |
| CN205880087U (en) | Electric performance detection device of touch -control display module assembly and touch -control display module assembly | |
| US20090167338A1 (en) | Test pattern for analyzing capacitance of interconnection line | |
| CN101719040A (en) | Testing apparatus of touch panel | |
| US9081056B2 (en) | Method for detecting working state of I/O pins of electronic components using charges from human body | |
| CN116482509B (en) | Radio frequency circuit testing method and device and related equipment | |
| CN221007627U (en) | Accelerometer circuit and main board of electronic equipment | |
| CN115562924B (en) | Method for detecting folding angle of folding screen, touch chip and electronic device | |
| CN117806889A (en) | Touch control testing system and touch control testing method based on capacitance matrix plate | |
| CN114665988B (en) | Antenna circuit | |
| CN102967776A (en) | Test system and method associated with capacitive sensing touch input device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |