CN110383089A - Grid capacitive plate and chip detecting method - Google Patents
Grid capacitive plate and chip detecting method Download PDFInfo
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- CN110383089A CN110383089A CN201880000177.8A CN201880000177A CN110383089A CN 110383089 A CN110383089 A CN 110383089A CN 201880000177 A CN201880000177 A CN 201880000177A CN 110383089 A CN110383089 A CN 110383089A
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Abstract
A kind of grid capacitive plate and chip detecting method are provided, grid capacitive plate, include: a plurality of first signal wire, a plurality of second signal line, the capacitance matrix that the capacitor of the intersection of each the first signal wire of item and each second signal line is formed is set, includes at least two capacitors in capacitance matrix；Chip detecting method includes, the capacitor of at least two capacitances is set in the capacitance matrix of grid capacitive plate, so as to simulate the function of normal condition (i.e. non-touch condition) and touch condition, and the test to the different performance situation of chip can be realized based on the function of grid capacitive plate.
Description
This application involves the field of test technology, in particular to a kind of grid capacitive plate and chip detecting method.
Extensive use with touch screen in fields such as smart phone, automobile and household electrical appliances, the demand of touch chip are also in explosive growth.For touch chip, functional and stability is extremely important, thus in volume production test, it needs to test the performance of touch chip.Currently, in touch chip test, it is whether normal to test each access of touch chip using self-discipline circuit built-in self-test (Automatic built-in self test, Abist).
The inventor finds that the existing technology has at least the following problems: in the prior art, tested by the circuit Abist each access of touch chip it is whether normal when, there is some accesses can not be covered using the circuit Abist, the test mode of touch chip and virtual condition deviation are larger, cause test coverage insufficient.
Summary of the invention
The application section Example is designed to provide a kind of grid capacitive plate and chip detecting method, the capacitor of at least two capacitances is set in the capacitance matrix of grid capacitive plate, to be able to achieve the function of simulation normal condition (i.e. non-touch condition) and touch condition, and the test to the different performance situation of chip can be realized based on the function of grid capacitive plate.
The embodiment of the present application provides a kind of grid capacitive plate, comprising: the capacitance matrix that the capacitor of the intersection of each first signal wire and each second signal line is formed is arranged in a plurality of first signal wire, a plurality of second signal line；It include the capacitor of at least two capacitances in capacitance matrix.
The embodiment of the present application also provides a kind of chip detecting method, provide such as above-mentioned grid capacitive plate, and grid capacitive plate is connected to chip to be measured；Using the first signal wire, second signal line one of signal wire as transmission channel, and using another signal wire as receiving channel；Successively apply scanning voltage to each transmission channel, and receives output voltage from each receiving channel；According to the received output voltage of each receiving channel, the performance condition of chip is analyzed.
The embodiment of the present application provides a kind of chip detecting method again, provides such as above-mentioned grid capacitive plate, and grid capacitive plate is connected to chip to be measured；Using the first signal wire or second signal line as current TCH test channel；Successively apply scanning voltage to each current TCH test channel, and receives output voltage from each current TCH test channel；According to each current received output voltage of TCH test channel, the performance condition of chip is analyzed.
The embodiment of the present application is in terms of existing technologies, the capacitor of at least two capacitances is set in the capacitance matrix of grid capacitive plate, to be able to achieve the function of simulation normal condition (i.e. non-touch condition) and touch condition, and the test to the different performance situation of chip can be realized based on the function of grid capacitive plate；Go out chip testing using the Functional Design of grid capacitive plate, is capable of the working environment of altitude simulation touch chip, to improve test coverage, while also improving test speed.
In addition, the capacitance for each capacitor being arranged successively on every first signal wire forms the corresponding capacitance distribution patterns of the first signal wire in grid capacitive plate；The capacitance for each capacitor being arranged successively on every second signal line forms the corresponding capacitance distribution patterns of second signal line；The first preset condition of each corresponding capacitance distribution patterns satisfaction of the first signal wire of item；Alternatively, the corresponding capacitance distribution patterns of each second signal line meet the second preset condition；Alternatively, the corresponding capacitance distribution patterns of each the first signal wire of item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition.Present embodiments provide the different designs scheme of capacitance matrix.
In addition, in grid capacitive plate, the first preset condition are as follows: the corresponding capacitance distribution patterns of each the first signal wire of item are all different；Second preset condition are as follows: the corresponding capacitance distribution patterns of each second signal line are all different.A kind of particular content for present embodiments providing preset condition provides a kind of specific design method of capacitance matrix.
In addition, being located on the diagonal line of capacitance matrix and each capacitor of diagonal line side all has the first capacitance, each capacitor positioned at the diagonal line other side all has the second capacitance.Present embodiments provide the specific design method of another kind of capacitance matrix.
In addition, the quantity of the first signal wire is equal to the quantity of second signal line.
In addition, in grid capacitive plate, the first preset condition are as follows: the corresponding capacitance distribution patterns of continuously arranged the first signal wire of m item are all different, and wherein m is the total number of integer more than or equal to 2 and m less than the first signal wire；Second preset condition are as follows: the corresponding capacitance distribution patterns of continuously arranged n second signal line are all different；Wherein n is less than the total number of second signal line for the integer more than or equal to 2 and n.Another particular content for present embodiments providing preset condition provides another specific design method of capacitance matrix.
In addition, in grid capacitive plate, the capacitor of different capacitances.The specific choice mode of different capacitances is present embodiments provided, so as to more accurately simulate the function of normal condition (i.e. non-touch condition) and touch condition.
In addition, including the capacitor of two kinds of capacitances in capacitance matrix, and two kinds of capacitances are respectively 1.5 pico farads and 1.0 pico farads in grid capacitive plate.
In addition, it is when transmission channel is applied scanning voltage, from the received output voltage of each receiving channel that each transmission channel, which corresponds to one group of output voltage and this group of output voltage, in chip detecting method；Using transmission channel as current TCH test channel；According to the received output voltage of each receiving channel, the performance condition of analysis chip, it include: for each current TCH test channel, by the voltage value of each output voltage in the corresponding one group of output voltage of current TCH test channel, as the corresponding voltage's distribiuting pattern of current TCH test channel；Judge whether the corresponding voltage's distribiuting pattern of current TCH test channel capacitance distribution patterns corresponding with current TCH test channel match；Wherein, the capacitance for each capacitor being arranged successively on each current TCH test channel forms the corresponding capacitance distribution patterns of current TCH test channel；If the judging result of each current TCH test channel is matching, determine that the touch detection function of chip is normal.Present embodiments provide a kind of whether normal specific implementation of touch detection function of detection chip.
In addition, grid capacitive plate is above-mentioned grid capacitive plate, and the corresponding capacitance distribution patterns of the first signal wire of each item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition in chip detecting method；It is when transmission channel is applied scanning voltage, from the received output voltage of each receiving channel that each transmission channel, which corresponds to one group of output voltage and this group of output voltage,；Using transmission channel as current TCH test channel；According to the received output voltage of each receiving channel, the performance condition of chip is analyzed, comprising: for each current TCH test channel, theoretical TCH test channel is identified according to the corresponding one group of output voltage of current TCH test channel；Judge whether theoretical TCH test channel and current TCH test channel are consistent；If it is inconsistent, determining that there are routing exceptions inside the pin corresponding to current TCH test channel of chip.Present embodiments providing a kind of detection chip whether there is the specific implementation of routing exception.
In addition, theoretical TCH test channel is identified according to the corresponding one group of output voltage of current TCH test channel, it include: for each current TCH test channel, by the voltage value of each output voltage in the corresponding one group of output voltage of current TCH test channel, as the corresponding voltage's distribiuting pattern of current TCH test channel；According to the default corresponding relationship of voltage's distribiuting pattern and theoretical TCH test channel, and obtain the corresponding theoretical TCH test channel of the corresponding voltage's distribiuting pattern of current TCH test channel.Present embodiments provide a kind of specific implementation for obtaining the corresponding theoretical TCH test channel of the corresponding voltage's distribiuting pattern of current TCH test channel.
In addition, in chip detecting method, according to each current received output voltage of TCH test channel, the performance condition of chip is analyzed, it include: whether is judged for each current TCH test channel if being matched from the received output voltage of current TCH test channel with the capacitance summation of each capacitor on current TCH test channel；If the corresponding judging result of each current TCH test channel is matching, determine that the touch detection function of chip is normal.Present embodiments provide a kind of whether normal specific implementation of touch detection function of detection chip.
In addition, grid capacitive plate is above-mentioned grid capacitive plate, and the corresponding capacitance distribution patterns of the first signal wire of each item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition in chip detecting method；According to each current received output voltage of TCH test channel, the performance condition of chip is analyzed, comprising: for each current TCH test channel, judge whether match from the received output voltage of current TCH test channel with the capacitance summation of each capacitor on current TCH test channel；If it does not match, determining that there are routing exceptions inside the pin corresponding to current TCH test channel of chip.Present embodiments providing a kind of detection chip whether there is the specific implementation of routing exception.
In addition, in chip detecting method, whether matched from the received output voltage of current TCH test channel with the capacitance summation of each capacitor on current TCH test channel, comprising: the default corresponding relationship of inquiry output voltage and capacitance summation, and obtain the corresponding capacitance summation of output voltage；The default corresponding relationship of TCH test channel and capacitance summation is inquired, and obtains the corresponding capacitance summation of current TCH test channel；Judge whether the corresponding capacitance summation of output voltage capacitance summation corresponding with current TCH test channel is consistent；Wherein, if unanimously, characterization matches from the received output voltage of current TCH test channel and the capacitance summation of each capacitor on current TCH test channel.Present embodiments provide a kind of whether matched specific implementation of capacitance summation for judging each capacitor on the received output voltage of current TCH test channel and current TCH test channel.
One or more embodiments are illustrated by the picture in corresponding attached drawing, these exemplary illustrations do not constitute the restriction to embodiment, element in attached drawing with same reference numbers label is expressed as similar element, unless there are special statement, composition does not limit the figure in attached drawing.
Fig. 1 is the schematic diagram according to the grid capacitive plate in the application first embodiment, wherein grid capacitive plate includes the capacitor of two kinds of capacitances；
Fig. 2 is the schematic diagram according to the grid capacitive plate in the application first embodiment, wherein grid capacitive plate includes the capacitor of three kinds of capacitances；
Fig. 3 is the schematic diagram according to the grid capacitive plate in the application second embodiment, wherein the corresponding capacitance distribution patterns of each the first signal wire of item are all different；
Fig. 4 is the schematic diagram according to the grid capacitive plate in the application second embodiment, wherein the corresponding capacitance distribution patterns of each second signal line are all different；
Fig. 5 A be according in the application second embodiment the corresponding capacitance distribution patterns of the first signal wire of each item and the corresponding capacitance distribution patterns of each second signal line be all satisfied preset condition grid capacitive plate schematic diagram, wherein, the quantity of the first signal wire is greater than the quantity of second signal line；
Fig. 5 B be according in the application second embodiment the corresponding capacitance distribution patterns of the first signal wire of each item and the corresponding capacitance distribution patterns of each second signal line be all satisfied preset condition grid capacitive plate schematic diagram, wherein, the quantity of second signal line is greater than the quantity of the first signal wire；
Fig. 6 be according in the application second embodiment on the diagonal line of capacitance matrix and each capacitor of diagonal line side is the first capacitance, each capacitor positioned at the diagonal line other side is the schematic diagram of the grid capacitive plate of the second capacitance, wherein, the quantity of the first signal wire is greater than the quantity of second signal line；
Fig. 7 be according in the application second embodiment on the diagonal line of capacitance matrix and each capacitor of diagonal line side is the first capacitance, each capacitor positioned at the diagonal line other side is the schematic diagram of the grid capacitive plate of the second capacitance, wherein, the quantity of the first signal wire is equal to the quantity of second signal line；
Fig. 8 A is the schematic diagram according to the grid capacitive plate in the application 3rd embodiment, wherein the corresponding capacitance distribution patterns of continuously arranged 2 the first signal wires are all different；
Fig. 8 B is the schematic diagram according to the grid capacitive plate in the application 3rd embodiment, wherein the corresponding capacitance distribution patterns of continuously arranged 2 the first signal wires are all different, and the corresponding capacitance distribution patterns of continuously arranged 2 second signal lines are all different,；
Fig. 9 is the specific flow chart according to the chip detecting method in the application fourth embodiment；
Figure 10 is the circuit diagram according to the mutual tolerance detection model in the application fourth embodiment；
Figure 11 is the specific flow chart according to the chip detecting method in the application fourth embodiment, wherein is detected for the touch detection function to touch chip；
Figure 12 is the specific flow chart according to the chip detecting method in the 5th embodiment of the application；
Figure 13 is the specific flow chart according to the chip detecting method in the application sixth embodiment；
Figure 14 is according to the circuit diagram from appearance detection model in the application sixth embodiment；
Figure 15 is the specific flow chart according to the chip detecting method in the application sixth embodiment, wherein is detected for the touch detection function to touch chip；
Figure 16 is the specific flow chart according to the chip detecting method in the 7th embodiment of the application；
Figure 17 is the whether matched specific flow chart of capacitance summation according to the judgement in the 7th embodiment of the application from each capacitor on the received output voltage of current TCH test channel and current TCH test channel.
In order to which the objects, technical solutions and advantages of the application are more clearly understood, with reference to the accompanying drawings and embodiments, the application section Example is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, it is not used to limit the application.
The application first embodiment is related to a kind of grid capacitive plate, grid capacitive plate includes: that capacitance matrix includes a plurality of first signal wire, a plurality of second signal line, and the capacitance matrix that the capacitor of the intersection of each the first signal wire of item and each second signal line is formed is arranged in；It in the present embodiment, is parallel to each other between each the first signal wire of item, is parallel to each other between each second signal line, each the first signal wire of item is mutually perpendicular to and intersects with each second signal line.It should be noted that one of them of the first signal wire and second signal line can be used as the transmission channel of grid capacitive plate, another is as receiving channel when grid capacitive plate is connected to chip；In the present embodiment, using the first signal wire as transmission channel (channel TX), second signal line be receiving channel (channel RX) for explanation is described.
It include the capacitor of at least two capacitances in the present embodiment, in capacitance matrix.In one example, please refer to Fig. 1, capacitance matrix includes the capacitor of two kinds of capacitances, and two kinds of capacitances are respectively 1.5 pico farads and 1.0 pico farads, capacitance matrix includes 5 the first signal wires (TX0 to TX4) and 5 second signal line (RX0 to RX4), (capacitance of the capacitor of intersection of the TX0 to TX4) is 1.0 pico farads, and (capacitance of the capacitor of TX0 to the intersection of TX4) is 1.5 pico farads for RX2 to RX4 and the first signal wire for RX0, RX1 and each the first signal wire of item.
In another example, as shown in Figure 2, capacitance matrix includes the capacitor of three kinds of capacitances (for three, it is so not limited), and three kinds of capacitances are respectively 2.0 pico farads, 1.5 pico farads and 1.0 pico farads are (as example, it is so not limited), capacitance matrix includes 5 the first signal wires (TX0 to TX4) and 5 second signal line (RX0 to RX4), TX0, (capacitance of the capacitor of RX0 to the intersection of RX4) is 1.0 pico farads to TX1 with each second signal line, TX2, (capacitance of the capacitor of RX0 to the intersection of RX4) is 1.5 pico farads to TX3 with each second signal line, (capacitance of the capacitor of RX0 to the intersection of RX4) is 2.0 pico farads to TX4 with each second signal line.
It should be noted that right the present embodiment is not intended to be limited in any the number of the first signal wire and second signal line in Fig. 1 and Fig. 2 by taking capacitance matrix includes 5 the first signal wires and 5 second signal lines as an example.
Existing capacitive touch screen can be become smaller under touch condition by the capacitance of the capacitor of touch area.Grid capacitive plate in the present embodiment can include the capacitor of at least two capacitances with artificial capacitor formula touch screen, in the capacitance matrix of grid capacitive plate, so that the lesser capacitor analog of capacitance is by touch area, the i.e. function of simulated touch state；The biggish capacitor analog of capacitance simulates the function of normal condition (i.e. touch condition) not by touch area.
Preferably, the capacitor of different capacitances meets following condition: the capacitance difference of any two kinds of capacitances is more than or equal to the one third of larger capacitance, so as to more accurately simulate the function of normal condition (i.e. non-touch condition) and touch condition.
The present embodiment is in terms of existing technologies, the capacitor of at least two capacitances is set in the capacitance matrix of grid capacitive plate, to be able to achieve the function of simulation normal condition (i.e. non-touch condition) and touch condition, and the test to the different performance situation of chip can be realized based on the function of grid capacitive plate；Go out chip testing using the Functional Design of grid capacitive plate, is capable of the working environment of altitude simulation touch chip, to improve test coverage, while also improving test speed.
The application second embodiment is related to a kind of grid capacitive plate, the present embodiment is improvement on the basis of first embodiment, it mainly thes improvement is that: providing the specific design scheme of grid capacitive plate, and the first preset condition are as follows: the corresponding capacitance distribution patterns of each the first signal wire of item are all different；Second preset condition are as follows: the corresponding capacitance distribution patterns of each second signal line are all different.
In the present embodiment, the capacitance for each capacitor being arranged successively on every first signal wire forms the corresponding capacitance distribution patterns of the first signal wire；The capacitance for each capacitor being arranged successively on every second signal line forms the corresponding capacitance distribution patterns of second signal line.
Three kinds of design schemes of grid capacitive plate are provided in the present embodiment, specific as follows:
The first, the first preset condition of each corresponding capacitance distribution patterns satisfaction of the first signal wire of item.
Second, the corresponding capacitance distribution patterns of each second signal line meet the second preset condition.
The third, the corresponding capacitance distribution patterns of each the first signal wire of item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition.
Wherein, the first preset condition are as follows: the corresponding capacitance distribution patterns of each the first signal wire of item are all different；Second preset condition are as follows: the corresponding capacitance distribution patterns of each second signal line are all different, based on three kinds of above-mentioned design schemes, available following grid capacitive plate.
The first, the first preset condition of each corresponding capacitance distribution patterns satisfaction of the first signal wire of item, the corresponding capacitance distribution patterns of i.e. each the first signal wire of item are all different, please refer to Fig. 3, capacitance matrix includes that ((the corresponding capacitance distribution patterns of RX0 to RX6), TX0 to TX4 are all different TX0 to TX4) 5 the first signal wires with 7 second signal lines.In Fig. 3, the capacitance for the capacitor being arranged successively on the first signal wire TX0 is 1.5pF, 1.0pF, 1.0pF, 1.0pF, 1.0pF, 1.0pF, 1.0pF；That is, the corresponding capacitance distribution patterns of the first signal wire TX0 are as follows: (3,2,2,2,2,2,2)；Wherein, capacitance distribution patterns herein are indicated with the ratio of capacitance, so without being limited thereto.It obtains by this method, each first signal wire (corresponding capacitance distribution patterns of TX0 to TX4), referring specifically to the following table 1.
Table 1
Second, the corresponding capacitance distribution patterns of each second signal line meet the second preset condition, that is the corresponding capacitance distribution patterns of each second signal line are all different, please refer to Fig. 4, capacitance matrix includes that ((the corresponding capacitance distribution patterns of RX0 to RX4), TX0 to TX7 are all different TX0 to TX6) 7 the first signal wires with 5 second signal lines.
The third, the corresponding capacitance distribution patterns of each the first signal wire of item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition, i.e., the corresponding capacitance distribution patterns of each the first signal wire of item are all different and the corresponding capacitance distribution patterns of each second signal line are all different.It please refers to Fig. 5 A (example), the number of the first signal wire is less than the number of second signal line；Capacitance matrix includes 5 the first signal wires (TX0 to TX4) and 7 second signal line (RX0 to RX6), (the corresponding capacitance distribution patterns of TX0 to TX4) are all different each the first signal wire of item, and (the corresponding capacitance distribution patterns of RX0 to RX6) are all different each second signal line.It please refers to Fig. 5 B (another example), the number of the first signal wire is greater than the number of second signal line；Capacitance matrix includes 7 the first signal wires (TX0 to TX6) and 5 second signal line (RX0 to RX4), (the corresponding capacitance distribution patterns of TX0 to TX6) are all different each the first signal wire of item, and (the corresponding capacitance distribution patterns of RX0 to RX4) are all different each second signal line.
In one example, it include the capacitor of two kinds of capacitances in capacitance matrix, and two kinds of capacitances are respectively the first capacitance and the second capacitance, on the diagonal line of capacitance matrix and each capacitor of diagonal line side is the first capacitance, each capacitor positioned at the diagonal line other side is the second capacitance, please refer to Fig. 6, capacitance matrix includes 5 the first signal wires (TX0 to TX4) and 7 second signal line (RX0 to RX6), (the corresponding capacitance distribution patterns of TX0 to TX4) are all different each the first signal wire of item, dotted line is the diagonal line of capacitance matrix, on the diagonal line and each capacitor of diagonal line side is 1.5pF, each capacitor positioned at the diagonal line other side is the second capacitance 1.0pF, it can be seen that the first preset condition of each corresponding capacitance distribution patterns satisfaction of the first signal wire of item in figure , i.e., the corresponding capacitance distribution patterns of each the first signal wire of item are all different；It is corresponding, using second signal line as transmission channel, the first signal wire as receiving channel, the corresponding capacitance distribution patterns of each second signal line can be then made to meet the second preset condition, i.e. the corresponding capacitance distribution patterns of each second signal line are all different, and details are not described herein.
Preferably, the quantity of first signal wire is equal to the quantity of second signal line, please refer to Fig. 7, capacitance matrix includes 5 the first signal wires (TX0 to TX4) and 5 second signal line (RX0 to RX4), first capacitance is 1.5 pico farads, second capacitance is 1.0 pico farads (as example, it is so not limited), dotted line is the diagonal line of capacitance matrix, on the diagonal line of capacitance matrix and each capacitor of diagonal line side is 1.5 pico farad of the first capacitance, each capacitor positioned at the diagonal line other side of capacitance matrix is 1.0 pico farad of the second capacitance, (the corresponding capacitance distribution patterns of TX0 to TX4) are all different each the first signal wire of item, and (the corresponding capacitance distribution patterns of RX0 to RX4) are all different each second signal line.
The present embodiment provides the different designs scheme of capacitance matrix for first embodiment, and meets the grid capacitive plate under above-mentioned first preset condition and the second preset condition.
The application 3rd embodiment is related to a kind of grid capacitive plate, the present embodiment is improvement on the basis of first embodiment, mainly the improvement is that: in the present embodiment, the first preset condition are as follows: the corresponding capacitance distribution patterns of continuously arranged the first signal wire of m item are all different；Second preset condition are as follows: the corresponding capacitance distribution patterns of continuously arranged n second signal line are all different.
In the present embodiment, the first preset condition are as follows: the corresponding capacitance distribution patterns of continuously arranged the first signal wire of m item are all different, and wherein m is the total number of integer more than or equal to 2 and m less than the first signal wire；Second preset condition are as follows: the corresponding capacitance distribution patterns of continuously arranged n second signal line are all different；Wherein n is less than the total number of second signal line for the integer more than or equal to 2 and n.Based on three kinds of design schemes in second embodiment, available following grid capacitive plate.
The first, in the corresponding capacitance distribution patterns of each the first signal wire of item, the corresponding capacitance distribution patterns of continuously arranged the first signal wire of m item are all different；Please refer to Fig. 8 A, capacitance matrix includes 6 the first signal wires (TX0 to TX5) and 4 second signal line (RX0 to RX3), the corresponding capacitance distribution patterns of continuously arranged 2 the first signal wires are all different, i.e., the corresponding capacitance distribution patterns of TX0, TX1 are all different, the corresponding capacitance distribution patterns of TX2, TX3 are all different, and the corresponding capacitance distribution patterns of TX4, TX5 are all different；Wherein, the corresponding capacitance distribution patterns of TX0, TX1, the corresponding capacitance distribution patterns of TX2, TX3 and the corresponding capacitance distribution patterns of TX4, TX5 are all the same, so without being limited thereto, the corresponding capacitance distribution patterns of TX0, TX1, the corresponding capacitance distribution patterns of TX2, TX3 and the corresponding capacitance distribution patterns of TX4, TX5 can not also be identical.
Second, in the corresponding capacitance distribution patterns of each second signal line, the corresponding capacitance distribution patterns of continuously arranged the first signal wire of n item are all different, concrete matrix capacitor board is similar with Fig. 8 A, only need to be using second signal line as transmission channel, the first signal wire as receiving channel, details are not described herein.
The third, the corresponding capacitance distribution patterns of continuously arranged the first signal wire of m item are all different, and the corresponding capacitance distribution patterns of continuously arranged the first signal wire of n item are all different, please refer to Fig. 8 B, capacitance matrix includes 6 the first signal wires (TX0 to TX5) and 4 second signal line (RX0 to RX3), the corresponding capacitance distribution patterns of continuously arranged 2 the first signal wires are all different, the corresponding capacitance distribution patterns of continuously arranged 2 second signal lines are all different, i.e., TX0, the corresponding capacitance distribution patterns of TX1 are all different, TX2, the corresponding capacitance distribution patterns of TX3 are all different, TX4, the corresponding capacitance distribution patterns of TX5 are all different, RX0, the corresponding capacitance distribution patterns of RX1 are all different, RX2, the corresponding capacitance point of RX3 Cloth pattern is all different.
It should be noted that, in the present embodiment by taking two kinds of capacitances of capacitor and capacitor in capacitance matrix including two kinds of capacitances are respectively 1.5 pico farads and 1.0 pico farads as an example, right the present embodiment is not intended to be limited in any the type of the capacitance for the capacitor for including in capacitance matrix and the size of capacitance.
It should also be noted that, the present embodiment only schematically describes the quantity of the first signal wire that capacitance matrix includes and second signal line, right the present embodiment is not intended to be limited in any this, can specifically set according to actual needs.
The present embodiment provides the grid capacitive plate met under above-mentioned first preset condition and the second preset condition for first embodiment.
The application fourth embodiment is related to a kind of chip detecting method, tests applied to touch chip；As shown in Figure 9: chip detecting method includes: step 101: providing the grid capacitive plate such as first embodiment to any one of 3rd embodiment, and grid capacitive plate is connected to chip to be measured；Using the first signal wire, second signal line one of signal wire as transmission channel, and using another signal wire as receiving channel；Step 102: successively applying scanning voltage to each transmission channel, and receive output voltage from each receiving channel；Step 103: according to the received output voltage of each receiving channel, analyzing the performance condition of chip.
The present embodiment is in terms of existing technologies, the capacitor of at least two capacitances is set in the capacitance matrix of grid capacitive plate, to be able to achieve the function of simulation normal condition (i.e. non-touch condition) and touch condition, and the test to the different performance situation of chip can be realized based on the function of grid capacitive plate；Go out chip testing using the Functional Design of grid capacitive plate, is capable of the working environment of altitude simulation touch chip, to improve test coverage, while also improving test speed.
The realization details of the chip detecting method of the present embodiment is specifically described below, the following contents only for convenience of the realization details provided is understood, not implements the necessary of this programme.Wherein, the present embodiment is specifically used for detecting the touch detection function of touch chip.
Chip detecting method in the present embodiment is based on mutual tolerance model, referring to FIG. 10, being the circuit diagram of mutual tolerance detection model, the capacitance of the capacitor on Cx representing matrix capacitor board, V
TXIndicate input signal, W indicates the frequency of input signal, V
RXIndicate output signal, following publicity can be obtained in the resistance of R indication circuit:
V
RX=R*W*Cx*V
TXFormula (1)
Wherein, input signal is constant, that is, W, V
TXConstant, the resistance R of circuit is constant；According to formula (1) it is found that output signal V
RXIt is proportional with the capacitor Cx on grid capacitive plate.
Due to the chip detecting method of the present embodiment, it is the principle based on mutual tolerance model and implements, output signal V
RXIt is proportional with the capacitor Cx on grid capacitive plate, it will as the subsequent principle foundation to chip testing analysis.
The detailed process of the chip detecting method of the present embodiment please refers to Fig. 9 and Figure 11.
In a step 101, it provides such as the grid capacitive plate in the first embodiment or the second embodiment, and grid capacitive plate is connected to chip to be measured.Wherein, the grid capacitive plate that grid capacitive plate provides for any one of first embodiment to 3rd embodiment.
Specifically, each first signal wire, each second signal line to be respectively connected to each pin of touch chip, every signal wire is connected to a pin.Wherein, using one of signal wire of the first signal wire, second signal line in the capacitance matrix of grid capacitive plate as transmission channel, and using another signal wire as receiving channel；That is, using the pin of touch chip being connect with each first signal wire as the pin of transmitting scanning signal, using the pin of touch chip being connect with each second signal line as the pin for receiving output signal.
In a step 102, successively apply scanning voltage to each transmission channel, and receive output voltage from each receiving channel.
Specifically, touch chip by being connected to the pin of transmission channel, successively applies scanning voltage, while the pin by being connected to receiving channel to each transmission channel, receives output voltage.
Step 103, according to the received output voltage of each receiving channel, the performance condition of chip is analyzed, Figure 11 is please referred to, specifically include following sub-step:
Sub-step 1031, for each transmission channel, by the voltage value of each output voltage in the corresponding one group of output voltage of transmission channel, as the corresponding voltage's distribiuting pattern of transmission channel.
Specifically, for a transmission channel, the voltage value of available one group of output voltage, using the voltage value of this group of output voltage as the corresponding voltage's distribiuting pattern of the transmitting, by taking the grid capacitive plate of Fig. 1 as an example, by 5 transmission channels (voltage value of the corresponding 5 groups of output voltages of TX0 to TX4), as the corresponding 5 voltage's distribiuting patterns of 5 transmission channels.
Sub-step 1032, judges whether the corresponding voltage's distribiuting pattern of transmission channel capacitance distribution patterns corresponding with transmission channel match.
Specifically, touch chip applies scanning voltage to transmission channel TX0 by taking transmission channel TX0 as an example, and by the voltage value of each output voltage in the corresponding one group of output voltage of transmission channel TX0, as the corresponding voltage's distribiuting pattern of transmission channel TX0, if the voltage value of each output voltage received is respectively: (4V, 4V, 6V, 6V, 6V), then the corresponding voltage's distribiuting pattern of transmission channel TX0 is (2,2,3,3,3)；As shown in Figure 1, the corresponding capacitance distribution patterns of transmission channel TX0 are (2,2,3,3,3)；By comparing it is found that the capacitance distribution patterns matching corresponding with transmission channel TX0 of the corresponding voltage's distribiuting pattern of transmission channel TX0；If the voltage value of each output voltage received is respectively: (4V, 4V, 4V, 6V, 6V), then the corresponding voltage's distribiuting pattern of transmission channel TX0 is (2,2,2,3,3), by comparing it is found that the corresponding voltage's distribiuting pattern of transmission channel TX0 capacitance distribution patterns corresponding with transmission channel TX0 mismatch.Based on similar principles, it can be determined that go out whether the corresponding voltage's distribiuting pattern of each transmission channel matches with capacitance distribution patterns.Wherein, for the ease of observation, the corresponding voltage's distribiuting pattern of transmission channel and capacitance distribution patterns are indicated in the form of ratio.
Sub-step 1033 determines that the touch detection function of chip is normal if the judging result of every transmission channel is matching.
Specifically, then illustrating that the touch detection function of touch chip is normal when the corresponding voltage's distribiuting pattern of every transmission channel capacitance distribution patterns corresponding with every transmission channel match；When mismatching there are the corresponding capacitance distribution patterns of the corresponding voltage's distribiuting pattern of one or more transmission channel, then illustrate that the touch detection function of touch chip is abnormal.
The 5th embodiment of the application is related to a kind of chip detecting method, and the present embodiment is roughly the same with fourth embodiment, is in place of the main distinction: in the third embodiment, detecting to the touch detection function of touch chip；In the present embodiment, detected extremely to inside the pin of touch chip with the presence or absence of routing.
In the present embodiment, the detailed process of chip detecting method is as shown in figure 12.Wherein, grid capacitive plate is the grid capacitive plate in second embodiment or 3rd embodiment, and the corresponding capacitance distribution patterns of the first signal wire of each item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition.
Wherein, step 201, step 202 are roughly the same with step 101 with step 102, are in place of main difference, using transmission channel as current TCH test channel, in the present embodiment, step 203, according to the received output voltage of each receiving channel, analyzes in the performance condition of chip, specifically includes:
Sub-step 2031 identifies theoretical TCH test channel according to the corresponding one group of output voltage of current TCH test channel for each current TCH test channel.
Specifically, for each current TCH test channel, by the voltage value of each output voltage in the corresponding one group of output voltage of current TCH test channel, as the corresponding voltage's distribiuting pattern of current TCH test channel.According to the default corresponding relationship of voltage's distribiuting pattern and theoretical TCH test channel, and thereby the corresponding theoretical TCH test channel of the corresponding voltage's distribiuting pattern of current TCH test channel can be obtained.
Concrete mode are as follows: each output voltage in the corresponding one group of output voltage of current TCH test channel is compared, and identifies the voltage jump point in this group of output voltage, and determines the capacitance jump position of the capacitor of voltage jump point characterization；Then according to capacitance jump position, capacitance distribution patterns, theoretical TCH test channel three default corresponding relationship, so as to obtain the corresponding theoretical TCH test channel of capacitance jump position.By taking the grid capacitive plate in Fig. 7 as an example, as shown in table 2 below, be capacitance jump position, capacitance distribution patterns, theoretical TCH test channel three default mapping table.
Table 2
It should be noted that, if the voltage jump point in the corresponding one group of output voltage of current TCH test channel is multiple, then need to identify the corresponding capacitance jump position of multiple voltage jump points, so as to according to multiple capacitance jump positions, obtain corresponding capacitance distribution patterns, then the corresponding theoretical TCH test channel of available capacitance distribution patterns, i.e., obtain the corresponding theoretical TCH test channel of current TCH test channel, by taking the grid capacitive plate of Fig. 3 as an example, if capacitance toggle bit is equipped with 2, and respectively the 4th capacitor and the 5th capacitor, then this corresponding capacitance distribution patterns of 2 two capacitance jump positions is (3, 3, 3, 3, 2, 3, 3), the corresponding theoretical TCH test channel of the capacitance distribution patterns is TX3, i.e., currently the corresponding theoretical TCH test channel of TCH test channel is TX3.
Sub-step 2032 judges whether theoretical TCH test channel is consistent with current TCH test channel.
Specifically, that is, the two is consistent when theoretical TCH test channel is same transmission channel with current TCH test channel, then it is abnormal to illustrate that routing is not present in the pin inside corresponding to current TCH test channel of touch chip.
Sub-step 2033, if it is inconsistent, determining that there are routing exceptions inside the pin corresponding to current TCH test channel of chip.
Specifically, when theoretical TCH test channel is different transmission channels from current TCH test channel, i.e. the two is inconsistent, then illustrates that routing is abnormal that is, between the external terminal of chip and the Pad of chip interior there are routing exception inside the pin corresponding to current TCH test channel of touch chip.
The present embodiment provides the specific implementation that whether there is routing exception inside a kind of pin of detection touch chip for fourth embodiment.
The application sixth embodiment is related to a kind of chip detecting method, tests applied to touch chip；As shown in figure 13, chip detecting method includes: step 301, provides the grid capacitive plate such as first embodiment to any one of 3rd embodiment, and grid capacitive plate is connected to chip to be measured；Step 302, successively apply scanning voltage to each current TCH test channel, and receive output voltage from each current TCH test channel；Step 303, according to each current received output voltage of TCH test channel, the performance condition of chip is analyzed.
The present embodiment is in terms of existing technologies, the capacitor of at least two capacitances is set in the capacitance matrix of grid capacitive plate, to be able to achieve the function of simulation normal condition (i.e. non-touch condition) and touch condition, and the test to the different performance situation of chip can be realized based on the function of grid capacitive plate；Go out chip testing using the Functional Design of grid capacitive plate, is capable of the working environment of altitude simulation touch chip, to improve test coverage, while also improving test speed.
The realization details of the chip detecting method of the present embodiment is specifically described below, the following contents only for convenience of the realization details provided is understood, not implements the necessary of this programme.Wherein, the present embodiment is specifically used for detecting the touch detection function of touch chip.
Chip detecting method in the present embodiment is based on please referring to Figure 14 from detection model is held, for the circuit diagram for holding detection model certainly, C
TxThe summation of the capacitance of the capacitor of a transmission channel on representing matrix capacitor board, V
TXIndicate input signal, W indicates the frequency of input signal, V
RXIndicate output signal, following publicity can be obtained in the resistance of R indication circuit:
V
RX=V
TX/(1+R*W*C
Tx) formula (2)
Wherein, input signal is constant, that is, W, V
TXConstant, the resistance R of circuit is constant；According to formula (2) it is found that output signal V
RXWith the capacitor C on grid capacitive plate
TxProportional relationship.
It due to the chip detecting method of the present embodiment, is implemented, output signal V based on the principle from molar type
RXWith the summation C of the capacitance of the capacitor of a transmission channel on grid capacitive plate
TxProportional relationship, it will as the subsequent principle foundation to chip testing analysis.
The detailed process of the chip detecting method of the present embodiment please refers to Figure 13 and Figure 15.
In step 301, the grid capacitive plate such as first embodiment into 3rd embodiment is provided, and grid capacitive plate is connected to chip to be measured.Wherein, the grid capacitive plate that grid capacitive plate provides for any one of first embodiment to 3rd embodiment.
Specifically, using in the capacitance matrix of grid capacitive plate the first signal wire or second signal line as current TCH test channel, and current TCH test channel is respectively connected to each pin of touch chip, every signal wire is connected to a pin.
In step 302, successively apply scanning voltage to each current TCH test channel, and receive output voltage from each current TCH test channel.
Specifically, touch chip by being connected to the pin of each current TCH test channel, successively applies scanning voltage, while the pin by being connected to each current TCH test channel to each current TCH test channel, output voltage is received from each current TCH test channel.
In step 303, according to the received output voltage of each receiving channel, the performance condition of chip is analyzed, Figure 15 is please referred to, specifically include following sub-step:
Sub-step 3031 judges whether match from the received output voltage of current TCH test channel with the capacitance summation of each capacitor on current TCH test channel for each current TCH test channel.
Specifically, prestoring the voltage value of output voltage and the default corresponding relationship of capacitance summation in touch chip；For each current TCH test channel, the voltage value of an available output voltage, according to the default corresponding relationship of the voltage value of output voltage and capacitance summation, judge whether match with the capacitance summation of each capacitor on current TCH test channel from the voltage value of the received output voltage of current TCH test channel, specific judgment mode are as follows: in input voltage V
TXUnder, the capacitance summation C of each capacitor on current TCH test channel
TXCorresponding output voltage is V
RXIf being not equal to V from the voltage value of the received output voltage of current TCH test channel
RX, then illustrate that the capacitance summation from each capacitor on the voltage value and current TCH test channel of the received output voltage of current TCH test channel mismatches；Conversely, then illustrating that the two matches.
Sub-step 3032 determines that the touch detection function of chip is normal if the corresponding judging result of each current TCH test channel is matching.
Specifically, then determining that the touch detection function of touch chip is normal when the received output voltage of each TCH test channel is matched with the capacitance summation of each capacitor on each TCH test channel；When there are the capacitance summation of the received output voltage of one or more TCH test channel and each capacitor on corresponding TCH test channel mismatch, then determining that the touch detection function of touch chip is abnormal.
The 7th embodiment of the application is related to a kind of chip detecting method, and the present embodiment is roughly the same with sixth embodiment, is in place of the main distinction: in the third embodiment, detecting to the touch detection function of touch chip；In the present embodiment, detected extremely to inside the pin of touch chip with the presence or absence of routing.
In the present embodiment, the detailed process of chip detecting method is as shown in figure 16.Wherein, grid capacitive plate is the grid capacitive plate in second embodiment or 3rd embodiment, and the corresponding capacitance distribution patterns of the first signal wire of each item meet the first preset condition and the corresponding capacitance distribution patterns of each second signal line are all satisfied the second preset condition.
Wherein, step 401, step 402 are roughly the same with step 301 with step 302, are in place of main difference, in the present embodiment, step 403, according to the received output voltage of each receiving channel, analyze the performance condition of chip, specifically include:
Sub-step 4031 judges whether match from the received output voltage of current TCH test channel with the capacitance summation of each capacitor on current TCH test channel for each current TCH test channel, with reference to Figure 17, including following sub-step:
Sub-step 40311, inquires the default corresponding relationship of output voltage and capacitance summation, and obtains the corresponding capacitance summation of output voltage.
Specifically, the default corresponding relationship of output voltage Yu capacitance summation is prestored in touch chip, according to from the received output voltage of current TCH test channel, the default corresponding relationship for inquiring output voltage and capacitance summation, from capacitance summation corresponding from the received output voltage of current TCH test channel can be obtained.
Sub-step 40312, inquires the default corresponding relationship of TCH test channel and capacitance summation, and obtains the corresponding capacitance summation of current TCH test channel.
Specifically, prestoring the default corresponding relationship of TCH test channel Yu capacitance summation in touch chip, the default corresponding relationship of TCH test channel and capacitance summation is inquired, so as to obtain the corresponding capacitance summation of current TCH test channel.
Sub-step 40313 judges whether the corresponding capacitance summation of output voltage capacitance summation corresponding with current TCH test channel is consistent.
Specifically, judge capacitance summation corresponding from the received output voltage of current TCH test channel, whether capacitance summation corresponding with current TCH test channel is equal, and when the two is equal, characterization matches from the received output voltage of current TCH test channel and the capacitance summation of each capacitor on current TCH test channel；If the two is not identical, characterizes and mismatched from the capacitance summation of each capacitor on the received output voltage of current TCH test channel and current TCH test channel, enter step 4032.
Sub-step 4032, if it does not match, determining that there are routing exceptions inside the pin corresponding to current TCH test channel of chip.
Specifically, if mismatched from the capacitance summation of each capacitor on the received output voltage of current TCH test channel and current TCH test channel, then illustrate that routing is abnormal that is, between the external terminal of chip and the Pad of chip interior there are routing exception inside the pin corresponding to current TCH test channel of chip；Based on the above principles, it can detecte out abnormal with the presence or absence of routing inside each pin of touch chip, it can detect to touch abnormal with the presence or absence of routing between each external terminal of chip and each Pad of chip interior.
The present embodiment provides the specific implementation that whether there is routing exception inside a kind of pin of detection touch chip for sixth embodiment.
It will be understood by those skilled in the art that the various embodiments described above are to realize the specific embodiment of the application, and in practical applications, can to it, various changes can be made in the form and details, without departing from spirit and scope.
Claims (16)
- A kind of grid capacitive plate characterized by comprising the capacitance matrix that the capacitor of the intersection of each first signal wire and each second signal line is formed is arranged in a plurality of first signal wire, a plurality of second signal line；It include the capacitor of at least two capacitances in the capacitance matrix.
- Grid capacitive plate as described in claim 1, which is characterized in that the capacitance for each capacitor being arranged successively on every first signal wire forms the corresponding capacitance distribution patterns of first signal wire；The capacitance for each capacitor being arranged successively on the every second signal line forms the corresponding capacitance distribution patterns of the second signal line；The corresponding capacitance distribution patterns of first signal wire described in each item meet the first preset condition；Alternatively, the corresponding capacitance distribution patterns of second signal line described in each item meet the second preset condition；Alternatively, the corresponding capacitance distribution patterns of the first signal wire described in each item, which meet the corresponding capacitance distribution patterns of second signal line described in first preset condition and each item, is all satisfied second preset condition.
- Grid capacitive plate as claimed in claim 2, which is characterized in thatFirst preset condition are as follows: the corresponding capacitance distribution patterns of the first signal wire described in each item are all different；Second preset condition are as follows: the corresponding capacitance distribution patterns of second signal line described in each item are all different.
- Grid capacitive plate as claimed in claim 3, which is characterized in thatOn the diagonal line of the capacitance matrix and each capacitor of the diagonal line side all has the first capacitance, and each capacitor positioned at the diagonal line other side all has the second capacitance.
- Grid capacitive plate as claimed in claim 4, which is characterized in that the quantity of first signal wire is equal to the quantity of the second signal line.
- Grid capacitive plate as claimed in claim 2, which is characterized in thatFirst preset condition are as follows: the corresponding capacitance distribution patterns of the first signal wire described in continuously arranged m item are all different, and wherein m is more than or equal to 2 integer and m is less than the total number of first signal wire；Second preset condition are as follows: the corresponding capacitance distribution patterns of second signal line described in continuously arranged n item are all different；Wherein n is more than or equal to 2 integer and n is less than the total number of the second signal line.
- Grid capacitive plate as described in claim 1, which is characterized in that the capacitor of different capacitances meets following condition: the capacitance difference of any two kinds of capacitances is more than or equal to the one third of larger capacitance.
- Grid capacitive plate as described in claim 1, which is characterized in that include the capacitor of two kinds of capacitances in the capacitance matrix, and described two capacitances are respectively 1.5 pico farads and 1.0 pico farads.
- A kind of chip detecting method characterized by comprisingSuch as grid capacitive plate described in any item of the claim 1 to 8 is provided, and the grid capacitive plate is connected to chip to be measured；Using first signal wire, the second signal line one of signal wire as transmission channel, and using another signal wire as receiving channel；Successively apply scanning voltage to each transmission channel, and receives output voltage from each receiving channel；According to each received output voltage of receiving channel, the performance condition of the chip is analyzed.
- Chip detecting method as claimed in claim 9, which is characterized in that it is when the transmission channel is applied the scanning voltage, from each received output voltage of receiving channel that each transmission channel, which corresponds to one group of output voltage and this group of output voltage,；Using the transmission channel as current TCH test channel；It is described according to each received output voltage of receiving channel, analyze the performance condition of the chip, comprising:For each current TCH test channel, by the voltage value of each output voltage in the corresponding one group of output voltage of the current TCH test channel, as the corresponding voltage's distribiuting pattern of the current TCH test channel；Judge whether the corresponding voltage's distribiuting pattern of current TCH test channel capacitance distribution patterns corresponding with the current TCH test channel match；Wherein, the capacitance for each capacitor being arranged successively on each current TCH test channel forms the corresponding capacitance distribution patterns of the current TCH test channel；If the judging result of each current TCH test channel is matching, determine that the touch detection function of the chip is normal.
- Chip detecting method as claimed in claim 9, it is characterized in that, the grid capacitive plate is grid capacitive plate described in any one of claim 3 to 6, and the corresponding capacitance distribution patterns of the first signal wire described in each item meet the corresponding capacitance distribution patterns of second signal line described in first preset condition and each item and are all satisfied second preset condition；It is when the transmission channel is applied the scanning voltage, from each received output voltage of receiving channel that each transmission channel, which corresponds to one group of output voltage and this group of output voltage,；Using the transmission channel as current TCH test channel；It is described according to each received output voltage of receiving channel, analyze the performance condition of the chip, comprising:For each current TCH test channel, theoretical TCH test channel is identified according to the corresponding one group of output voltage of the current TCH test channel；Judge whether the theoretical TCH test channel and the current TCH test channel are consistent；If it is inconsistent, determining that there are routing exceptions inside the pin corresponding to the current TCH test channel of the chip.
- Chip detecting method as claimed in claim 11, which is characterized in that described that theoretical TCH test channel is identified according to the corresponding one group of output voltage of the current TCH test channel, comprising:For each current TCH test channel, by the voltage value of each output voltage in the corresponding one group of output voltage of the current TCH test channel, as the corresponding voltage's distribiuting pattern of the current TCH test channel；According to the default corresponding relationship of voltage's distribiuting pattern and theoretical TCH test channel, and obtain the corresponding theoretical TCH test channel of the corresponding voltage's distribiuting pattern of the current TCH test channel.
- A kind of chip detecting method characterized by comprisingSuch as grid capacitive plate described in any item of the claim 1 to 8 is provided, and the grid capacitive plate is connected to chip to be measured；Using first signal wire or the second signal line as current TCH test channel；Successively apply scanning voltage to each current TCH test channel, and receives output voltage from each current TCH test channel；According to each current received output voltage of TCH test channel, the performance condition of the chip is analyzed.
- Chip detecting method as claimed in claim 13, which is characterized in that it is described according to each current received output voltage of TCH test channel, analyze the performance condition of the chip, comprising:For each current TCH test channel, judge whether match from the current received output voltage of TCH test channel with the capacitance summation of each capacitor on the current TCH test channel；If the corresponding judging result of each current TCH test channel is matching, determine that the touch detection function of the chip is normal.
- Chip detecting method as claimed in claim 13, it is characterized in that, the grid capacitive plate is grid capacitive plate described in any one of claim 3 to 6, and the corresponding capacitance distribution patterns of the first signal wire described in each item meet the corresponding capacitance distribution patterns of second signal line described in first preset condition and each item and are all satisfied second preset condition；It is described according to each current received output voltage of TCH test channel, analyze the performance condition of the chip, comprising:For each current TCH test channel, judge whether match from the current received output voltage of TCH test channel with the capacitance summation of each capacitor on the current TCH test channel；If it does not match, determining that there are routing exceptions inside the pin corresponding to the current TCH test channel of the chip.
- Chip detecting method as claimed in claim 15, which is characterized in that described whether to be matched from the current received output voltage of TCH test channel with the capacitance summation of each capacitor on the current TCH test channel, comprising:The default corresponding relationship of output voltage and capacitance summation is inquired, and obtains the corresponding capacitance summation of the output voltage；The default corresponding relationship of TCH test channel and capacitance summation is inquired, and obtains the corresponding capacitance summation of the current TCH test channel；Judge whether the corresponding capacitance summation of output voltage capacitance summation corresponding with the current TCH test channel is consistent；Wherein, if unanimously, characterization matches from the capacitance summation of the current received output voltage of TCH test channel and each capacitor on the current TCH test channel.
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