CN107238788B - Touch chip test system based on matrix capacitor plate and test method thereof - Google Patents
Touch chip test system based on matrix capacitor plate and test method thereof Download PDFInfo
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- CN107238788B CN107238788B CN201610188273.2A CN201610188273A CN107238788B CN 107238788 B CN107238788 B CN 107238788B CN 201610188273 A CN201610188273 A CN 201610188273A CN 107238788 B CN107238788 B CN 107238788B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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Abstract
The invention belongs to the technical field of touch screens, and discloses a touch chip testing system based on a matrix capacitor plate and a testing method thereof. The test system comprises a matrix capacitor plate, a configuration file acquisition module, a test link simulation module and a test module. The testing module is internally provided with a testing program used for loading the configuration file to the testing program, and then the testing program loaded with the configuration file is operated on the simulated self-capacitance link or mutual capacitance link so as to test the touch chip to be tested. According to the invention, when the touch chip to be tested is a mutual capacitance type touch chip, the matrix capacitor plate and the touch chip to be tested can jointly simulate a mutual capacitance link, and when the touch chip to be tested is a self-capacitance type touch chip, the matrix capacitor plate and the touch chip to be tested jointly simulate a self-capacitance link, so that the mutual capacitance type touch chip and the self-capacitance type touch chip can be tested on the basis of the matrix capacitor plate, and the test coverage rate of the matrix capacitor plate is improved.
Description
Technical Field
The invention belongs to the technical field of touch screens, and particularly relates to a touch chip testing system based on a matrix capacitor plate and a testing method thereof.
Background
Various touch screen terminals such as smart phones need to use a touch chip to identify and respond to touch operation of a user, and the touch chip can normally work on the premise that the touch screen terminal can be normally used.
The popularization of the touch screen terminal brings about explosive increase of the shipment volume of the touch chip, and in the mass production and manufacturing process of the touch chip, strict test analysis needs to be carried out on the touch chip to ensure that the shipped touch chip can work normally. The existing touch chip test analysis method has the following problems:
1. the coverage of the test tool is limited. The common touch screen has two types of mutual capacitance and self-capacitance, and a testing tool for a mutual capacitance type touch chip is a matrix capacitance plate, but the matrix capacitance plate can only be used for testing the mutual capacitance type touch chip but not the self-capacitance type touch chip, so that the testing coverage rate of the matrix capacitance plate is insufficient.
2. The self-capacitance touch chip has a large test error. When the self-capacitance type touch chip is tested, different grounding capacitors with fixed numerical values are constructed among different channels of the touch chip to simulate the self-capacitance change, but the fixed numerical values are added with the deviation among the channels, so that the test error is larger.
3. The test comprehensiveness and accuracy of the self-capacitance touch control chip are poor. When the self-capacitance type touch control chip is tested, whether the signal quantity change under different self-capacitance gears accords with expectation or not is tested, and the circuit performance when the self-capacitance is evaluated is not comprehensive and accurate enough, because the first, the testing gears are limited; second, variations in test signal levels adulterate numerical shifts due to chip manufacturing variations, test tool variations.
Disclosure of Invention
The invention provides a touch control chip test system based on a matrix capacitor plate, and aims to enable the matrix capacitor plate to simultaneously support the test of a mutual capacitance type touch control chip and a self-capacitance type touch control chip and improve the test coverage rate of the matrix capacitor plate.
The invention provides a touch chip test system based on a matrix capacitor plate, which comprises the matrix capacitor plate, a configuration file acquisition module, a test link simulation module and a test module;
the matrix capacitor plate is controlled to be connected with a touch chip to be tested during testing;
the configuration file acquisition module is used for acquiring a configuration file corresponding to the type of the touch chip to be detected; the configuration file comprises type information of the touch chip to be tested;
the test link simulation module is connected with the touch chip to be tested and used for controlling the touch chip to be tested and the matrix capacitor plate to form a corresponding effective circuit structure type according to the type information of the touch chip to be tested, so that the matrix capacitor plate and the touch chip to be tested jointly simulate a self-capacitance link or a mutual capacitance link required by the test;
the testing module is internally provided with a testing program used for loading the configuration file to the testing program and then running the testing program loaded with the configuration file on the simulated self-capacitance link or mutual capacitance link so as to test the touch chip to be tested.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the matrix capacitor board includes a PCB board, and a capacitor matrix is disposed on the PCB board; each row of the capacitor matrix has a first signal terminal and each column has a second signal terminal; in the capacitor matrix, first ends of all capacitors in each row are connected to the first signal terminals corresponding to the row, and second ends of all capacitors in each column are connected to the second signal terminals corresponding to the column; one of the first signal terminal and the second signal terminal is correspondingly connected with a signal input pin of the touch chip to be tested, and the other one of the first signal terminal and the second signal terminal is correspondingly connected with a signal output pin of the touch chip to be tested;
the touch chip to be tested comprises a first signal generating circuit, a second signal generating circuit, a first signal receiving circuit, a second signal receiving circuit, a plurality of output switch units which are in one-to-one correspondence with signal output pins of the touch chip to be tested, and a plurality of input switch units which are in one-to-one correspondence with signal input pins of the touch chip to be tested; each output switch unit comprises a first switch, a second switch and a third switch, and each input switch unit comprises a fourth switch, a fifth switch and a sixth switch;
the first signal generating circuit is connected with the corresponding signal output pins through each first switch, the first signal receiving circuit is connected with the corresponding signal output pins through each second switch, and the signal output pins of the touch chip to be tested are grounded through the corresponding third switches; the second signal generating circuit is connected with the corresponding signal output pins through the fourth switches, the second signal receiving circuit is connected with the corresponding signal output pins through the fifth switches, and the signal output pins of the touch chip to be tested are grounded through the corresponding sixth switches.
With reference to the first possible implementation manner of the first aspect, when the touch chip to be tested is a mutual capacitance touch chip, the test link simulation module is configured to control a first switch, a second switch, and a third switch in an output switch unit to be tested to be turned on, and control a fourth switch, a fifth switch, and a sixth switch in an input switch unit to be tested to be turned off;
when the touch chip to be tested is a self-capacitance touch chip, the test link simulation module is used for controlling the first switch, the second switch and the third switch in each output switch unit to be closed and to be opened in a first test stage, and controlling the fourth switch, the fifth switch and the sixth switch in each input switch unit to be opened or closed; the first test stage is used for controlling the first switch, the second switch and the third switch in each input switch unit to be switched on and switched off, and controlling the second switch, the third switch and the fourth switch in each output switch unit to be switched on and switched off; and the third switch and the sixth switch are switched on or off to determine the capacitance value of the simulated self-capacitance link.
With reference to the first possible implementation manner of the first aspect, when the touch chip to be tested is a mutual capacitance touch chip, the test link simulation module is further configured to control the first switch, the second switch, and the third switch in the output switch unit that does not need to be tested to be all turned off; and controlling the fourth switch, the fifth switch and the sixth switch in the input switch unit which does not need to be tested to be switched off.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the test module includes a first test submodule and a second test submodule;
the first testing submodule is used for judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset first detection threshold range or not when the touch chip to be tested is a mutual capacitance type touch chip, if so, judging that the functional test of the part corresponding to the testing position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the testing position is unqualified;
and the second testing submodule is used for judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset second detection threshold range or not when the touch chip to be tested is a self-capacitance type touch chip, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the test position is unqualified.
With reference to the second possible implementation manner of the first aspect, the test module further includes a stability determination sub-module, configured to divide a plurality of test results into at least two groups when the touch chip to be tested is tested for a plurality of times, determine a proximity degree between a sum of reciprocals of the detection data of the self-capacitance link simulated in each test in each group and a sum of reciprocals of the detection data of the self-capacitance link simulated in each test in other groups, and if the proximity degree is within a preset range, determine that the stability degree of the self-capacitance link of the chip to be tested is qualified, otherwise, determine that the stability degree of the self-capacitance link of the chip to be tested is unqualified;
each group of tests comprises a plurality of test results, and the sum of the capacitance values of the self-capacitance link simulated in each test in each group is the same as the sum of the capacitance values of the self-capacitance link simulated in each test in other groups.
With reference to the first aspect, in a third possible implementation manner of the first aspect, a capacitance value of each capacitor in the capacitor matrix is 1.5pF or 1 pF.
The second aspect of the invention provides a test method of a touch chip test system based on a matrix capacitor plate, wherein the matrix capacitor plate is controlled to be connected with a touch chip to be tested during testing; the testing method comprises the following steps:
a configuration file obtaining step: acquiring a configuration file corresponding to the type of the touch chip to be detected; the configuration file comprises type information of the touch chip to be tested;
a test link simulation step: controlling a corresponding effective circuit structure type to be formed between the touch chip to be tested and the matrix capacitor plate according to the type information of the touch chip to be tested, so that the matrix capacitor plate and the touch chip to be tested jointly simulate a self-capacitance link or a mutual capacitance link required by the test;
the testing steps are as follows: and loading the configuration file to the test program, and then running the test program loaded with the configuration file on the simulated self-capacitance link or mutual capacitance link to test the touch chip to be tested.
With reference to the second aspect, in a first possible implementation manner of the second aspect:
the matrix capacitor plate comprises a PCB, and a capacitor matrix is arranged on the PCB; each row of the capacitor matrix has a first signal terminal and each column has a second signal terminal; in the capacitor matrix, first ends of all capacitors in each row are connected to the first signal terminals corresponding to the row, and second ends of all capacitors in each column are connected to the second signal terminals corresponding to the row; one of the first signal terminal and the second signal terminal is correspondingly connected with a signal input pin of the touch chip to be tested, and the other one of the first signal terminal and the second signal terminal is correspondingly connected with a signal output pin of the touch chip to be tested;
the touch chip to be tested comprises a first signal generating circuit, a second signal generating circuit, a first signal receiving circuit, a second signal receiving circuit, a plurality of output switch units which are in one-to-one correspondence with signal output pins of the touch chip to be tested, and a plurality of input switch units which are in one-to-one correspondence with signal input pins of the touch chip to be tested; each output switch unit comprises a first switch, a second switch and a third switch, and each input switch unit comprises a fourth switch, a fifth switch and a sixth switch;
the first signal generating circuit is connected with the corresponding signal output pins through each first switch, the first signal receiving circuit is connected with the corresponding signal output pins through each second switch, and the signal output pins of the touch chip to be tested are grounded through the corresponding third switches; the second signal generating circuit is connected with the corresponding signal input pins through the fourth switches, the second signal receiving circuit is connected with the corresponding signal input pins through the fifth switches, and the signal input pins of the touch chip to be tested are grounded through the corresponding sixth switches.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the step of testing link simulation specifically includes:
mutual capacitance link simulation: controlling a first switch, a second switch and a third switch in an output switch unit to be tested to be closed, and controlling a fourth switch, a fifth switch and a sixth switch in an input switch unit to be tested to be opened;
self-capacitance link simulation: in the first test stage, a first switch, a second switch and a third switch in each output switch unit are controlled to be closed, and a fourth switch, a fifth switch and a sixth switch in each input switch unit are controlled to be opened or closed; in the second test stage, the fourth switch, the fifth switch and the sixth switch in each input switch unit are controlled to be closed, and the first switch, the second switch and the third switch in each output switch unit are controlled to be opened or closed; and the third switch and the sixth switch are switched on or off to determine the capacitance value of the simulated self-capacitance link.
With reference to the first possible implementation manner of the second aspect, in the mutual capacitance link simulation step, the method further includes: controlling a first switch, a second switch and a third switch in an output switch unit which does not need to be tested to be disconnected; and controlling the fourth switch, the fifth switch and the sixth switch in the input switch unit which does not need to be tested to be switched off.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the testing step includes:
when the touch chip to be tested is a mutual capacitance type touch chip, judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset first detection threshold range, if so, judging that the function test of the part corresponding to the test position in the touch chip to be tested is qualified, otherwise, judging that the function test of the part corresponding to the test position is unqualified;
and when the touch chip to be tested is a self-capacitance type touch chip, judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset second detection threshold range, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the test position is unqualified.
With reference to the second possible implementation manner of the second aspect, the testing step further includes:
when the touch chip to be tested is tested for multiple times, dividing multiple test results into at least two groups, judging the proximity degree of the reciprocal sum of the detection data of the self-capacitance link simulated during each test in each group and the reciprocal sum of the detection data of the self-capacitance link simulated during each test in other groups, if the proximity degree is within a preset range, judging that the stability degree of the self-capacitance link of the chip to be tested is qualified, otherwise, judging that the stability degree of the self-capacitance link of the chip to be tested is unqualified;
each group of tests comprises a plurality of test results, and the sum of the capacitance values of the self-capacitance link simulated in each test in each group is the same as the sum of the capacitance values of the self-capacitance link simulated in each test in other groups.
As can be seen from the foregoing embodiments of the present invention, according to the type of the touch chip to be tested, the touch chip to be tested and the matrix capacitor plate can be controlled to form a corresponding effective circuit structure type, that is, when the touch chip to be tested is a mutual capacitance type touch chip, the matrix capacitor plate and the touch chip to be tested can jointly simulate a mutual capacitance link, and when the touch chip to be tested is a self-capacitance type touch chip, the matrix capacitor plate and the touch chip to be tested can jointly simulate a self-capacitance link, so that the testing of the mutual capacitance type touch chip and the self-capacitance type touch chip can be simultaneously realized on the basis of the matrix capacitor plate, and the testing coverage rate of the matrix capacitor plate is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is an architecture schematic diagram of a touch chip testing system based on a matrix capacitor board according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure of the matrix capacitor plate of FIG. 1;
fig. 3 is a schematic connection diagram of each signal output pin of the touch chip to be tested in fig. 1;
fig. 4 is a schematic connection diagram of each signal input pin of the touch chip to be tested in fig. 1;
FIG. 5 is an equivalent model diagram of a self-capacitance signal link according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating an implementation of a testing method of a touch chip testing system based on a matrix capacitor board according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows an architecture principle of a touch chip testing system based on a matrix capacitor plate according to an embodiment of the present invention, and referring to fig. 1, the touch chip testing system based on a matrix capacitor plate according to an embodiment of the present invention includes a matrix capacitor plate 1, a configuration file obtaining module 2, a test link simulation module 3, and a test module 4. The matrix capacitor plate 1 has a structure as shown in fig. 2, where the matrix capacitor plate 1 includes a PCB on which a capacitor matrix is disposed, each row of the capacitor matrix has a first signal terminal (Rx0, Rx1, Rx2, Rx3, Rx4 …), and each column has a second signal terminal (Tx0, Tx1, Tx2, Tx3, Tx4 …). In the capacitor matrix, the first ends a of all the capacitors C in each row are connected to the first signal terminals (Rx0, Rx1, Rx2, Rx3, Rx4 …) corresponding to the row, and the second ends b of all the capacitors C in each column are connected to the second signal terminals (Tx0, Tx1, Tx2, Tx3, Tx4 …) corresponding to the column.
In the embodiment of the present invention, the capacitance value of each capacitor in matrix capacitor plate 1 generally takes 1.5pF or 1pF, and the capacitance values of the capacitors may be the same, that is, all of them are 1.5pF or all of them are 1 pF. It may be 1.5pF in part and 1pF in another part. The influence of parasitic parameters is reduced by adopting a high-precision capacitor with the packaging size of 0402 or 0201 for each capacitor, and meanwhile, the capacitor with the smaller packaging size is also beneficial to reducing the volume of the matrix capacitor plate 1.
One of the first signal terminals (Rx0, Rx1, Rx2, Rx3, Rx4 …) and the second signal terminals (Tx0, Tx1, Tx2, Tx3, Tx4 …) is connected to a signal input pin of the touch chip to be tested, and the other is connected to a signal output pin of the touch chip to be tested, that is, the first signal terminals (Rx0, Rx1, Rx2, Rx3, Rx4 …) may be connected to a signal input pin of the touch chip to be tested, and the second signal terminals (Tx0, Tx1, Tx2, Tx3, Tx4 …) are connected to a signal output pin of the touch chip to be tested; the first signal terminals (Rx0, Rx1, Rx2, Rx3, Rx4 …) may be correspondingly connected to signal output pins of the touch chip to be tested, and the second signal terminals (Tx0, Tx1, Tx2, Tx3, Tx4 …) may be correspondingly connected to signal input pins of the touch chip to be tested.
The configuration file obtaining module 2 is configured to obtain a configuration file corresponding to the type of the touch chip to be tested, where the configuration file includes type information of the touch chip to be tested, such as a self-capacitance touch chip or a mutual capacitance touch chip. As an embodiment of the present invention, the configuration file corresponding to the type of the touch chip to be tested may be input by the tester before each test, and if the type of the touch chip currently tested is the same as the type of the touch chip tested last time, the configuration file does not need to be input again. As another embodiment of the present invention, all types of configuration files may be backed up in advance, and a tester directly selects a configuration file that needs to be used at this time during a test, for example, a list including information of all configuration files is provided for the tester to select, the configuration file list may include options such as "configuration file for self capacitance test", "configuration file for mutual capacitance test", and then the corresponding configuration file content may be called according to the option name of the configuration file selected by the tester.
The test link simulation module 3 is connected to the touch chip to be tested, and is configured to control the touch chip to be tested and the matrix capacitor plate 1 to form a corresponding effective circuit structure type (i.e., a self-capacitance link or a mutual capacitance link) according to type information (i.e., a self-capacitance type or a mutual capacitance type) of the touch chip to be tested, so that the matrix capacitor plate 1 and the touch chip to be tested jointly simulate the self-capacitance link or the mutual capacitance link required by the test. After the matrix capacitor plate 1 and the touch chip to be tested jointly simulate a mutual capacitance link or a self-capacitance link, a foundation for running some functions of the touch chip to be tested is established, and the touch chip can be tested on the foundation to judge whether the touch chip meets the relevant standards.
As described above, the touch chip to be tested may be a mutual capacitance type or a self-capacitance type. No matter the mutual capacitance type touch control chip or the self capacitance type touch control chip, a signal generating circuit, a signal receiving circuit, a necessary switch element and the like required by normal work are designed in the touch control chip, and when the touch control chip to be tested is tested, the circuit and the switch element need to be reused. The following is a brief description of the internal circuit structure of the touch chip to be tested that needs to be reused during testing.
First, please refer to fig. 3 showing the connection relationship between the signal output pins of the touch chip to be tested. The touch chip to be tested comprises a first signal generating circuit 31, a first signal receiving circuit 32, and a plurality of output switch units 331 and 333n corresponding to the signal output pins 1-n of the touch chip to be tested one by one, wherein each output switch unit comprises a first switch K1, a second switch K2, and a third switch K3, and the first switch K1, the second switch K2, and the third switch K3 of each output switch unit can be controlled independently. The first signal generating circuit 31 is connected with the corresponding signal output pin through each first switch K1, the first signal receiving circuit 32 is connected with the corresponding signal output pin through each second switch K2, and each signal output pin 1-n of the touch chip to be tested is grounded through the corresponding third switch K3.
Next, please refer to fig. 4, which shows a connection relationship between signal input pins of the touch chip to be tested. The touch chip to be tested comprises a second signal generating circuit 41, a second signal receiving circuit 42, and a plurality of output switch units 431 and 433n corresponding to the signal input pins 1-n of the touch chip to be tested one by one, wherein each input switch unit comprises a fourth switch K4, a fifth switch K5 and a sixth switch K6, and similarly, the fourth switch K4, the fifth switch K5 and the sixth switch K6 of each input switch unit can also be controlled independently. The second signal generating circuit 41 is connected to the corresponding signal input pin through each fourth switch K4, the second signal receiving circuit 42 is connected to the corresponding signal input pin through each fifth switch K5, and each signal input pin of the touch chip to be tested is grounded through the corresponding sixth switch K6.
As can be seen from fig. 3 and 4, the circuit connection topologies of the signal output pin and the signal input pin of the touch chip to be tested are the same, and during testing, the test link simulation module 2 controls the states of some of the switches according to the type of the touch chip to be tested, so as to control whether the signal input pin and the signal output pin have signal input/output.
When the touch chip to be tested is of a mutual capacitance type, the test link simulation module 2 is configured to control the first switch K1, the second switch K2, and the third switch K3 in the output switch unit to be tested to be closed (floating to the ground), control the fourth switch K4, the fifth switch K5, and the sixth switch K6 in the input switch unit to be tested to be opened (floating to the ground), and control the first switch, the second switch, the third switch in the output switch unit not to be tested, and the fourth switch, the fifth switch, and the sixth switch in the input switch unit not to be tested to be opened under the control of the test link simulation module 2. At this time, each capacitor in the matrix capacitor plate 1 simulates a mutual capacitance between a signal output end and a signal input end in the mutual capacitance type touch screen, and since a mutual capacitance exists between each signal output pin and all signal input pins, the degree of conformity with the mutual capacitance type touch screen model at this time is very high.
When the touch chip to be tested is a self-capacitance type, in order to simulate a self-capacitance working mode in the matrix capacitor plate, the test is carried out in two test stages, the test link simulation module 2 is used for controlling the first switch K1, the second switch K2 and the third switch K3 in each output switch unit to be closed, and controlling the fourth switch K4, the fifth switch K5 and the sixth switch K6 in each input switch unit to be opened or closed in the first test stage; and the test circuit is also used for controlling the fourth switch K4, the fifth switch K5 and the sixth switch K6 in each input switch unit to be closed, the fifth switch K5 to be closed and the sixth switch K6 to be opened in the second test stage, and controlling the first switch K1, the second switch K2 and the third switch K3 in each output switch unit to be opened or closed.
For example, the RX group lines and the TX group lines are divided into two groups to be tested separately (the signal output pin lines of the touch chip to be tested are named as TX group lines to correspond to the second signal terminals TX0, TX1, TX2, TX3, TX4, etc. in the matrix capacitive plate 1, and the signal input pin lines are named as RX group lines to correspond to the first signal terminals RX0, RX1, RX2, RX3, RX4, etc. in the matrix capacitive plate 1). During the TX group test, all TX group lines are in the signal output and receiving states together (K1 and K2 are closed, K3 is open), while the lines in the RX group can be controlled to be grounded or completely floating (K4 and K5 are open, and K6 can be closed or opened as required), and the self-capacitance of the TX group lines depends on the number of the line grounds in the RX group and the capacitance value of a single capacitor, so that the self-capacitance of the TX group lines can be changed by changing the number of the line grounds in the RX group, and the change of the self-capacitance value of the self-capacitance type touch screen under the touch of a finger can be well simulated. Since the signal output pin connection diagram and the signal input pin connection diagram have the same topology, the RX group test may adopt the same test method as the TX group test. Therefore, the working mode of the matrix capacitor plate 1 in the self-capacitance test is very high in matching degree with the working mode of the actual self-capacitance touch screen.
The test module 4 comprises a first test submodule and a second test submodule, wherein the first test submodule is used for judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset first detection threshold range when the touch chip to be tested is a mutual capacitance type touch chip, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, otherwise, judging that the functional test of the part corresponding to the test position is unqualified. And the second testing submodule is used for judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset second detection threshold range or not when the touch chip to be tested is a self-capacitance type touch chip, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the test position is unqualified.
For example, the detection data of the capacitors at the ith row and the jth column of the matrix circuit board when testing the mutual capacitance type touch chip and the self-capacitance type touch chip are respectively Dij1、Dij2The first detection threshold corresponding to the capacitor is Dth1The second detection threshold is Dth2. Directly detecting the data D when judgingij1And a first detection threshold Dth1Comparing and detecting data Dij2And a second detection threshold Dth2And (6) comparing.
It can be seen from the above embodiments that the touch chip testing system based on the matrix capacitor plate provided by the embodiment of the invention can simultaneously realize two types of tests of mutual capacitance and self capacitance in the matrix capacitor plate 1, improves the test coverage rate compared with the case of simply performing the mutual capacitance test, is simple in device, and has high matching degree between the chip working environment under the mutual capacitance test and the self capacitance test and the real working environment under the capacitor screen, and high testing accuracy.
Further, as described above, the change of the self-capacitance value of the self-capacitance touch screen under the touch of a finger is simulated by changing the number of the ground capacitors (which is realized by closing the third switch K3 and the sixth switch K6) during the test of the self-capacitance touch chip, so that, due to the manufacturing and manufacturing differences of the self-capacitance touch chip and the numerical value offset caused by the deviation of the test tool, when the third switch K3 and the sixth switch K6 at different positions are selected to be grounded during each test, even if the number of the ground capacitors is the same every time, the test result may be different every time, and the accuracy of the test is affected. In order to eliminate the influence and avoid the influence of the simulated self-capacitance link on the test result, the stability of the simulated self-capacitance link needs to be further judged so as to improve the test accuracy.
Based on the above consideration, the test module 4 further includes a stability determination sub-module, configured to divide the multiple test results into at least two groups when the touch chip to be tested is tested for multiple times, determine a proximity degree between a reciprocal sum of detection data of the self-capacitance link simulated in each test in each group and a reciprocal sum of detection data of the self-capacitance link simulated in each test in other groups, and if the proximity degree is within a preset range, determine that the stability degree of the self-capacitance link of the chip to be tested is qualified, otherwise, determine that the stability degree of the self-capacitance link of the chip to be tested is unqualified;
each group of tests comprises a plurality of test results, and the sum of the capacitance values of the self-capacitance link simulated in each test in each group is the same as the sum of the capacitance values of the self-capacitance link simulated in each test in other groups.
The principle of the stability test described above is explained below. The principle is as follows: the stability of the self-capacitance circuit can be accurately evaluated by using the application method of the rule that the sum of the reciprocal of the generated semaphore value is the same under the condition that the sum of the values of the self-capacitances with the same gear number is the same, wherein the same gear refers to the test times. The condition that the rule is established only needs to construct that the total sum of the self-capacitance values with the same gear number is the same, and the conformity between the performance of the actual circuit and the ideal circuit model when the self-capacitance changes can be observed under the condition that the condition is established. By using the application method generated by the rule, the accurate capacitance value of the self-capacitance of a specific gear does not need to be constructed (the deviation influence of the self-capacitance value in the simulated self-capacitance link can be eliminated), and the influence of the internal resistance of the signal generation circuit and the size of the series resistor does not need to be concerned, so that the problem that the stability of the circuit when the self-capacitance changes is not well evaluated by a pure signal quantity control method can be solved.
The rule "the sum of the inverses of the values of the generated semaphore is the same under the condition that the sum of the values of the self-capacitors with the same gear number is the same" is proved. Referring to fig. 5, in the equivalent model of the self-capacitance signal link shown in fig. 5, S1 represents a source end output signal, R represents equivalent voltage dividing and current limiting resistances, C represents a certain line-to-ground capacitance (i.e., self-capacitance) of a chip, which changes with finger pressing, and Buf represents a driving circuit that inputs high impedance and outputs low impedance. The original value of the self-capacitance will depend on the magnitude of the S2 signal, while the S2 signal, with the S1 determination, will depend on the reactance ratio of R and C.
The following derives the law "the sum of the reciprocal values of the generated semaphore values is the same for self-capacitors of the same shift number, if the sum of the values is the same", as follows, capacitors of n shift stages are provided, wherein the capacitance values of one of the groups are C1, C2, … Cn, and the capacitance values of the other group are Cn +1, Cn +2, … C2n, wherein C1+ C2+ … + Cn +1+ Cn +2+ … + C2n, according to the capacitance reactance formula:
wherein z represents reactance; j is the imaginary unit, the square root of-1; w represents the signal angular frequency through the capacitor; and c represents a capacitance value. The following can be obtained:
from the equivalent model diagram of the self-capacitance signal link in fig. 2, it can be known that the relationship between S1 and S2 is:
let the signals of C1, C2, …, Cn +1, Cn +2, … and C2n corresponding to the S2 node be Combining equation (2) and equation (3) yields:
the law is proved.
For example, let the number of TX groups be M and the number of RX groups be N (M >4, N >4 for an actual touch IC). The detection data is linearly proportional to the magnitude of the signal S2, and is named as RawData, so that the change of the RawData can reflect the change of the S2. The following method is the focus of the text, and is intended to eliminate the influence of the deviation of the resistance R and the capacitance C in the evaluation method, and simultaneously well reflect the stability of the whole self-capacitance circuit when the self-capacitance C changes.
Setting the capacitance value of a single capacitor in the matrix capacitor plate as C, and considering the deviation of each capacitor, setting the numerical values of the RX group grounding capacitors as C1, C2 and C3... CN respectively; let k be the number of steps of the capacitance change that needs to be tested, and k may be 5 for the sake of describing this method without loss of generality.
In order to ensure the uniformity of the gear distribution, the number of the grounding capacitors can be respectively set as: 0. n/4, 2N/4, N-N/4, N (N is the number of RX group lines, N >4, and the division result is rounded), and simultaneously, 1 (N-2N/4) test of grounding capacitors is required to be added for constructing the next test method.
The specific ground capacitance distribution scheme for the self-capacitance test is as follows (explained in terms of RX group, the same method as for TX group):
watch (1)
As can be seen from the above capacitance distribution scheme, Cg1+ Cg 2-Cg 3+ Cg 4-Cg 5+ Cg6(5), the following equation set can be obtained from the rule "the sum of the inverses of the signal quantity values generated by the same-shift-number self-capacitance is the same under the condition that the sum of the values is the same":
in addition, in the equivalent model diagram of the self-capacitance signal link in fig. 5, RawData (which is a value calculated by the touch chip according to the received signal strength S2 and is linearly proportional to the signal strength S2, and may be referred to as an original value) is linearly proportional to the S2 signal, equation set (7) and equation set (8) can be derived:
the proportionality coefficients h1 and h2 are:
ideally, h1 is 1 and h2 is 1.
It can be seen that the stability of the whole circuit when the self-capacitance changes is evaluated by the equation set (7) and the equation set (8) constructed by the grounding capacitance distribution scheme is independent of the specific values of R and C, so that the influence of the deviation of the chip resistance R and the external test capacitance C is eliminated.
Equation (9) can be derived from the number of ground capacitors in the ground capacitor allocation scheme:
RawData6>RawData1>RawData3>RawData2>RawData5 (9)
in practical application, the chip is usually clamped (in a chip test, whether the chip passes or not is judged according to whether a test parameter meets the specification or not, the process is called clamping control), whether the minimum value RawData5 is within the original value Spec range or not is judged, whether the equation (9) is established or not is judged, the chip with the equation (9) not established is judged to be an NG slice directly, whether the difference value between the RawData6, the RawData1, the RawData3, the RawData2 and the RawData5 is within the original value change Spec clamping control range or not is judged, finally, the proportionality coefficients h1 and h2 are calculated according to the equation group (8), and the degree of closeness of the h1 and h2 to an ideal value 1 is observed to quickly and accurately evaluate the stability of the self-capacitance link when the self-capacitance changes.
It can be seen that on the basis of testing whether the semaphore change under different self-capacitance gears accords with the expectation or not, the stability of the self-capacitance driving circuit (signal source and internal resistance) during the change of the self-capacitance is evaluated by comparing the semaphore values generated under different self-capacitance gears with the conformity of the rules contained in the ideal self-capacitance model, so that the influence of numerical value deviation caused by the production and manufacturing difference of the touch chip and the deviation of a testing tool is eliminated, and the self-capacitance test is more accurate.
Fig. 6 shows an implementation flow of a testing method of a touch chip testing system based on a matrix capacitor plate according to an embodiment of the present invention, which is described in detail below.
Step S61, this step is used for obtaining the configuration file: and acquiring a configuration file corresponding to the type of the touch chip to be tested.
In hardware, the test of the touch chip needs a test link corresponding to the type of the touch chip to be tested, for example, the self-capacitance type touch chip needs a self-capacitance link, and the mutual capacitance type touch chip needs a mutual capacitance link. In software, the test program needs to load a configuration file corresponding to the type of the touch chip to be tested, where the configuration file includes related information such as the type of the touch chip to be tested. When both the hardware condition and the software condition are met, the test can be started by running the test program loaded with the configuration file on the corresponding test link.
As an embodiment of the present invention, the configuration file corresponding to the type of the touch chip to be tested may be input by the tester before each test, and if the type of the touch chip currently tested is the same as the type of the touch chip tested last time, the configuration file does not need to be input again.
As another embodiment of the present invention, all types of configuration files may be backed up in advance, and a tester directly selects a configuration file that needs to be used at this time during a test, for example, a list including information of all configuration files is provided for the tester to select, the configuration file list may include options such as "configuration file for self capacitance test", "configuration file for mutual capacitance test", and then the corresponding configuration file content may be called according to the option name of the configuration file selected by the tester.
Step S62, the function of this step is to simulate the test link: and controlling the touch chip to be tested and the matrix capacitor plate to form a corresponding effective circuit structure type according to the acquired configuration file, so that the matrix capacitor plate and the touch chip to be tested jointly simulate a self-capacitance link or a mutual capacitance link required by the test.
As described above, the configuration file includes the type of the touch chip to be tested and other relevant information, and therefore, it can be determined whether the self-capacitance link or the mutual capacitance link needs to be formed currently for testing according to the relevant information in the configuration file. The self-capacitance link or the mutual capacitance link is formed by the matrix capacitance plate and the touch chip to be tested, which is shown above and is not described herein again.
Step S63, the function of this step is to test the touch chip: and loading the acquired configuration file by the test program, and then running the test program loaded with the configuration file on the simulated self-capacitance link or mutual capacitance link to test the touch chip to be tested.
Further, step S62 specifically includes: mutual capacitance link simulation step and self-capacitance link simulation step. The mutual capacitance link simulation step comprises the following steps: and controlling a first switch, a second switch and a third switch in the output switch unit to be tested to be closed, and controlling a fourth switch, a fifth switch and a sixth switch in the input switch unit to be tested to be opened. The self-capacitance link simulation steps are as follows: in the first test stage, a first switch, a second switch and a third switch in each output switch unit are controlled to be closed, and a fourth switch, a fifth switch and a sixth switch in each input switch unit are controlled to be opened or closed; in the second test stage, the fourth switch, the fifth switch and the sixth switch in each input switch unit are controlled to be closed, and the first switch, the second switch and the third switch in each output switch unit are controlled to be opened or closed; and the third switch and the sixth switch are switched on or off to determine the capacitance value of the simulated self-capacitance link.
Further, step S62 further includes: controlling a first switch, a second switch and a third switch in an output switch unit which does not need to be tested to be disconnected; and controlling the fourth switch, the fifth switch and the sixth switch in the input switch unit which does not need to be tested to be switched off.
Further, step S63 includes: when the touch chip to be tested is a mutual capacitance type touch chip, judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset first detection threshold range, if so, judging that the function test of the part corresponding to the test position in the touch chip to be tested is qualified, otherwise, judging that the function test of the part corresponding to the test position is unqualified; and when the touch chip to be tested is a self-capacitance type touch chip, judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset second detection threshold range, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the test position is unqualified.
Further, step S53 further includes: when the touch chip to be tested is tested for multiple times, dividing multiple test results into at least two groups, judging the proximity degree of the reciprocal sum of the detection data of the self-capacitance link simulated during each test in each group and the reciprocal sum of the detection data of the self-capacitance link simulated during each test in other groups, if the proximity degree is within a preset range, judging that the stability degree of the self-capacitance link of the chip to be tested is qualified, otherwise, judging that the stability degree of the self-capacitance link of the chip to be tested is unqualified; each group of tests comprises a plurality of test results, and the sum of the capacitance values of the self-capacitance link simulated in each test in each group is the same as the sum of the capacitance values of the self-capacitance link simulated in each test in other groups.
In summary, the touch chip testing system based on the matrix capacitor plate provided by the embodiment of the invention can simultaneously realize two types of tests of mutual capacitance and self-capacitance in the simple device of the matrix capacitor plate, improve the testing coverage rate of the matrix capacitor plate, and evaluate the stability of a self-capacitance driving circuit (a signal source and internal resistance) during self-capacitance change by comparing the conformity degree of the signal quantity values generated under different self-capacitance gears with the rules contained in an ideal self-capacitance model on the basis of testing whether the signal quantity change under different self-capacitance gears accords with the expectation, so that the influence of value deviation caused by chip production and manufacturing differences and testing tool deviation is eliminated, and the self-capacitance test is more accurate.
In the several embodiments provided in the present application, it should be understood that the disclosed system and method may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In view of the above description of the touch chip testing system and the testing method thereof based on the matrix capacitive plate provided by the present invention, for those skilled in the art, there may be variations in the specific implementation and application scope according to the ideas of the embodiments of the present invention, and in summary, the contents of the present specification should not be construed as limiting the present invention.
Claims (8)
1. A touch chip test system based on a matrix capacitor plate is characterized by comprising the matrix capacitor plate, a configuration file acquisition module, a test link simulation module and a test module;
the matrix capacitor plate is controlled to be connected with a touch chip to be tested during testing;
the configuration file acquisition module is used for acquiring a configuration file corresponding to the type of the touch chip to be detected; the configuration file comprises type information of the touch chip to be tested;
the test link simulation module is connected with the touch chip to be tested and used for controlling the touch chip to be tested and the matrix capacitor plate to form a corresponding effective circuit structure type according to the type information of the touch chip to be tested, so that the matrix capacitor plate and the touch chip to be tested jointly simulate a self-capacitance link or a mutual capacitance link required by the test;
the test module is internally provided with a test program for loading the configuration file to the test program and then running the test program loaded with the configuration file on the simulated self-capacitance link or mutual capacitance link so as to test the touch chip to be tested;
the matrix capacitor plate comprises a PCB, and a capacitor matrix is arranged on the PCB; each row of the capacitor matrix has a first signal terminal and each column has a second signal terminal; in the capacitor matrix, first ends of all capacitors in each row are connected to the first signal terminals corresponding to the row, and second ends of all capacitors in each column are connected to the second signal terminals corresponding to the column; one of the first signal terminal and the second signal terminal is correspondingly connected with a signal input pin of the touch chip to be tested, and the other one of the first signal terminal and the second signal terminal is correspondingly connected with a signal output pin of the touch chip to be tested;
the touch chip to be tested comprises a first signal generating circuit, a second signal generating circuit, a first signal receiving circuit, a second signal receiving circuit, a plurality of output switch units which are in one-to-one correspondence with signal output pins of the touch chip to be tested, and a plurality of input switch units which are in one-to-one correspondence with signal input pins of the touch chip to be tested; each output switch unit comprises a first switch, a second switch and a third switch, and each input switch unit comprises a fourth switch, a fifth switch and a sixth switch;
the first signal generating circuit is connected with the corresponding signal output pins through each first switch, the first signal receiving circuit is connected with the corresponding signal output pins through each second switch, and the signal output pins of the touch chip to be tested are grounded through the corresponding third switches; the second signal generating circuit is connected with the corresponding signal input pins through each fourth switch, the second signal receiving circuit is connected with the corresponding signal input pins through each fifth switch, and each signal input pin of the touch chip to be tested is grounded through the corresponding sixth switch; when the touch chip to be tested is a mutual capacitance touch chip, the test link simulation module is used for controlling the first switch, the second switch and the third switch in the output switch unit to be tested to be closed, and controlling the fourth switch, the fifth switch and the sixth switch in the input switch unit to be tested to be opened;
when the touch chip to be tested is a self-capacitance touch chip, the test link simulation module is used for controlling the first switch, the second switch and the third switch in each output switch unit to be closed and to be opened in a first test stage, and controlling the fourth switch, the fifth switch and the sixth switch in each input switch unit to be opened or closed; the first test stage is used for controlling the first switch, the second switch and the third switch in each input switch unit to be switched on or switched off; the third switch and the sixth switch are turned on or off to determine the capacitance of the simulated self-capacitance link.
2. The touch chip test system according to claim 1, wherein when the touch chip to be tested is a mutual capacitance touch chip, the test link simulation module is further configured to control the first switch, the second switch, and the third switch of the output switch unit that does not need to be tested to be turned off; and controlling the fourth switch, the fifth switch and the sixth switch in the input switch unit which does not need to be tested to be disconnected.
3. The touch chip test system of claim 1, wherein: the test module comprises a first test submodule and a second test submodule;
the first testing submodule is used for judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset first detection threshold range or not when the touch chip to be tested is a mutual capacitance type touch chip, if so, judging that the functional test of the part corresponding to the testing position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the testing position is unqualified;
and the second testing submodule is used for judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset second detection threshold range or not when the touch chip to be tested is a self-capacitance type touch chip, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the test position is unqualified.
4. The touch chip testing system of claim 3, wherein the testing module further comprises a stability determining sub-module, configured to divide the multiple testing results into at least two groups when the touch chip to be tested is tested for multiple times, determine a proximity of a sum of reciprocals of the detection data of the self-capacitance link simulated in each test in each group to a sum of reciprocals of the detection data of the self-capacitance link simulated in each test in other groups, and determine that the stability of the self-capacitance link of the chip to be tested is qualified if the proximity is within a preset range, otherwise determine that the stability of the self-capacitance link of the chip to be tested is unqualified;
each group of tests comprises a plurality of test results, and the sum of the capacitance values of the self-capacitance link simulated in each test in each group is the same as the sum of the capacitance values of the self-capacitance link simulated in each test in other groups.
5. A test method of a touch control chip test system based on a matrix capacitor plate is characterized in that the matrix capacitor plate is controlled to be connected with a touch control chip to be tested during test; the testing method comprises the following steps:
a configuration file obtaining step: acquiring a configuration file corresponding to the type of the touch chip to be detected; the configuration file comprises type information of the touch chip to be tested;
a test link simulation step: controlling a corresponding effective circuit structure type to be formed between the touch chip to be tested and the matrix capacitor plate according to the type information of the touch chip to be tested, so that the matrix capacitor plate and the touch chip to be tested jointly simulate a self-capacitance link or a mutual capacitance link required by the test;
the testing steps are as follows: loading the configuration file to a test program, and then running the test program loaded with the configuration file on the simulated self-capacitance link or mutual capacitance link to test the touch chip to be tested; the matrix capacitor plate comprises a PCB, and a capacitor matrix is arranged on the PCB; each row of the capacitor matrix has a first signal terminal and each column has a second signal terminal; in the capacitor matrix, first ends of all capacitors in each row are connected to the first signal terminals corresponding to the row, and second ends of all capacitors in each column are connected to the second signal terminals corresponding to the row; one of the first signal terminal and the second signal terminal is correspondingly connected with a signal input pin of the touch chip to be tested, and the other one of the first signal terminal and the second signal terminal is correspondingly connected with a signal output pin of the touch chip to be tested;
the touch chip to be tested comprises a first signal generating circuit, a second signal generating circuit, a first signal receiving circuit, a second signal receiving circuit, a plurality of output switch units which are in one-to-one correspondence with signal output pins of the touch chip to be tested, and a plurality of input switch units which are in one-to-one correspondence with signal input pins of the touch chip to be tested; each output switch unit comprises a first switch, a second switch and a third switch, and each input switch unit comprises a fourth switch, a fifth switch and a sixth switch;
the first signal generating circuit is connected with the corresponding signal output pins through each first switch, the first signal receiving circuit is connected with the corresponding signal output pins through each second switch, and the signal output pins of the touch chip to be tested are grounded through the corresponding third switches; the second signal generating circuit is connected with the corresponding signal input pins through each fourth switch, the second signal receiving circuit is connected with the corresponding signal input pins through each fifth switch, and each signal input pin of the touch chip to be tested is grounded through the corresponding sixth switch; the test link simulation step specifically includes:
mutual capacitance link simulation: controlling a first switch, a second switch and a third switch in an output switch unit to be tested to be closed, and controlling a fourth switch, a fifth switch and a sixth switch in an input switch unit to be tested to be opened;
self-capacitance link simulation: in the first test stage, a first switch, a second switch and a third switch in each output switch unit are controlled to be closed, and a fourth switch, a fifth switch and a sixth switch in each input switch unit are controlled to be opened or closed; in the second test stage, the fourth switch, the fifth switch and the sixth switch in each input switch unit are controlled to be closed, and the first switch, the second switch and the third switch in each output switch unit are controlled to be opened or closed; the third switch and the sixth switch are turned on or off to determine the capacitance of the simulated self-capacitance link.
6. The testing method of claim 5, wherein the mutual capacitance link simulation step further comprises: controlling a first switch, a second switch and a third switch in the output switch unit which does not need to be tested to be disconnected; and controlling the fourth switch, the fifth switch and the sixth switch in the input switch unit which does not need to be tested to be disconnected.
7. The test method of claim 6, wherein the testing step comprises:
when the touch chip to be tested is a mutual capacitance type touch chip, judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset first detection threshold range, if so, judging that the function test of the part corresponding to the test position in the touch chip to be tested is qualified, otherwise, judging that the function test of the part corresponding to the test position is unqualified;
and when the touch chip to be tested is a self-capacitance type touch chip, judging whether the detection data of the capacitor at the position to be tested on the matrix capacitor plate meets a preset second detection threshold range, if so, judging that the functional test of the part corresponding to the test position in the touch chip to be tested is qualified, and otherwise, judging that the functional test of the part corresponding to the test position is unqualified.
8. The test method of claim 7, wherein the testing step further comprises:
when the touch chip to be tested is tested for multiple times, dividing multiple test results into at least two groups, judging the proximity degree of the reciprocal sum of the detection data of the self-capacitance link simulated during each test in each group and the reciprocal sum of the detection data of the self-capacitance link simulated during each test in other groups, if the proximity degree is within a preset range, judging that the stability degree of the self-capacitance link of the chip to be tested is qualified, otherwise, judging that the stability degree of the self-capacitance link of the chip to be tested is unqualified;
each group of tests comprises a plurality of test results, and the sum of the capacitance values of the self-capacitance link simulated in each test in each group is the same as the sum of the capacitance values of the self-capacitance link simulated in each test in other groups.
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