CN216209684U

CN216209684U - MCU testing arrangement and electronic equipment

Info

Publication number: CN216209684U
Application number: CN202122583939.3U
Authority: CN
Inventors: 余锦泽
Original assignee: Zhuhai Huge Ic Co ltd
Current assignee: Zhuhai Huge Ic Co ltd
Priority date: 2021-10-26
Filing date: 2021-10-26
Publication date: 2022-04-05
Anticipated expiration: 2031-10-26

Abstract

The embodiment of the application discloses MCU testing arrangement and electronic equipment relates to the test field. MCU testing arrangement includes: the device comprises a chip interface circuit, a power supply circuit, a reset circuit, a clock circuit, a hardware mode selection circuit, a serial port debugging interface circuit, an online debugging interface circuit, a general peripheral circuit, an IO interface circuit, a test equipment interface circuit, a communication interface circuit and a resistance matrix circuit. The method and the device can be used for testing the functions of the MCUs of different models, and can shorten the project development period and save the project development cost.

Description

MCU testing arrangement and electronic equipment

Technical Field

The utility model relates to the field of testing, in particular to an MCU testing device and electronic equipment.

Background

In MCU design enterprises, MCU of various models can be generally designed, and the current MCU verification test mode is a targeted test device which is independently developed for each model of MCU, so that the problems of long project development period and resource waste exist.

SUMMERY OF THE UTILITY MODEL

The MCU testing device and the electronic equipment provided by the embodiment of the application can solve the problem of high cost of long MCU testing development period in the related technology. The technical scheme is as follows:

in a first aspect, an embodiment of the present application provides an MCU testing apparatus, including:

the device comprises a chip interface circuit, a power supply circuit, a reset circuit, a clock circuit, a hardware mode selection circuit, a serial port debugging interface circuit, an online debugging interface circuit, a general peripheral circuit, an IO interface circuit, a test equipment interface circuit, a communication interface circuit and a resistance matrix circuit;

the chip interface circuit is used for connecting an MCU (microprogrammed control unit) to be tested, and the power supply circuit, the reset circuit, the clock circuit, the hardware mode selection circuit, the serial port debugging interface circuit, the online debugging interface circuit, the general peripheral interface circuit, the IO interface circuit, the general test interface circuit and the resistance matrix circuit are respectively connected with the chip interface circuit;

the power supply circuit provides working voltage for the MCU test device, the reset circuit performs reset operation on the MCU, the clock circuit is used for providing clock signals for the MCU, the hardware mode selection circuit is used for switching the running mode of the MCU, and the running mode is a normal starting mode or a test mode; the serial port debugging interface circuit is used for outputting test data of the MCU, the online debugging interface circuit is used for performing online debugging on the MCU, the general peripheral circuit is used for connecting general peripherals, the IO interface circuit is used for connecting all IO pins of the MCU, the resistance matrix circuit is used for providing pull-up resistance or pull-down resistance for all the IO pins of the MCU, and the communication interface circuit performs a communication function; the test equipment interface circuit is used for connecting external test equipment.

In a second aspect, the present application provides an electronic device comprising: the MCU testing device comprises any one of the MCU testing devices.

The beneficial effects brought by the technical scheme provided by some embodiments of the application at least comprise:

the MCU testing device is simple in circuit structure, can be compatible with function tests of MCUs of various different models, does not need to specially relate to testing hardware aiming at the MCU of a specific model, can be repeatedly used in the testing process, and can shorten the project development period and save the project development cost.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of an MCU testing apparatus according to an embodiment of the present invention;

fig. 2 to 14 are schematic circuit structures of various components in the MCU test apparatus provided in the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 to 10, the MCU testing apparatus according to an embodiment of the present invention includes: the device comprises a chip interface circuit 1, a power supply circuit 2, a reset circuit 3, a clock circuit 4, a hardware mode selection circuit 5, a serial port debugging interface circuit 6, an online debugging interface circuit 7, a general peripheral circuit 8, an IO interface circuit 9, a test equipment interface circuit 10, a resistance matrix circuit 11 and a communication interface circuit 12. The chip interface circuit 1 comprises a plurality of different types of chip slots for being compatible with various MCUs of different models, the type of the chip socket is matched with the packaging mode of the MCU to be calibrated, and the chip slots are used for being connected with the MCU to be calibrated.

Wherein, the connection relation of the above-mentioned parts is: the power circuit 2, the reset circuit 3, the clock circuit 4, the hardware mode selection circuit 5, the serial port debugging interface circuit 6, the online debugging interface circuit 7, the general peripheral circuit 8, the IO interface circuit 9, the test equipment interface circuit 10 and the communication interface circuit 12 are respectively connected with the chip interface circuit 1. The resistor matrix circuit is connected to the IO interface circuit 9.

Wherein, the theory of operation of the MCU testing arrangement of this application includes: and a user selects a matched chip socket to insert in the plurality of chip slots of the chip interface circuit according to the packaging mode of the MCU to be tested. The power switch of the MCU testing device is turned on, the power circuit 2 supplies power for each component in the MCU testing device, the power circuit 2 can provide voltage signals of multiple paths of different voltage values, working voltage can be provided for components with voltage requirements, each path of voltage signal is provided with a power indicator, when the path of voltage signal is selected, the associated power indicator emits green light, and if the path of voltage signal is not selected, the associated power indicator does not emit light. The reset circuit 3 is used for providing a reset signal for the MCU and indicating the MCU to reset. The clock circuit 4 is used to provide the MCU with a clock signal. The hardware mode selection circuit 5 is used to select different operation modes for the MCU: normal mode and test mode, etc. The serial port debugging interface circuit 6 is used for outputting test data, and the test data comprises: test items, test results, test IDs, and the like. The online debugging interface circuit 7 is used for debugging the current test code, and online single step operation is convenient for positioning and solving the relevant problems of the test code. The general-purpose peripheral circuit 8 is used for connecting general-purpose peripherals, and the general-purpose peripheral comprises: EEPRO, FLASH, keyboard or LED, etc. The IO interface circuit includes one or more connectors for connecting all IO pins of the MCU. The test equipment interface circuit 10 is used for externally connecting test equipment, and the test equipment comprises: external meters, oscilloscopes or spectrometers, etc. The resistor matrix circuit 11 includes a plurality of branches for providing a pull-up resistor or a pull-down resistor for each IO pin of the MCU. The communication interface circuit 12 is used for communication with an external device.

In one or more possible embodiments, referring to fig. 2, the MCU is provided with a reset pin MCLR and the reset circuit includes a capacitor C1. One end of the reset switch S1 is grounded, the other end is connected to the reset pin MCLR, and the capacitor C1 is connected across two ends of the reset switch S1.

In one or more possible embodiments, referring to fig. 3, the MCU is provided with a clock output pin XO and a clock input pin XI, and the clock circuit includes a passive crystal Y1, a capacitor C2, and a capacitor C3;

the shell (the third pin 3 and the fourth pin 4) of the passive crystal oscillator Y1 is grounded, the first electrode 1 of the passive crystal oscillator is connected with the clock output pin XO of the MCU, and the second electrode 2 of the passive crystal oscillator is connected with the clock input pin XI; one end of the capacitor C2 is connected with the first electrode, and the other end is grounded; one end of the capacitor C3 is connected to the second electrode, and the other end is grounded. The capacitance values of the capacitor C2 and the capacitor C3 are equal, for example: are all 22 pF.

In one or more possible embodiments, referring to fig. 4, the hardware mode selection circuit includes a switch S2, the switch S2 is provided with 4 switch paths, and 3 of the 4 switch paths are provided with parallel branches, each branch containing two resistors in series, for example: the two resistors have values of 1K and 100K.

In one or more possible embodiments, referring to fig. 5, the serial port debug interface circuit includes a serial port socket J6, the serial port socket J6 includes a ground pin GND, a receive data pin RXD1, a transmit data pin TXD1, and a power supply pin VDD UART; the ground pin GND is grounded, the transmitting data pin TXD1 and the receiving data pin RXD1 are respectively connected with an IO pin of the MCU, and the power supply pin VDD UART is connected with the power circuit.

In one or more possible embodiments, referring to fig. 6, fig. 6 is a schematic structural diagram of an online debugging interface circuit, where the online debugging interface circuit supports DEBUG and JTAG debugging, and a connection relationship between devices included in the online debugging interface circuit and each device is referring to fig. 6, which is not described herein again.

In one or more possible embodiments, the communication interface circuit includes a CAN bus interface circuit, an RS485 interface circuit, and an RS232 interface circuit, which are respectively used to connect the CAN device, the RS485 device, and the RS232 circuit, and connection relationships between devices included in the above circuits and the respective devices are shown in fig. 7 to 9, which are not described herein again.

In one or more possible embodiments, the general-purpose peripheral circuits include an EEPROM peripheral circuit, an SPI FLASH circuit, a key peripheral circuit, and an LED peripheral circuit. The connection relationship between the devices included in the circuit and each device is shown in fig. 10 to 13, and is not described herein again.

In one or more possible embodiments, referring to fig. 14, the resistor matrix circuit includes a plurality of branches connected in parallel, each branch includes two serial resistors, and the two resistors have a resistance value of 100K.

The electronic device provided by the embodiment of the application can include, besides the MCU testing apparatus described above, the following: a housing for housing the various components.

The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.

Claims

1. An MCU testing device, comprising:

2. The MCU test device of claim 1, wherein the power circuit provides multiple voltage signals, each of which is provided with a power indicator.

3. The MCU testing device of claim 1 or 2, wherein the MCU is provided with a reset pin MCLR;

the reset circuit includes: a reset switch S1 and a capacitor C1;

one end of the reset switch S1 is grounded, the other end is connected to the reset pin MCLR, and the capacitor C1 is connected across two ends of the reset switch S1.

4. The MCU testing device of claim 3, wherein the MCU is provided with a clock output pin XO and a clock input pin XI, the clock circuit comprises a passive crystal oscillator Y1, a capacitor C2 and a capacitor C3;

the shell of the passive crystal oscillator Y1 is grounded, the first electrode of the passive crystal oscillator is connected with a clock output pin XO of the MCU, and the second electrode of the passive crystal oscillator is connected with a clock input pin XI; one end of the capacitor C2 is connected with the first electrode, and the other end of the capacitor C2 is grounded; one end of the capacitor C3 is connected to the second electrode, and the other end is grounded.

5. An MCU testing device according to claim 1, 2 or 4, characterized in that the hardware mode selection circuit comprises: a switch S2, the switch S2 being provided with a plurality of switch channels, each switch channel being provided with a branch, each branch comprising a resistance of 100K and a resistance of 1K in series relationship.

6. The MCU testing device of claim 5, wherein the general purpose peripheral circuitry comprises one or more of EEPROM peripheral circuitry, SPIFLASH peripheral circuitry, key press peripheral circuitry, and LED peripheral circuitry.

7. The MCU test device of claim 6, wherein the communication interface circuit comprises: one or more of a CAN bus interface circuit, an RS485 interface circuit and an RS232 interface circuit.

8. An MCU testing arrangement according to claim 5 or 6, characterized in that the test device is a multimeter, oscilloscope or spectrometer.

9. An MCU test device as defined in claim 8, wherein the resistor matrix circuit comprises a plurality of parallel branches, each branch comprising two 100K resistors connected in series.

10. An electronic device, comprising any one of the above MCU test devices.