CN207337386U - A kind of server master board test device - Google Patents
A kind of server master board test device Download PDFInfo
- Publication number
- CN207337386U CN207337386U CN201721038128.2U CN201721038128U CN207337386U CN 207337386 U CN207337386 U CN 207337386U CN 201721038128 U CN201721038128 U CN 201721038128U CN 207337386 U CN207337386 U CN 207337386U
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- cpld
- contact
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- 238000012360 testing method Methods 0.000 title claims abstract description 29
- 230000011664 signaling Effects 0.000 claims description 7
- 230000006870 function Effects 0.000 description 9
- 238000004458 analytical method Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Abstract
The utility model discloses a kind of server master board test device, including pcb board card, pcb board card is equipped with motherboard connector, CPLD, indicator light and JTAG connectors, the size of the pcb board card is identical with the size of CPU, motherboard connector is equipped with contact, the contact is identical with the contact on CPU, and motherboard connector is connected by contact with CPLD, and the CPLD is also respectively connected with JTAG connectors and indicator light.The utility model at the same time can test multiple signals of mainboard, save the time, improve work efficiency.
Description
Technical field
Server board technical field of measurement and test is the utility model is related to, specifically a kind of server master board test dress
Put.
Background technology
Mainboard is the core board of server, and core devices CPU is located on mainboard.In addition, the dimension in order to facilitate server
Shield, test, CPU will not be directly welded on mainboard, but the slot for placing CPU is welded on mainboard.CPU is inserted installed in this
In groove.
CPU has some to configure signal, and for configuring the state of its work, and CPU gathers the configuration signal when powering on
Level, to be configured.In motherboard design, these configuration signal some are connected to power supply by resistance or pass through resistance
Ground connection, some due to other multiplexing functions, be connected to other function modules.Test phase is, it is necessary to these configuration signals
Test one by one, to ensure that CPU configurations meet design requirement.And this test is needed to the continuous power-on and power-off of system, and use oscillography
Device is tested to complete one by one, inefficiency.
Utility model content
The purpose of this utility model is to provide a kind of server master board test device, for solving existing test needs pair
The problem of system constantly powers on, and is tested one by one using oscillograph, and testing efficiency is low.
Technical solution is used by the utility model solves its technical problem：A kind of server master board test device, bag
Include pcb board card, pcb board card is equipped with motherboard connector, CPLD, indicator light and JTAG connectors, the size of the pcb board card with
The size of CPU is identical, and motherboard connector is equipped with contact, and the contact is identical with the contact on CPU, and motherboard connector is by touching
Point is connected with CPLD, and the CPLD is also respectively connected with JTAG connectors and indicator light.
Further, the contact includes reset signal contact and configuration signalling contact, and motherboard connector is respectively by multiple
Position signalling contact connects CPLD with configuration signalling contact, and CPLD connects JTAG connectors by JTAG pins.
Further, the indicator light has multiple, connects the GPIO pins of CPLD respectively.
Further, the contact further includes error signal contact, and error signal the contact portion CPLD, CPLD are also logical
Cross serial port connector connection PC.
Further, the CPLD is also connected with memory, and memory also connects signal reader by storing connector.
Further, the contact further includes power contact, and the power contact connects CPLD by ADC.
The effect provided in utility model content is only the effect of embodiment, rather than whole effects that utility model is all
Fruit, a technical solution in above-mentioned technical proposal has the following advantages that or beneficial effect：
1st, pcb board card is equipped with the contact identical with CPU contacts, and the size of pcb board card is identical with CPU sizes, makes PCB
Board can be installed in CPU slots, realize that simulation CPU is in place, flexible design is ingenious.
2nd, multiple configuration signals are sent to CPLD at the same time by the contact in motherboard connector, and is shown respectively by indicator light
Show the state of configuration signal, avoid testing multiple configuration signals one by one, save the time, improve work efficiency, and tester
The state of configuration signal can be intuitively got by the state of indicator light.
3rd, CPLD is also connected with memory, and memory connects signal analysis device by storing connector, and memory can be deposited
The configuration information of test is stored up, and the configuration information is sent to signal analysis device, configuration information is divided easy to tester
Analyse and check.
4th, CPLD also connects PC machine by serial port connector, is sent and ordered to CPLD using PC machine, sends CPLD specific
Error signal, by checking the daily record of BMC, judge the reliability of main board function, make the functional test to mainboard more comprehensive,
Overcome at the same time in traditional test, CPU is sent the defects of error signal is more difficult.
Brief description of the drawings
Fig. 1 is a kind of structure diagram of embodiment of device described in the utility model.
Embodiment
In order to clarify the technical characteristics of the invention, below by embodiment, and its attached drawing is combined, to this reality
It is described in detail with new.Following disclosure provides many different embodiments or example is used for realizing the utility model
Different structure.In order to simplify the disclosure of the utility model, hereinafter the component and setting of specific examples are described.In addition,
The utility model can in different examples repeat reference numerals and/or letter.This repetition is to simplify and clear mesh
, the relation between itself not indicating discussed various embodiments and/or setting.It is it should be noted that illustrated in the accompanying drawings
Component is not drawn necessarily to scale.The utility model eliminates description to known assemblies and treatment technology and process to avoid not
Necessarily limit the utility model.
A kind of as shown in Figure 1, embodiment of server master board test device provided by the utility model.
Test device is by being designed to realize PCB (Printed Circuit Board, printed circuit board) board
Test purpose.The size of the pcb board card is identical with CPU sizes, pcb board card is plugged in CPU slots.The pcb board card
Including motherboard connector, motherboard connector is equipped with the contact identical with CPU, for contacting slot transmission corresponding signal, and will
Signalling contact in place ground connection in motherboard connector is in place for simulating CPU.
Motherboard connector passes through reset signal contact, configuration signalling contact and error signal contact portion CPLD respectively
GPIO pins, the power supply signal contact of motherboard connector also pass through the GPIO pins of ADC connections CPLD.Wherein CPLD is
The abbreviation of Complex Programmable Logic Device, looks like for Complex Programmable Logic Devices, can in the present embodiment
Select the CPLD of model LCMXO2-4000HC-5TG144C.GPIO is the contracting of General Purpose Input Output
Write, look like for universal input/output.ADC is the abbreviation of Analog-to-Digital Converter, is looked like for analog-to-digital conversion
Device.The present embodiment selects the ADC of model ADC128.CPLD is by obtaining the digital signal of ADC, detection pcb board card power supply
No connection is normal, correspondingly, whether i.e. detection cpu power is normal.
The JTAG pins connection JTAG connectors of CPLD, for the configuration of burning CPLD, each pin of as CPLD is matched somebody with somebody
Corresponding function is put, reset signal receive capabilities, configuration signal receiving function, electricity is respectively configured in the GPIO pins for being, for example, CPLD
Source signal reception function, error signal sending function etc..Wherein JTAG is the abbreviation of Joint Test Action Group, meaning
Think for joint test working group.The header (i.e. 2 that 2x5, pin spacing are 2.45mm can be selected in the JTAG connectors of the present embodiment
Row, often arranges 5 pin, and be connected the connector that two pin spacing are 2.45mm).
CPLD also connects indicator light by GPIO pins, and indicator light has multiple, is respectively used to indicate whether to send and matches somebody with somebody confidence
Number, whether send error signal, whether send reset signal, whether send power supply signal etc..By the bright of indicator light or go out pair
Status signal is shown.
CPLD also connects memory by GPIO pins, and memory connects signal reader by storing connector.Deposit
Reservoir is used to store the configuration signal that CPLD is collected.The memory of model AT24C64 can be selected in the memory of the present embodiment,
The header (connector of 3 pin feet) of 3pin can be selected in storage connector, and signal reader is read by storing connector
Data in memory, signal reader make tester on the terminal device to configuration by the connection with terminal device
Signal etc. is analyzed.
CPLD also connects PC (personal computer, personal computer), the GPIO pipes of CPLD by serial port connector
Foot is connected with serial port connector, and serial port connector is used for serial ports and reads the configuration signal that CPLD is collected, and is sent and ordered by PC
Make to CPLD, CPLD is sent out error signal, such as CPU heat alarms.Realize simulation CPU and send error signal, overcome
In traditional test, the CPU is set to send the defects of error signal is more difficult.After CPU sends error signal, by checking BMC
Whether the daily record of (Baseboard Management Controller, baseboard management controller) detects this error signal, surveys
Try the reliability of mainboard error signal sending function.
The process tested using the device of above-described embodiment is：The pcb board card is installed in CPU slots and opened
Machine.CPLD (configures signal generally to come into force) acquisition configuration information when reset signal discharges when configuring signal and coming into force automatically, and
It is stored in memory, is indicated by indicator light, and is come out by serially printing.Tester can observe wherein any
One kind exports (indicator light, serial ports and storage information) to obtain the configuration status of current CPU, so as to be contrasted with preset value, confirms
Whether mainboard is problematic.Meanwhile can be sent and ordered to CPLD by serial port connector, make CPLD send certain specific mistake
Signal.After CPU sends the signal, the daily record of BMC can be checked, see whether detect this kind of signal, verify its functional reliability.
, it is necessary to be CPLD burning configuration informations by JTAG connectors, it is each that burning information includes CPLD before being tested
The functional configuration of a pin, configuration of inner function module etc., CPLD mentioned above connect reset signal by GPIO pins
Multiple components such as contact, configuration signalling contact, ADC, indicator light, the GPIO pins of connection are different GPIO pins respectively,
And each pin can realize that the processing to different input/output signals is due to that JTAG connectors configure the burning of CPLD pins
The reason for.Therefore in the description above, expression is not named respectively to GPIO pins.
The above is the preferred embodiment of the utility model, is come for those skilled in the art
Say, on the premise of the utility model principle is not departed from, some improvements and modifications can also be made, these improvements and modifications also by
It is considered as the scope of protection of the utility model.
Claims (6)
1. a kind of server master board test device, it is characterized in that：Including pcb board card, pcb board card be equipped with motherboard connector,
CPLD, indicator light and JTAG connectors, the size of the pcb board card is identical with the size of CPU, and motherboard connector, which is equipped with, to be touched
Point, the contact is identical with the contact on CPU, and motherboard connector is connected by contact with CPLD, and the CPLD is also respectively connected with
JTAG connectors and indicator light.
2. test device according to claim 1, it is characterized in that：The contact includes reset signal contact and configuration signal
Contact, motherboard connector connect CPLD by reset signal contact with configuration signalling contact respectively, and CPLD is connected by JTAG pins
Connect JTAG connectors.
3. test device according to claim 1 or 2, it is characterized in that：The indicator light has multiple, connects CPLD respectively
GPIO pins.
4. test device according to claim 1, it is characterized in that：The contact further includes error signal contact, the mistake
Error signal contact portion CPLD, CPLD also connect PC by serial port connector.
5. test device according to claim 1, it is characterized in that：The CPLD is also connected with memory, and memory also passes through
Store connector connection signal reader.
6. test device according to claim 1, it is characterized in that：The contact further includes power contact, and the power supply touches
Point connects CPLD by ADC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721038128.2U CN207337386U (en) | 2017-08-18 | 2017-08-18 | A kind of server master board test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721038128.2U CN207337386U (en) | 2017-08-18 | 2017-08-18 | A kind of server master board test device |
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| Publication Number | Publication Date |
|---|---|
| CN207337386U true CN207337386U (en) | 2018-05-08 |
Family
ID=62372955
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721038128.2U Expired - Fee Related CN207337386U (en) | 2017-08-18 | 2017-08-18 | A kind of server master board test device |
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| Country | Link |
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| CN (1) | CN207337386U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557992A (en) * | 2018-11-29 | 2019-04-02 | 郑州云海信息技术有限公司 | A kind of BMC repositioning method, device, terminal and storage medium |
| TWI691835B (en) * | 2018-12-18 | 2020-04-21 | 英業達股份有限公司 | Detection control circuit and detection control method |
| TWI734357B (en) * | 2020-01-21 | 2021-07-21 | 英業達股份有限公司 | Mainboard and assisting test method of thereof |
| CN114780468A (en) * | 2022-04-28 | 2022-07-22 | 北京百度网讯科技有限公司 | Server carrier plate, data communication method, server mainboard, system and medium |
-
2017
- 2017-08-18 CN CN201721038128.2U patent/CN207337386U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109557992A (en) * | 2018-11-29 | 2019-04-02 | 郑州云海信息技术有限公司 | A kind of BMC repositioning method, device, terminal and storage medium |
| TWI691835B (en) * | 2018-12-18 | 2020-04-21 | 英業達股份有限公司 | Detection control circuit and detection control method |
| TWI734357B (en) * | 2020-01-21 | 2021-07-21 | 英業達股份有限公司 | Mainboard and assisting test method of thereof |
| CN114780468A (en) * | 2022-04-28 | 2022-07-22 | 北京百度网讯科技有限公司 | Server carrier plate, data communication method, server mainboard, system and medium |
| CN114780468B (en) * | 2022-04-28 | 2023-08-11 | 北京百度网讯科技有限公司 | Server carrier plate, data communication method, server main board, system and medium |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180508 Termination date: 20180818 |