CN211509076U

CN211509076U - FPGA remote loading and debugging system

Info

Publication number: CN211509076U
Application number: CN202020566271.4U
Authority: CN
Inventors: 汪魁
Original assignee: Chengdu Medium Kelong Microelectronics Co ltd
Current assignee: Chengdu Medium Kelong Microelectronics Co ltd
Priority date: 2020-04-16
Filing date: 2020-04-16
Publication date: 2020-09-15
Anticipated expiration: 2030-04-16

Abstract

The utility model discloses a long-range loading of FPGA and debug system, which comprises a microcontroller, microcontroller sets up JTAG interface and network interface, microcontroller passes through JTAG interface connection FPGA, microcontroller passes through network interface connection network physical layer, network physical layer passes through network communication with the debugging host computer and is connected, the encapsulation is equipped with in the microcontroller and is used for the network signal to parse, the main control chip of XVC signal conversion, the XVC agreement is integrated in main control chip, the debugging host computer sends the configuration instruction for microcontroller through the network, microcontroller simulation produces the JTAG chronogenesis, the JTAG chronogenesis passes through the JTAG interface and sends for FPGA, FPGA accomplishes the configuration. FPGA debugging and program solidification updating can be realized at a far end; all the array elements are accessed to a closed local area network by using an exchanger, and a remote terminal can access nodes in the local area network through any port of the exchanger; the switching network is integrated into the FPGA remote loading and debugging system, and when the debugging host is connected into the switching network, different board cards can be debugged only by switching to different IPs in the integrated design environment.

Description

FPGA remote loading and debugging system

Technical Field

The utility model relates to a FPGA debugs technical field, especially relates to a long-range loading of FPGA and debug system.

Background

The FPGA program in the military electronic system and the functional module containing the XilinxFPGA often needs to be modified and updated. The existing FPGA debugging has the following problems:

1. electronic equipment is often arranged at a position where personnel can not reach or can not fix and debug for a long time in use, such as a comprehensive mast in the prior ship/ship, the equipment is uniformly arranged on the mast, if a traditional USB debugging mode is adopted, JTAG signal lines need to be directly inserted into a debugging port of the equipment, the equipment can only be detached for independent debugging or the personnel works on the mast for a long time due to the limitation of the effective length of 1-2 meters of USB data lines, and the board card debugging port needs to be exposed and independently debugged if necessary;

2. in an array-distributed product, for example, a common radar array, there may be hundreds of array elements, each array element has an FPGA, when large-area maintenance is required, the array element equipment needs to be disassembled in a conventional manner, and then a USB simulator is used to debug one by one, which is very heavy;

3. when the extension equipment needs to realize traditional USB debugging, the JTAG interface of each FPGA single plate is often led out to an extension panel independently, and when a debugging target needs to be switched, the simulator needs to be switched to the corresponding JTAG interface;

4. for the maintenance work of the equipment, if the online upgrade or remote upgrade function of the equipment is to be realized, a corresponding complex remote upgrade circuit needs to be added in the design stage of the board card.

Disclosure of Invention

The utility model aims at providing a long-range loading of FPGA and debug system for solving above-mentioned problem just.

In order to realize the above-mentioned purpose, the utility model provides a long-range loading of FPGA and debug system, which comprises a microcontroller, microcontroller sets up JTAG interface and network interface, microcontroller passes through JTAG interface connection FPGA, microcontroller passes through network interface connection network physical layer, network physical layer passes through network communication with the debugging host computer and is connected, the encapsulation is equipped with in the microcontroller and is used for the network signal to parse, the master control chip of XVC signal conversion, the XVC agreement is integrated in master control chip, the debugging host computer sends the configuration instruction for microcontroller through the network, the microcontroller simulation produces the JTAG chronogenesis, the JTAG chronogenesis sends for FPGA through the JTAG interface, FPGA accomplishes the configuration.

The beneficial effects of the utility model reside in that:

the utility model relates to a long-range loading of FPGA and debug system breaks through the restriction of distance: the FPGA debugging and the program solidification updating of the FPGA can be realized at a far end only by connecting to the equipment to be debugged through a network cable;

breakthrough the limitation of quantity: the FPGA remote loading and debugging system is used, and only the switch is needed to be used for connecting all the array elements into a closed local area network, so that the remote terminal can access the nodes in the local area network through any port of the switch, debug the FPGA of any array element in a switching network, and even update all node programs in the whole network in a broadcasting mode;

convenient realization route: the switching network is integrated into an FPGA remote loading and debugging system, the contradiction between the number of the board cards and JTAG ports on the extension sets is solved at a very low cost, when a debugging host is connected into the switching network, different board cards can be debugged only by switching to different IPs in an integrated design environment, a simulator does not need to be repeatedly plugged and pulled, and only one network cable interface is needed externally no matter the number of the board cards.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

fig. 1 is a connection block diagram of the FPGA remote loading and debugging system of the present invention;

fig. 2 is a connection block diagram of the main control chip.

Detailed Description

The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.

As shown in fig. 1, the utility model relates to a long-range loading of FPGA and debug system, including microcontroller, microcontroller sets up JTAG interface and network interface, microcontroller passes through JTAG interface connection FPGA, microcontroller passes through network interface connection network physical layer, network physical layer passes through network communication with the debugging host computer and is connected, the encapsulation is used for the network signal to parse in the microcontroller, the master control chip of XVC signal conversion, the XVC agreement is integrated in master control chip, the debugging host computer sends the configuration instruction for microcontroller through the network, the microcontroller simulation produces the JTAG chronogenesis, the JTAG chronogenesis sends for FPGA through the JTAG interface, FPGA accomplishes the configuration.

The microcontroller adopts embedded ARMCortex^TMA 32-bit high performance general purpose microcontroller of M3 core. It adopts ARM high-performance dual-bus architecture. The highest working frequency of the kernel can reach 75MHz, and 32-bit single-cycle hardware multiplication is supported in the kernel. The advanced ARMThrum instruction set technology makes the instruction more compact and is easy to design and debug the program.

The master control chip is integrated into the microcontroller and its connection in the system is shown in fig. 2. The XVC protocol is developed secondarily and encapsulated in a main control chip, so that the protocol can run in a chip with ultra-low power consumption efficiently, the function of the protocol is equal to that of a Jtag cable, a user is allowed to directly debug the Jtag of the Xilinx FPGA through the Ethernet without using a USB simulator, complete Ethernet TCP protocol analysis and XVC signal conversion can be realized by a single chip through assembly level optimization and JTAG time sequence fitting, and the whole technical scheme is nationwide, productive and independently controllable.

After the debugging host establishes connection with the network physical layer through the IP address, the debugging host starts to send Getinfo information to the network physical layer for obtaining the version of the XVC server, and the network physical layer feeds back corresponding version information after receiving the information. And the debugging host starts to send the settck information to the network physical layer, and the network physical layer feeds back the communication clock information. And the debugging host starts to send shitf information to the MCU again, wherein the shitf information comprises TMS (transport management system) and TDI (transport driver interface) data contents and data length, the network physical layer sends each bit data TMS and TDI data to the FPGA in sequence, and one bit data is read from the TDO interface. And returning all the finally read data to the debugging host through the network.

The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present disclosure are not described again.

In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.

Claims

The FPGA remote loading and debugging system is characterized in that: the XVC-based micro-controller comprises a microcontroller, wherein the microcontroller is provided with a JTAG interface and a network interface, the microcontroller is connected with an FPGA through the JTAG interface, the microcontroller is connected with a network physical layer through the network interface, the network physical layer is connected with a debugging host through network communication, a main control chip for network signal analysis and XVC signal conversion is packaged in the microcontroller, an XVC protocol is integrated in the main control chip, the debugging host sends a configuration instruction to the microcontroller through a network, the microcontroller simulates to generate a JTAG time sequence, the JTAG time sequence is sent to the FPGA through the JTAG interface, and the FPGA completes configuration.