CN101963948B - BMCH protocol data transceiver module based on CPCI bus - Google Patents
BMCH protocol data transceiver module based on CPCI bus Download PDFInfo
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Abstract
The invention relates to a BMCH protocol data transceiver module based on a CPCI bus, comprising a hardware module and an FPGA program, wherein the hardware module comprises an impedance control circuit board, an electronic component, an SCSI50 signal gang socket, a standard CPCI bus connector and a standard 3U Eurocard board card front panel; the impedance control circuit board and the electronic component are the core functional carriers of the invention and are divided into five functional units, i.e. an FPGA unit, a CPCI bus unit, a BMCH protocol transmitting and conditioning unit, a BMCHprotocol receiving and conditioning unit and an assistant unit; and the FPGA program comprises a BMCH protocol data receiver module, a BMCH protocol data transmitter module and a self-checking functional module and is programmed and developed by Verilog HDL. The invention has stable performance and high reliability and can carry out continuous transmission of the BMCH protocol data of large data volume for a long term; CPCI bus data transmission has a DMA function, practical bus transmission rate can reach 80MB/s, and no frames are lost by high-speed continuous transmission; and the BMCH bus signal has strong driving capability and long transmission distance. The invention has simple structure, low cost and convenient use.
Description
Technical field
The present invention relates to a kind of BMCH protocol data transceiver module, refer in particular between a kind of computing machine and the external unit module of carrying out data transmission through the BMCH agreement based on cpci bus.In military project control field, BMCH protocol data bus is widely used in carrying out between the inner important device of flight control computer and guided missile the occasion of big data quantity, high-speed telemetry intelligence (TELINT) transmission.Simultaneously, in fields such as the test of missile, emulation, need realize high-speed transfer, collection, storage and decoding between BMCH data and the computing machine through cpci bus again.The invention belongs to compunication, computer-aided test and field of automatic testing.
Background technology
PCI (Peripheral Components Interconnect) bus is a kind of standard 32-bit local bus that Intel Company releases; Frequency of operation 33MHz/66MHz; Transmission bandwidth is supported the plug and play characteristic up to the 133MB/266MB per second, and system can carry out resources allocation automatically to equipment; Simple to operate, use flexibly.These advantages make pci bus be highly suitable in supercomputing and the high-speed data communications field and use, and have become now and have used STD bus the most widely in the world.
CPCI (Compact PCI) bus is a kind of high performance bus technology based on the standard pci bus that PICMG (PCI Computer Manufacturer ' s Group, PCI industrial computer GPMA) proposes.Electric, compatible fully with the PCI standard in logic.The CPCI integrated circuit board adopts the Eurocard plug-in card physical construction that meets IEEE 1101.1 standards, has two kinds of moulding of 3U and 6U.The front panel of CPCI integrated circuit board comprises the EMC O-ring seal to reduce electromagnetic interference (EMI); Use meets IEC-1076 international standard high density air hermetic pin hole connector; The metal stitch of its 2mm has low induction reactance and impedance, thereby has reduced the signal reflex that the high speed cpci bus causes.All cpci bus electrical connecting wires all on the card extender of rear portion, therefore can need not line again when changing integrated circuit board, this just makes the plug of CPCI integrated circuit board have great durability; Integrated circuit board has guide rail and the support of front end fastener simultaneously, and card closely links to each other through the pin hole connector with slot, has very high impact resistance.Therefore, cpci bus has a wide range of applications in fields such as telecommunications, compunication, industry control test, Aero-Space.
BMCH (Bytes Multi-Channel; Being the byte hyperchannel) Data Transport Protocol is mainly used in the military project control field; Realize digital telemetry information between the inner important device of flight-control computer and guided missile big data quantity, high-speed, transmit for a long time, can detect the correctness of guided missile internal digital telemetry equipment through the BMCH Data Transport Protocol, the overall performance of guided missile is played a key effect; Therefore, obtained application more and more widely in current war production and field tests.The BMCH Data Transport Protocol is the full-duplex data transmission, can carry out independently data transmit-receive.Unidirectional employing 8 bit parallel address/data transmission modes, other has three road timing control signals, and protocol architecture is simple, and transmission speed is fast, contain much information, and has higher reliability.Therefore, develop a kind of high reliability, BMCH agreement transceiver module at a high speed, will play greatly facilitation the progress of war production and field tests.
But; In current BMCH protocol data transceiver module, on the one hand, because the BMCH protocol data amount between external unit and the computing machine is very big; Yet be subject to the read or write speed of computer bus; Therefore can't accomplish the continuous transmitting-receiving of data stream, only the configuration mass storage could be realized this function as buffering on transport module; On the other hand; Also there is not special-purpose BMCH protocol data transport module on the current market; Common implementation method is to adopt the transmission-receiving function of Digital I amount transceiver module simulation BMCH agreement; But need isolate conditioning to each road IO amount simultaneously, and the transmitting-receiving sequential of BMCH agreement be difficult to work good.Therefore, current BMCH data transmit-receive module is complex design, cost height not only, and is simultaneously functional relatively poor, is very easy to occur the phenomenon of frame losing under the occasion real-time at needs, that mass data is transmitted.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art, a kind of BMCH protocol data transceiver module based on the computing machine cpci bus is provided.This module is utilized fpga chip and signal conditioning circuit, realizes the data transmission standard of BMCH agreement; Employing meets the cpci bus of PICMG CompactPCI Specifications Rev1.0 standard and realizes the high speed data transfer between transceiver module and the computing machine; Support the 32-bit of accord with PCI Specification version 2.2 standards fully, 33MHzPCI bus electrical code.Final continuous, efficient, the stable transmission-receiving function of realizing the BMCH protocol data between external unit and the computing machine.
The present invention is a kind of BMCH protocol data transceiver module based on the computing machine cpci bus of exploitation, forms and comprises a hardware module and a FPGA module.
Wherein hardware module comprises:
1) an impedance control circuit plate comprises the electronic devices and components that are welded on this circuit board, has constituted kernal hardware circuit of the present invention jointly.The impedance control circuit plate is used for realizing that the present invention respectively forms the high speed of electric signal between the electronic devices and components, low-loss, short-distance transmission; Plurality of electronic elements on the described circuit board is used to realize each item logic function of the present invention, specifically comprises following five unit:
1. a FPGA unit is a hardware ingredient of the present invention, is the core cell of all electronic devices and components, and it uses fpga chip, is welded in the center of described impedance control circuit plate, is used to realize to the connection of other each component units and controls;
2. a cpci bus unit, its application of CPC I bridge chip is used for realizing with the FPGA unit matching data transmission of the present invention and cpci bus computing machine;
3. a BMCH agreement is sent the conditioning unit, adopts the output of high-performance triode array, is used for converting the data logical signal of FPGA unit output into BMCH agreement electric signal, improves the signal driving force;
4. a BMCH agreement receives the conditioning unit, adopts high speed photo coupling to receive BMCH agreement input electric signal, isolates converting the data logical signal into and being transferred to the FPGA unit;
5. an auxiliary circuit unit is realized power supply of the present invention, and configuration information is provided for segment chip.
2) a SCSI50 signal gang socket is welded in the left side edge of impedance control circuit plate, is used for the interface that provides BMCH protocol data bus of the present invention to be connected with external unit;
3) a standard C pci bus connector is welded in the edge, lower right of impedance control circuit plate, is used for providing the interface that is connected between cpci bus of the present invention and the computing machine backboard;
4) a standard 3U Eurocard integrated circuit board front panel is installed on the left side edge of impedance control circuit plate, is used to the present invention hardware protection is provided, and the installation of being convenient to integrated circuit board is with fixing, and plays electromagnetic shielding action;
The FPGA module comprises:
1) BMCH protocol data receiver module is used to receive the BMCH protocol data and is uploaded to the cpci bus computing machine;
2) BMCH protocol data sending module is used to receive the data that the cpci bus computing machine issues and sends the BMCH protocol data;
3) BMCH protocol data self-checking function module is used for the present invention self function is verified; It links to each other with the gang socket of described SCSI50 signal through an external SCSI50 self check plug.
Wherein, Described BMCH protocol data receiver module, its composition comprises: BMCH reception decoding submodule, a receiver address register, two BMCH Data Receiving buffer memory RAM, arbitration machines, interrupt sending a submodule and a cpci bus read operation submodule;
The 8-bit address value that receiver address register logger computer issues, recording interval are 00H～FFH, and this address value receives the unique foundation that whether stops as the BMCH protocol data;
BMCH receives the decoding submodule and receives BMCH agreement 8 bit parallel address/data multiplexed signalss, and is decoded as 8 bit address and 16 bit data;
Two BMCH Data Receiving buffer memory RAM are at in-built two storage spaces that size is 256 * 16-bit of FPGA, are used for BMCH is received the decoded BMCH data of the decoding submodule accessing operation of rattling, and realize the seamless transmission of data;
The arbitration machine is the comparison of the address that receives and receiver address register, if identical then the triggering interrupt sending submodule and cpci bus read operation submodule, with the data upload among two BMCH Data Receiving buffer memory RAM to computing machine.
Cpci bus read operation submodule through cooperating with the sequential of the electric signal of cpci bus unit, is realized DMA and bus Target slave unit reading dual mode, and the BMCH protocol data is uploaded to computing machine.
Wherein, described BMCH protocol data sending module, its composition comprises: BMCH data are sent buffer memory RAM, BMCH data are sent coding submodule, and sent an address register and a cpci bus write operation submodule;
Send the 16-bit address value that the address register logger computer issues, most-significant byte is for sending termination address, and least-significant byte is for sending start address, and the address value scope is 00H～FFH, as the start address and the termination address that send data block;
Cpci bus write operation submodule through cooperating with the sequential of the electric signal of cpci bus unit, is write several dual modes through DMA and bus Target slave unit data distributing to the described BMCH data of computing machine is sent among the buffer memory RAM;
It is to be 256 * 16-bit storage space in the in-built size of FPGA that the BMCH data are sent buffer memory RAM, is used for the address value and the data value of the BMCH protocol data that the storage computation machine issues;
The BMCH data are sent the coding submodule, and 8-bit address value and 16-bit data value that the BMCH data are sent BMCH data among the buffer memory RAM convert the 8 bit parallel address/data multiplexed signalss that meet the BMCH protocol specification into and send.
Wherein, this impedance control circuit plate integrated circuit board is a 3U Eurocard external form, is of a size of 160mm * 100mm; Thickness is 1.6mm, adopts the FR-4 material, 4 layers and above multilayer circuit board; Comprise a bus plane, a stratum and two signals layers, the characteristic impedance of single-ended signal transmission line is 50 Ω+10 Ω.
Each road cpci bus signal of this cpci bus unit one 10 terminal resistance of all will connecting, signal routing length remains in 1.5 inches, and clock line length remains in 2.5 ± 0.1 inches scopes.
Wherein, this auxiliary circuit unit is divided into level switch module, FPGA configuration module, CPCI module and four parts of reset circuit module:
Wherein, level switch module general+3.3V voltage is converted into+1.5V voltage, and is designed with decoupling capacitor at the input and output pin of power supply conversion chip.
Wherein, the FPGA configuration module has JTAG and two kinds of configuration modes of AS, and selects for use the EPCS4 chip as the EEPROM configuring chip under the AS pattern.
Wherein, the cpci bus configuration module selects for use eeprom chip that the cpci bus unit is carried out initial configuration, and the configuration information capacity is 22 double words.
Wherein, this SCSI50 signal gang socket, its double 50 needle sockets connect 22 of BMCH protocol data bus altogether and send signal wires, and 22 receive signal wires, and 3 ground wires and+5V power lead.
Wherein, this standard C pci bus connector adopts to meet IEC-1076 international standard high density air hermetic pin hole connector.
Wherein, this standard 3U Eurocard integrated circuit board front panel is connected with the impedance control circuit plate through two screws, and has the EMC O-ring seal.
A kind of BMCH protocol data transceiver module of the present invention based on the computing machine cpci bus; Its advantage and effect are: stable performance, reliability height; The continuous transmission of the BMCH protocol data of long-time, big data quantity can be carried out, reception, transmission and the self check of data can be realized; The cpci bus data transmission has the DMA function, and the bus actual transfer rate reaches as high as 80MB/s, and high-speed and continuous is transmitted not frame losing; BMCH bus signals driving force is strong, long transmission distance; The design of employing impedance Control, signal integrity and Electro Magnetic Compatibility are good; Simple in structure, cheap, easy to use.
Description of drawings
The present invention shown in Figure 1---based on the BMCH protocol data transceiver module of cpci bus;
Shown in Figure 2 is the PCB hierarchical design of the impedance control circuit plate among Fig. 1
Shown in Figure 3 is SCSI50 gang socket front elevation among Fig. 1
Shown in Figure 4 is cpci bus connector front elevation among Fig. 1
Shown in Figure 5 is 3U Eurocard integrated circuit board front panel side view among Fig. 1
Shown in Figure 6 is hardware global design block diagram of the present invention
Shown in Figure 7 is cpci bus unit design schematic diagram among Fig. 6
Shown in Figure 8 is that BMCH sends conditioning unit design figure among Fig. 6
Shown in Figure 9 is that BMCH receives conditioning unit design figure among Fig. 6
Shown in Figure 10 is auxiliary circuit design drawing among Fig. 6
Shown in Figure 11 is FPGA configuration module port definition among Figure 10
Shown in Figure 12 is that FPGA designs and develops theory diagram among the present invention
Shown in Figure 13ly be that the BMCH protocol data receives the decoding sequential chart
Local local bus read operation sequential chart when Figure 14 a, b are depicted as the cpci bus reading of data
Shown in Figure 15ly be that the BMCH protocol data sends the coding sequential chart
Local local bus write operation sequential chart when Figure 16 a, b are depicted as the cpci bus write data
Concrete label is following among the figure:
101 impedance control circuit plates, 102 plurality of electronic elements
103SCSI50 signal gang socket 104CPCI Bussing connector
1053U Eurocard integrated circuit board front panel 501 attachment screws
502 front panel fixation clamps 601FPGA unit
602CPCI bus unit 603BMCH agreement is sent the conditioning unit
The 604BMCH agreement receives conditioning 605 auxiliary circuit unit, unit
701CPCI bus end 702Local local bus end
1001 level switch module 1002FPGA configuration modules
1003CPCI bus configuration module 1004 reset circuit modules
The definition of 1101FPGA chip JTAG configured port definition 1102FPGA chip AS configured port
1201BMCH protocol data receiver module 1202BMCH protocol data sending module
1203CPCI bus Local local bus module 1204 Data Receiving spatial cache RAMA
1205 Data Receiving spatial cache RAMB, 1206 arbitration machines
1207 interrupt sending module 1208BMCH receives decoder module
1209 receiver address registers, 1210 data are sent spatial cache RAMC
1211BMCH sends coding module 1212 and sends address register
1213 self-checking function modules 1401 are from pattern monocycle read operation sequential
1402DMA read operation sequential 1601 is from pattern monocycle write operation sequential
1602DMA write operation sequential
Embodiment
Hardware of the present invention comprises an impedance control circuit plate 101, plurality of electronic elements 102, a SCSI50 signal gang socket 103, a standard C pci bus connector 104, a standard 3U Eurocard integrated circuit board front panel 105.
The present invention also comprises the fpga logic function development, and the setting of various configuration informations, finally realizes transmitting-receiving of BMCH protocol data and cpci bus operation.
Said impedance control circuit plate 101 adopts standard Eurocard physical construction, the 3U external form, and integrated circuit board is of a size of 160mm * 100mm, thickness 1.6mm.
Said impedance control circuit plate 101 adopts the making sheet of standard FR-4 material, 4 layers of PCB design, and ground floor (L1) is a signals layer 1, and the second layer (L2) is a ground plane, and the 3rd layer (L3) is bus plane, and the 4th layer (L4) is signals layer 2, each flaggy thickness is as shown in table 1 below.
| Level number | Type | Thickness (mils) |
| L1 | 0.60 | |
| Prepreg | 4.00 | |
| L2 | 1.20 | |
| Central layer | 51.4 | |
| L3 | 1.20 | |
| Prepreg | 4.00 | |
| L4 | 0.60 |
Table 1
For all signal lead of signals layer on the said impedance control circuit plate 101 1 and signals layer 2, its single-ended impedance is 50 Ω+10 Ω.
Said SCSI50 signal gang socket 103 has double 50 looper pins, is welded on said impedance control circuit plate 101 left side edge places, is used to connect BMCH protocol data transfer bus.
Said BMCH agreement respectively has 22 signal wires on physical electrical; Wherein 8 is data/address multiplex data line BMCH [7:0]; 3 are that byte judges and enable signal line C1, C2 and EN, and every signal wire has an accompaniment signal line (actual on the transceiver module+5V high level signal).Total data receiving and transmitting signal line all pass through the gang socket of SCSI50 signal and external unit interconnected.SCSI50 signal gang socket 103 interface definitions are as shown in table 2 below.
Table 2
Said cpci bus connector 104 adopts and meets IEC-1076 international standard high density air hermetic pin hole connector, and pin-pitch 2mm has 7 row, and 25 row pins are arranged.Said cpci bus connector 104 is welded on the edge, lower right of said impedance control circuit plate 101.Cpci bus connector 104 pinouts are as shown in table 3 below.
Table 3
Said 3U Eurocard integrated circuit board front panel 105 meets IEEE1101.1 and IEEE1101.10 standard, and front panel 105 has the EMC O-ring seal to reduce electromagnetic interference (EMI).Front panel 105 is fixed on said impedance control circuit plate left side edge through 2 attachment screws 501; Near said SCSI50 signal connector 103 1 sides; Be fixed on the slot of cpci bus computing machine through front panel fixation clamps 502 simultaneously, guarantee to install fastness.
Said plurality of electronic elements 102 all is welded on the said impedance control circuit plate, is divided into 5 unit according to function---and FPGA unit 601, cpci bus unit 602, BMCH send conditioning unit 603, BMCH receives conditioning unit 604 and auxiliary circuit unit 605.
Said FPGA unit 601 is selected the chip EP1C3T144 of the Cyclone I series of altera corp for use, uses the VerilogHDL programming development, realizes transmitting-receiving of BMCH protocol data and cpci bus operation.
Said cpci bus unit 602 is selected the cpci bus bridging chip PCI-9054 of PLX company for use.Be used for cooperating the data transmission of realization the present invention and cpci bus computing machine with FPGA unit 601; PCI-9054 bridging chip pin is divided into cpci bus end signal and Local local bus end signal two parts by logic function.
Said cpci bus end signal PCB layout meets PICMG CompactPCI specification version1.0 standard; Each road signal except that CLK, REQ#, GNT#, TDI, TDO, TCK, TMS and TRST signal one 10 Ω terminal resistance of all will connecting; To reduce the high speed signal reflection; Interconnected with the corresponding pin of said cpci bus connector afterwards, realize being connected with the physical electrical of cpci bus.Every signal line wiring length remains in 1.5 inches, and clock line length remains in 2.5 ± 0.1 inches scopes.
The IO pin of said Local local bus end signal and said FPGA unit EP1C3T144 chip is interconnected, and part signal connects outward and draws or pull down resistor.Local local bus end signal connection attribute is as shown in table 4 below.Pin programming through fpga chip cooperates generation Local local bus logical sequence, accomplishes the operation of each item cpci bus.
Table 4
The BMCH agreement is sent conditioning unit 603 and is adopted high-performance triode array chip HT251, is used for converting the data logical signal of FPGA unit output into BMCH agreement electrical signal, improves the driving force of BMCH signal.It is as shown in Figure 8 to send the conditioning unit.
The BMCH agreement receives conditioning unit 604 and adopts high speed photo coupling HP2630 chip, receives BMCH agreement input electric signal, isolates converting the data logical signal into and being transferred to the FPGA unit, guarantees the job security of receiver module.Each opto-coupler chip can carry out the conditioning of two-way input signal, and it is as shown in Figure 9 that the receiving signal science and engineering is made principle.
Said auxiliary circuit unit 605 comprises level switch module, FPGA configuration module, cpci bus configuration module and reset circuit module.
Said level switch module be used for come from said cpci bus connector 104+3.3V voltage is converted into+1.5V voltage.+ 3.3V voltage is used for to most components and parts power supplies, and+1.5V is used for the fpga chip core is supplied power.Select the LT1587CM1.5 level transferring chip for use.Level transferring chip+3.3V all is designed with decoupling capacitor, respectively comprises 1 10uF low frequency filtering electric capacity and 1 0.1uF high-frequency filter capacitor with+1.5V input and output pin.
Said reset circuit module 1004 is controlled by 1 SR, presses that to be that pin is put low, produces reset signal.
Said FPGA configuration module 1002 is used to realize that the program to FPGA unit 601 loads and on-line debugging.The FPGA configuration module is divided into JTAG and two kinds of patterns of AS.JTAG is the on-line debugging pattern, and it is promptly available to power on, but power down information then all loses, and it is as shown in the table for JTAG download port pinout; AS is the program Solidification pattern, uses the EEPROM save routine, and the FPGA power down is not lost, and the back FPGA that powers on can read configurator from EEPROM, and EEPROM selects the EPCS4 chip for use, and AS download port pinout is shown in figure 11.
Said cpci bus configuration module 1003 adopts 93C56 type eeprom chip, is used for the PCI-9054 bridging chip of said cpci bus unit 602 is configured.At first use special software that EEPROM is configured, after this when said cpci bus unit powers on, all can from EEPROM, read configuration information, self configuration register is rewritten, guaranteed the operate as normal of said cpci bus unit.EEPROM provides the configuration information of 22 double words (32-bit) altogether to the PCI-9054 chip.
Fpga logic function development among the present invention is mainly reflected in and uses Verilog HDL that fpga chip is programmed, and realizes the present invention---based on the overall logic function of the BMCH protocol data transceiver module of cpci bus.
BMCH protocol data transceiver module of the present invention can be realized three logic functions---Data Receiving, data are sent and the data self check.Also respectively corresponding these three functions of the functional development of fpga logic described in the present invention are divided into BMCH protocol data receiver module 1201 and BMCH protocol data sending module 1202, and are used through these two modules, realize data self-checking function 1213.
1) said BMCH protocol data receiver module 1201 principles
The present invention receives in the BMCH protocol data process; Outside BMCH protocol signal is through said SCSI50 signal gang socket 103 input BMCH agreement transceiver modules; The isolation that receives conditioning unit 604 through said BMCH is nursed one's health, and inputs to the BMCH data reception module 1201 of said FPGA unit 601.
The present invention can change the initial sum termination address of reception, and all stores the data that receive into computing machine, also can select to read the BMCH data of individual address.The realization of Data Receiving mainly is to rely on RAM 1204 and 1205, arbitration machine 1206, interruption sending module 1207 and the cpci bus read operation module 1203 that the in-built BMCH in FPGA unit 601 receive decoder modules 1208, receiver address register 1209, two buffer memory BMCH data.
The present invention is receiving after computing machine begins to receive instruction; The reception initial sum termination address that at first computing machine is issued deposits described receiver address register 1209 in; Subsequently the BMCH protocol data that receives is decoded, obtain the 8 bit address values and 16 bit data value of a BMCH agreement word.BMCH protocol data decoding sequential is shown in figure 13.
Said fpga chip internal structure two RAM that capacity is 256 * 16bits---RAMA (1204), RAMB (1205), can distinguish the BMCH protocol data of largest buffered one group address from 00 to FF.When beginning the reception of BMCH data, elder generation in RAMA, when the address value of the BMCH agreement word that receives equals the termination address in the said receiver address register 1209, triggers said arbitration machine 1206 to metadata cache.The duty of 1206 couples of two current RAM of arbitration machine is switched; Be that RAMB begins the BMCH data that buffer memory receives; And RAMA switches to wait host computer read states, and the arbitration machine triggers interrupt module simultaneously, and the notice computing machine reads data among the RAMA; So repeatable operation realizes the table tennis read-write capability.
After the look-at-me that the present invention produces was received by computing machine, computing machine can read the data in the RAM among the said FPGA through two kinds of reading modes of cpci bus, i.e. DMA pattern (1402) and bus Target slave unit reading pattern (1401).The realization of two kinds of cpci bus transmission modes all is to cooperate the sequential operation of CPCI bridging chip Local local bus end signal to accomplish through fpga chip.Said Local local bus read operation sequential chart is shown in Figure 14 a, b.
The present invention operates through above-described reception, just can realize to a large amount of BMCH protocol datas in real time, continuous acquisition and transmission.
2) said BMCH protocol data sending module principle
BMCH protocol data sending module is to send buffer memory ram space 1210, BMCH data transmission coding module 1211, transmission address register 1212 and cpci bus write operation module 1203 through the in-built data of FPGA to realize among the present invention.
The data that capacity of said FPGA internal structure is 256 * 16bits are sent buffer memory RAM---RAMC (1210); After computing machine is opened sending function; Computing machine at first writes described transmission metadata cache space RAMC through the frame BMCH data that cpci bus will send; Transmission initial sum termination address with these frame data writes said transmission address register 1212 simultaneously; Start BMCH subsequently and send coding module 1211,16 bit data value of each the BMCH word in the frame data and 8 bit address values are sent to the BMCH data with the data layout that meets the BMCH agreement send conditioning unit 603.It is as shown in the figure that the BMCH protocol data sends the coding sequential.
Computing machine can be write several modes through two kinds of cpci bus and deposit in the said transmission metadata cache ram space, and promptly DMA pattern 1602 is write digital modeling 1601 with bus Target slave unit.The realization of two kinds of cpci bus data WriteModes all is to accomplish through the sequential operation of FPGA unit matching CPCI bridging chip Local local bus end signal.Said Local local bus read operation sequential chart is shown in Figure 16 a, b.
The data that meet the BMCH agreement that BMCH protocol data sending module sends among the said FPGA are sent conditioning unit 603 by said BMCH data and are received; Conditioning through the triode array chip; Be converted into final BMCH agreement physical electrical signal, and export external unit to through said SCSI50 signal gang socket 103.
3) said BMCH protocol data self check 1213 principles
The present invention can be through said BMCH protocol data self-checking function checking transceiver module self performance.
Said self-checking function needs an external SCSI50 plug to be used in combination with said SCSI50 gang socket.The BMCH agreement transmitting-receiving pin of SCSI50 gang socket is connected one to one, form the transmitting-receiving loop.
In said self-checking function process; At first open the receiving function of BMCH protocol data receiver module; By computing machine timed sending multiframe BMCH data,, finally transmit back computing machine again via the transmission and the reception flow process of BMCH protocol data sending module and BMCH protocol data receiver module; Transceive data is compared then self check success of data consistent.
BMCH agreement transmitting-receiving sequential is shown in Figure 13, figure, and the retention time of each signal sequence is as shown in table 5 below among the figure.
| The input sign | Explanation | Maximum time | Minimum time |
| tcds | Input command Time Created | 25ns | |
| tcdh | The input command retention time | 25ns | |
| tenh | The enable signal retention time | 325ns | |
| tenuv | Enable signal ineffective time | 25ns | |
| taduv | Data or address ineffective time | 200ns | |
| tads | Data or address Time Created | 50ns | |
| tadh | Data or low address hold time | 25ns |
| tadd | Data or address time expand | 25ns | |
| Output identification | Explanation | Time | |
| t’cds | Output command Time Created | 250ns | |
| t’cdh | The output command retention time | 750ns | |
| t’enh | The output enable signal retention time | 750ns | |
| t’cduv | The output invalid command retention time | 1000ns | |
| t’adh | OPADD or data hold time | 1000ns | |
| t’aduv | The output invalid data retention time | 1000ns |
Table 5
Claims (8)
1. BMCH protocol data transceiver module based on cpci bus, it is characterized in that: its composition is divided into two parts-hardware module and FPGA module;
Wherein, the English full name of BMCH is Bytes Multi-Channel, i.e. the byte hyperchannel;
Hardware module comprises:
1) an impedance control circuit plate comprises the electronic devices and components that are welded on this circuit board, and this impedance control circuit plate specifically comprises following five unit:
1. a FPGA unit, it uses fpga chip, is welded in the center of described impedance control circuit plate, is used to realize to the connection of other each component units on the impedance control circuit plate and controls;
2. a cpci bus unit, its application of CPC I bridge chip is used for and the FPGA unit matching realizes the data transmission with the cpci bus computing machine;
3. a BMCH agreement is sent the conditioning unit, adopts the output of triode array, is used for converting the data logical signal of FPGA unit output into BMCH agreement electric signal;
4. a BMCH agreement receives the conditioning unit, adopts optocoupler to receive BMCH agreement input electric signal, isolates converting the data logical signal into and being transferred to the FPGA unit;
5. an auxiliary circuit unit provides power supply, and configuration information is provided for configuring chip;
2) a SCSI50 signal gang socket is welded on the impedance control circuit plate, is used to provide the BMCH protocol data interface that bus is connected with external unit;
3) a standard C pci bus connector is welded on the impedance control circuit plate, is used to provide the interface that is connected between cpci bus and the computing machine backboard;
4) a standard 3U Eurocard integrated circuit board front panel is installed on the impedance control circuit plate, is used to the impedance control circuit plate protection is provided, and the installation of being convenient to integrated circuit board is with fixing, and plays electromagnetic shielding action;
The FPGA module comprises:
1) BMCH protocol data receiver module is used to receive the BMCH protocol data and is uploaded to the cpci bus computing machine;
2) BMCH protocol data sending module is used to receive the data that the cpci bus computing machine issues and sends the BMCH protocol data;
3) BMCH protocol data self-checking function module, it links to each other with the gang socket of described SCSI50 signal through an external SCSI50 self check plug.
2. the BMCH protocol data transceiver module based on cpci bus according to claim 1; It is characterized in that: described BMCH protocol data receiver module, its composition comprises: BMCH reception decoding submodule, a receiver address register, two BMCH Data Receiving buffer memory RAM, arbitration machines, interrupt sending a submodule and a cpci bus read operation submodule;
The 8-bit address value that receiver address register logger computer issues, recording interval are 00H～FFH, and this address value receives the unique foundation that whether stops as the BMCH protocol data;
BMCH receives the decoding submodule and receives BMCH agreement 8 bit parallel address/data multiplexed signalss, and is decoded as 8 bit address and 16 bit data;
Two BMCH Data Receiving buffer memory RAM are at in-built two storage spaces that size is 256 * 16-bit of FPGA, are used for BMCH is received the decoded BMCH data of the decoding submodule accessing operation of rattling, and realize the seamless transmission of data;
The arbitration machine is the comparison of the address that receives and receiver address register, if identical then the triggering interrupt sending submodule and cpci bus read operation submodule, with the data upload among two BMCH Data Receiving buffer memory RAM to computing machine;
Cpci bus read operation submodule through cooperating with the sequential of the electric signal of cpci bus unit, is realized DMA and bus Target slave unit reading dual mode, and the BMCH protocol data is uploaded to computing machine.
3. the BMCH protocol data transceiver module based on cpci bus according to claim 1; It is characterized in that: described BMCH protocol data sending module, its composition comprises: BMCH data are sent buffer memory RAM, BMCH data are sent coding submodule, and sent an address register and a cpci bus write operation submodule;
Send the 16-bit address value that the address register logger computer issues, most-significant byte is for sending termination address, and least-significant byte is for sending start address, and the address value scope is 00H～FFH, as the start address and the termination address that send data block;
Cpci bus write operation submodule through cooperating with the sequential of the electric signal of cpci bus unit, is write several dual modes through DMA and bus Target slave unit data distributing to the described BMCH data of computing machine is sent among the buffer memory RAM;
It is to be 256 * 16-bit storage space in the in-built size of FPGA that the BMCH data are sent buffer memory RAM, is used for the address value and the data value of the BMCH protocol data that the storage computation machine issues;
The BMCH data are sent the coding submodule, and 8-bit address value and 16-bit data value that the BMCH data are sent BMCH data among the buffer memory RAM convert the 8 bit parallel address/data multiplexed signalss that meet the BMCH protocol specification into and send.
4. the BMCH protocol data transceiver module based on cpci bus according to claim 1; It is characterized in that: this impedance control circuit plate is a 3U Eurocard external form, is of a size of 160mm * 100mm, and thickness is 1.6mm; Adopt the FR-4 material; 4 layers and above multilayer circuit board comprise a bus plane, a stratum and two signals layers, and the characteristic impedance of single-ended signal transmission line is 50 Ω ± 10 Ω.
5. the BMCH protocol data transceiver module based on cpci bus according to claim 1; It is characterized in that: each road cpci bus signal of this cpci bus unit one 10 Ω terminal resistance of all will connecting; Signal routing length remains in 1.5 inches, and clock line length remains in 2.5 ± 0.1 inches scopes.
6. the BMCH protocol data transceiver module based on cpci bus according to claim 1 is characterized in that: this auxiliary circuit unit is divided into level switch module, FPGA configuration module, cpci bus configuration module and four parts of reset circuit module:
Level switch module general+3.3V voltage is converted into+1.5V voltage, and is designed with decoupling capacitor at the input and output pin of power supply conversion chip;
The FPGA configuration module has JTAG and two kinds of configuration modes of AS, and selects for use the EPCS4 chip as the EEPROM configuring chip under the AS pattern;
The cpci bus configuration module selects for use eeprom chip that the cpci bus unit is carried out initial configuration, and the configuration information capacity is 22 double words.
7. the BMCH protocol data transceiver module based on cpci bus according to claim 1; It is characterized in that: this SCSI50 signal gang socket; Its double 50 needle sockets connect 22 transmission signal wires of BMCH protocol data bus altogether; 22 receive signal wires, and 3 ground wires and+5V power lead.
8. the BMCH protocol data transceiver module based on cpci bus according to claim 1 is characterized in that: this standard 3U Eurocard integrated circuit board front panel is connected with the impedance control circuit plate through two screws, and has the EMC O-ring seal.
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| CN103425615B (en) * | 2013-07-31 | 2016-07-13 | 中国人民解放军海军装备研究院信息工程技术研究所 | Three-channel data sends adapter |
| CN104579885B (en) * | 2015-02-05 | 2016-03-23 | 中车青岛四方车辆研究所有限公司 | The protocol converter of cpci bus and isa bus and conversion method |
| CN104899341A (en) * | 2015-05-28 | 2015-09-09 | 西北工业大学 | FPGA based high-speed PCI acquisition card adopting embedded optional filtering algorithm |
| CN105068956A (en) * | 2015-08-04 | 2015-11-18 | 西北工业大学 | Field programmable gate array (FPGA) based high-speed peripheral component interconnect (PCI) data acquisition card with inset USB debugging module |
| CN113721729A (en) * | 2017-03-28 | 2021-11-30 | 上海山里智能科技有限公司 | Integrated computing system |
| CN109117289B (en) * | 2018-08-15 | 2022-02-22 | 英业达科技有限公司 | Server system and method for managing dual-substrate management controller |
| CN110134622B (en) * | 2019-05-07 | 2022-11-11 | 电子科技大学 | Data interaction system of data acquisition module and data transmission module |
| CN110635985A (en) * | 2019-11-13 | 2019-12-31 | 天津津航计算技术研究所 | FlexRay-CPCIe communication module |
| CN112463660A (en) * | 2020-12-11 | 2021-03-09 | 北京航天自动控制研究所 | Multifunctional real-time interaction system based on CPCI bus |
| CN113960857B (en) * | 2021-10-29 | 2023-05-12 | 歌尔光学科技有限公司 | DMD circuit board and DLP light machine module |
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