CN202975317U - Reconstructed FPGA radar digital signal processing assembly - Google Patents
Reconstructed FPGA radar digital signal processing assembly Download PDFInfo
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- CN202975317U CN202975317U CN 201220742095 CN201220742095U CN202975317U CN 202975317 U CN202975317 U CN 202975317U CN 201220742095 CN201220742095 CN 201220742095 CN 201220742095 U CN201220742095 U CN 201220742095U CN 202975317 U CN202975317 U CN 202975317U
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Abstract
The utility model discloses a reconstructed FPGA radar digital signal processing assembly. The reconstructed FPGA radar digital signal processing assembly belongs to the technical field of digital signal processing. According to the reconstructed FPGA radar digital signal processing assembly of the utility model, through a fixed FPGA arithmetic unit and rich fixed peripheral interface modes, and with the cooperation of a kind of uniform customizable flexible peripheral interface mode, a multi-field general high-performance digital signal processing hardware platform is realized under the requirements of communication, radar, satellite, image processing, remote sensing surveying and mapping, and seismic and geological signal analysis as well marine and meteorological signals analysis and other intensive high-bandwidth digital signal processing.
Description
Technical field
The utility model relates in the process field of radar digital signal, particularly reconstruct FPGA radar digital signal processing assembly.
Background technology
Along with the high speed development of computing machine and infotech, Digital Signal Processing arises at the historic moment and development rapidly thereupon.The Digital Signal Processing fields such as infiltrating into communication, radar, satellite, image processing, remote sensing mapping, seismogeology signal analysis, ocean and meteorologic signal analysis that has wide range of applications.In front field of digital signals practical application, more and more wider also more and more higher for performances such as the concurrency of disposal system, arithmetic speed, processing bandwidth, algorithm flexibility ratios.Only the way take the dominant frequency that improves the disposal system arithmetic element as means more and more can not satisfy processing requirements.Different field is numerous for the real needs of digital information processing system, and in present field, special-purpose digital information processing system only can satisfy the demand in special-purpose field mostly, has no idea to accomplish the agile and all-purpose demand that satisfies most fields.The versatility of signal processing platform and dirigibility become of crucial importance.For example, at present in the field of general radar signal simulation and processing, in typical signal processor hardware configuration (as shown in Figure 1), can formulate concrete signal processor index according to system, mode of operation, application scenario and the demand of a radar, and select ADC, DAC, storer, processor (as the FPGA/DSP) chip that satisfies the demands according to index, then carry out the hardware research and development according to chip, the module device selected.The hardware research and development are comparatively very long parts of time in whole performance history, and from principle diagram design, PCB is designed into plate-making and arrives the welding debugging again, generally needs three months time to half a year depending on complexity.After the processor research and development are completed, generally can only satisfy system identical, mode of operation is close, and the similar radar of application scenario and demand uses.Such signal processor performance is high, but needs to go specially development for different radars or occasion, causes the R﹠D cycle to lengthen, and it is large that R﹠D risk becomes.Thereby can not satisfy the new demand of signal process field.
Realize in the utility model process the inventor, finding has following defective in prior art, in prior art.In the field of general radar signal simulation and processing, in typical signal processor hardware configuration, can formulate concrete signal processor index according to system, mode of operation, application scenario and the demand of a radar, and select ADC, DAC, storer, processor (as the FPGA/DSP) chip that satisfies the demands according to index, thereby in system's actual needs adjustment and when needing to expand on function, to again adjust the system hardware layout, can not satisfy the needs of signal process field development.
The utility model content
For defective of the prior art, the utility model has solved that existing FPGA radar digital signal processing device can not be expanded and the problem of reconstruct.
Provide reconstruct FPGA radar digital signal processing assembly in order to solve above technical matters the utility model, specifically comprise: motherboard and subcard, configuration FPGA and docking station on described motherboard, this FPGA comprises: radar signal processing unit and interface module, and described interface module defines consistent and is connected with described docking station with the digital interface of described radar signal processing unit; Described subcard comprises: the radar signal processing unit subcard, the interface definition of this subcard is identical with described docking station definition.
Compared with prior art, the utility model embodiment has following several respects advantage:
1. what the utility model was related is a kind of general signal processing platform based on FPGA and plug-in unit reconfiguration technique.Platform has adopted high performance FPGA arithmetic element and flexible reconfigurable system architecture.When possessing powerful digital signal processing capability, satisfying various fields signal processing algorithm complexity and requirement of real-time, can build flexibly again the digital information processing system in different field.Do not need signal processing demands in different fields is carried out independent system development exploitation, shorten system development cycle.
2. reconstruct connector interface has adopted EMIF, DDR2, DDR3, QDR, RocketIO, and GTP, the high speed interfacings such as PCI-E have increased substantially the exchanges data bandwidth.
3. the system architecture of reconstruct can flexmux except hardware platform, and the interface programming of FPGA inside equally also can corresponding flexmux, and system development and maintenance cost can significantly reduce.
4. the utility model has defined a kind of general recombination function interface specification, and the interface routine of FPGA can be realized with the algorithm development of FPGA relatively independent, has improved the portability of signal processing algorithm.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1: the schematic diagram that is the existing FPGA radar digital signal processing system of the utility model;
Fig. 2: the composition schematic diagram that is a kind of reconstruct FPGA of the utility model radar digital signal processing assembly;
Fig. 3: the composition schematic diagram that is another kind of reconstruct FPGA radar digital signal processing assembly in the utility model;
Fig. 4: be the composition schematic diagram that in the utility model, reconstruct FPGA radar digital signal processing assembly comprises the double FPGA device;
Fig. 5: be that in the utility model, reconstruct FPGA radar digital signal processing assembly comprises that the another kind of double FPGA device forms schematic diagram.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obvious described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
Reconstruct FPGA radar digital signal processing assembly is provided in the utility model embodiment, as shown in Figure 2,
Reconstruct FPGA radar digital signal processing assembly, comprise: motherboard 11 and subcard 12, configuration FPGA13 and docking station 14 on described motherboard 11, this FPGA comprises: radar signal processing unit 131 and interface module 132, and described interface module 132 defines consistent and is connected with described docking station with the digital interface of described radar signal processing unit 131; Described subcard 12 is radar signal processing unit subcard 121, and the interface definition of this subcard is identical with described docking station definition.Described FPGA also comprises: storage unit 133, communication unit 134.Described docking station 14 comprises: a plurality of interface modules 14, described a plurality of interface modules 14 define consistent and are connected respectively with a plurality of docking stations with the digital interface of described storage unit 133 and described communication unit 134 respectively; Described subcard comprises: storage unit subcard 123 and communication unit subcard 122, the interface definition of described storage unit subcard 123 and communication unit subcard 122 is identical with described docking station definition.Need to prove that in the utility model, each unit module of FPGA is the hardware language unit module, is realize and burn the hardware cell module that realizes to solidifying in FPGA by hardware language.
as another preferred version in the present embodiment, as shown in Figure 3, also can be designed as independent docking station and independent interface module, thereby above-mentioned independent docking station is with interface module can be from being complementary with described a plurality of subcards separately according to actual needs, described independent interface module 132 comprises: switch unit 1321 and current interface unit 1322, described current interface unit 1322 comprises: described radar signal processing unit 131, storage unit 133, the data-interface type of communication unit 134, described switch unit 1321 is according to the subcard validation of information subcard type that powers on, from described radar signal processing unit 131, confirm the current interface type of described interface module 1322 in storage unit 133 or communication unit 134, above-mentioned identifying can realize by the interface definition that powers on of subcard, as radar signal processing unit subcard 121, the pin that powers on approximately can be decided to be number one or first and second number pin, other unit subcard approximately is decided to be other pin simultaneously, thereby realize the identification to above-mentioned a plurality of subcards, or by to the agreement of several pins wherein, forming key word identifies the unit subcard, described subcard comprises: radar signal processing unit subcard 121, storage unit subcard 123 and communication unit subcard 122, the interface of described subcard is corresponding with described docking station, the information that the powers on difference of described different subcards.Also configure power supply on described motherboard 11 and process distribution module 15 and clock distribution module 16.
A kind of preferred version as the present embodiment, for treating apparatus can in time be dispelled the heat, described motherboard 11 also comprises: heat dissipation cold plate, described heat dissipation cold plate are fixedly connected on the device-side of described motherboard 11 by a plurality of support columns, and 11 of described heat dissipation cold plate and described motherboards are filled silicone grease.
As shown in Figure 4, the Ben Leida treating apparatus comprises a hardware motherboard HQGF-CPCI-V4.Settle power supply to process distribution module on the hardware motherboard; The clock distribution module is set on the hardware motherboard; The hardware motherboard arranges main arithmetic element FPGA13 process chip and association's process chip 147; FPGA13 is connected by bus and realizes control information and data interaction with association process chip 147; The hardware motherboard arranges restructural expanded function connector 141,142 and is connected at a high speed with FPGA13 and realizes data interaction; The hardware motherboard arrange restructural extension storage connector 144 be connected at a high speed with FPGA13 and realize the storage data interaction; The hardware motherboard arranges multi-platform isomorphism connector 143 and is connected at a high speed with FPGA13.Can also comprise simultaneously association's processing unit 147 on the basis that comprises FPGA master's arithmetic element, two restructural expanded function connectors 141,142, a restructural extension storage connector 144, reset switch, plate carries storer, Ethernet interface, the JTAG debugger interface, serial ports, pci bus interface.Described motherboard is the CPCI-6U normal structure, and power supply is processed distribution module 15 and is responsible for the required power supply of all devices on distribution plate.Harmonizing processor chip 147 and FPGA process chip 13, Ethernet interface, plate carry dynamic RAM, plate and carry nonvolatile memory, JTAG debugging interface, serial ports, pci bus interface and be connected.Above-mentioned FPGA master's arithmetic element 13 and association's processing unit 147 can be two or more.Use simultaneously the high-speed link interface to connect between above-mentioned fpga core arithmetic element, thereby satisfy the needs of supercomputing.Also can comprise for easy to assembly on above-mentioned motherboard: fixed orifice, register pin, driver-extractor, locking device.Described register pin, driver-extractor, locking device is fixed on integrated circuit board by fixed orifice.
This device has adopted the motherboard of fixedly processing core and reconfigurable system structure that the function daughter board of customization/the storage daughter board is combined by connector.The daughter board connector adopts the solid and reliable product of high speed, and assurance can realize high speed data transfer with motherboard, and the function daughter board can design according to practical application request, include but not limited to all kinds of high-speed ADCs, DAC, DRFM, optical communication, large capacity NAND-FLASH, the function daughter boards such as high-speed DRAM.Motherboard has fixing one or more high performance programmable FPGA signal computing units.Each arithmetic element comprises a slice High Performance FPGA.Motherboard also has fixing coprocessor, completes configuration and the control of integrated circuit board arithmetic element information, and management and the data transmission of the basic interfaces such as reset switch, Ethernet, serial ports, PCI.Be connected by the high-speed communication interface agreement between coprocessor and FPGA and carry out data interaction.Motherboard high speed connector directly connects motherboard FPGA, realizes EMIF by FPGA, DDR2, DDR3, QDR, RocketIO, and GTP, the high-speed interface that PCI-E etc. are abundant enriches reconfigurable daughter board type and daughter board function.Reach the unitized purpose of design of platform.High speed connector type is divided into three kinds, function subcard connector, storage subcard connector, multi-platform isomorphism communication connector.Different connectors is for different linked objects.Function subcard connector is mainly used in the Various types of data collection, the subcard of data readback or data communication function type; Storage subcard connector is mainly used in the memory cards such as all kinds of FLASH/DRAM; Multi-platform isomorphism communication connector is to be applied to the data communication of the parallel isomorphism of the many integrated circuit boards of this platform interconnected the time.Function subcard connector and storage subcard connector can patch different subcards; And multi-platform isomorphism communication connector is only interconnected for many integrated circuit boards isomorphism of this platform.For the different function subcard of motherboard access, the utility model has also comprised the daughtercard interface program of developing under the corresponding difference in functionality subcard of FPGA, and the daughtercard interface program is corresponding with subcard.The developer can directly select according to the function subcard of current platform configuration in the time of exploitation fpga logic algorithm, need not again to develop.Be provided with the clock distribution module on motherboard, the clock distribution module has a plurality of input modes: 1. by motherboard clock input port; 2. by the input of recombination function subcard connector; 3. carrying the clock generating chip by plate produces.The clock distribution module controls by source selection flexibly and power division is selected to control, the processing clock of selecting the FPGA signal computing unit to use.The clock distribution module can satisfy platform demand for clock synchronous in the signal process field of the needs modulus/digital-to-analog conversions such as radar.For example, use based on a typical case of the present utility model.The research staff obtains the manufacture claim of a radar signals processor, first formulates concrete processor index according to system, mode of operation, application scenario and the demand of a radar.Then select according to different application systems and index demand the ADC that satisfies index, then DAC or memory card module with daughter card module and the motherboard combination of correspondence, consist of the processor prototype fast.The developer can skip principle diagram design, PCB making sheet, weld is the part of hardware debug, directly enters fpga logic algorithm design part, has greatly shortened the hardware R﹠D cycle.When change occurs the development demand, can adjust hardware platform by the subcard that the New Set demand is satisfied in direct replacing, to adapt to the variation of more wide in range radar system, mode of operation and application scenario.
As shown in Figure 5, QPLAT is applied to Simulated Radar Signal Generator based on the utility model common hardware device, comprise CPCI cabinet 151, general-purpose platform motherboard 152, high-speed ADC function daughter board 153, high-speed DAC function daughter board 154, large capacity NAND-FLASH storage daughter board 155, Ethernet cable and supervisory control comuter.
QPLAT has a FPGA arithmetic element 152, selects the virtex6 series SX315T model high-performance FPGA of xilinx company; Coprocessor 156 selects the virtex5 series LX50T model high-performance FPGA of xilinx company to build, and has been equipped with simultaneously 64MB; QPLAT carries two function subcards, is respectively 1.5G high-speed ADC 153 and 1.5G high-speed DAC 154; QPLAT carries a storage subcard SLC-32G NAND-FLASH155, and subcard has the access bandwidth of 32GB memory capacity and 800MB/s; QPLAT has used gigabit ethernet interface, by the external inspecting computing machine, QPLAT is carried out Monitoring and Controlling.
Be connected by standard 802.11 Ethernet protocols between coprocessor 156 and gigabit Ethernet; Coprocessor 156 is connected by Standard PC I agreement with CPCI cabinet 151; Coprocessor 156 is connected with self-defining LINK high speed protocol with FPGA arithmetic element 152;
FPGA arithmetic element 152 all is connected by the serdes host-host protocol with high-speed ADC interface subcard and high-speed DAC interface subcard.The high speed data transfer that ADC153 arrives Collect conversion is to FPGA arithmetic element 152; FPGA unit 152 with the high speed data transfer handled well to DAC154.
FPGA arithmetic element 152 is connected by common I/O Parallel agreement with SLC-32G NAND-FLASH subcard 155.SLC-32G NAND-FLASH subcard 155 can storage system gather the data obtained from ADC153, also can store the supervisory control comuter initialize data and offer the use of radar target simulation algorithm.
In order to satisfy the general radar signal simulation demand of different system different modes, QPLAT can pass through to change the function subcard of the different numbers of channels of different bandwidth, and changes larger or storage subcard more low capacity according to the data volume demand.
Through the above description of the embodiments, those skilled in the art can be well understood to the utility model and can realize by hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding, the technical solution of the utility model can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the utility model.
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the module in accompanying drawing or flow process might not be that enforcement the utility model is necessary.
It will be appreciated by those skilled in the art that the module in the device in embodiment can be distributed in the device of embodiment according to the embodiment description, also can carry out respective change and be arranged in the one or more devices that are different from the present embodiment.The module of above-described embodiment can be merged into a module, also can further split into a plurality of submodules.
Above-mentioned the utility model embodiment sequence number does not represent the quality of embodiment just to description.
Above disclosed be only several specific embodiment of the present utility model, still, the utility model is not limited thereto, the changes that any person skilled in the art can think of all should fall into protection domain of the present utility model.
Claims (6)
1. reconstruct FPGA radar digital signal processing assembly, it is characterized in that, comprise: motherboard and subcard, configuration FPGA and docking station on described motherboard, this FPGA comprises: radar signal processing unit and interface module, and described interface module defines consistent and is connected with described docking station with the digital interface of described radar signal processing unit; Described subcard comprises: the radar signal processing unit subcard, the interface definition of this subcard is identical with described docking station definition.
2. processing components as described in claim 1, is characterized in that, described FPGA also comprises: storage unit, communication unit.
3. processing components as described in claim 2, it is characterized in that, described docking station comprises: a plurality of interface modules, described a plurality of interface modules define consistent and are connected respectively with a plurality of docking stations with the digital interface of described storage unit and described communication unit respectively; Described subcard comprises: storage unit subcard and communication unit subcard, the interface definition of described storage unit subcard and communication unit subcard is identical with described docking station definition.
4. processing components as described in claim 2, it is characterized in that, described docking station and described interface module are independent docking station and described independent interface module, described independent interface module comprises: switch unit and current interface unit, described current interface unit comprises: the data-interface type of described radar signal processing unit, storage unit, communication unit, described switch unit is confirmed the current interface type of described interface module according to the subcard validation of information subcard type that powers on from described radar signal processing unit, storage unit or communication unit; Described subcard comprises: radar signal processing unit subcard, storage unit subcard and communication unit subcard, the interface of described subcard is corresponding with described docking station, the information that the powers on difference of described different subcards.
5. processing components as described in claim 1, is characterized in that, also configures power supply on described motherboard and process on distribution module and hardware support plate the clock distribution module is set.
6. processing components as described in claim 1, is characterized in that, described motherboard also comprises: heat dissipation cold plate, described heat dissipation cold plate are fixedly connected on the device-side of described motherboard by a plurality of support columns, fill silicone grease between described heat dissipation cold plate and described motherboard.
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| CN 201220742095 CN202975317U (en) | 2012-12-28 | 2012-12-28 | Reconstructed FPGA radar digital signal processing assembly |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103901402A (en) * | 2012-12-28 | 2014-07-02 | 北京华清瑞达科技有限公司 | Reconstructed FPGA radar digital signal processing assembly and reconstructed FPGA radar digital signal processing method |
| CN105786620A (en) * | 2016-02-25 | 2016-07-20 | 电子科技大学 | Integrated reconfigurable summarized information processing loading system |
| CN107202977A (en) * | 2017-05-10 | 2017-09-26 | 湖北航天技术研究院总体设计所 | A kind of total system and software design approach based on VPX platforms |
-
2012
- 2012-12-28 CN CN 201220742095 patent/CN202975317U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103901402A (en) * | 2012-12-28 | 2014-07-02 | 北京华清瑞达科技有限公司 | Reconstructed FPGA radar digital signal processing assembly and reconstructed FPGA radar digital signal processing method |
| CN103901402B (en) * | 2012-12-28 | 2016-06-29 | 北京华清瑞达科技有限公司 | Reconstruct FPGA radar digital signal processing assembly and method |
| CN105786620A (en) * | 2016-02-25 | 2016-07-20 | 电子科技大学 | Integrated reconfigurable summarized information processing loading system |
| CN105786620B (en) * | 2016-02-25 | 2019-03-01 | 电子科技大学 | The restructural integrated information of integration handles load system |
| CN107202977A (en) * | 2017-05-10 | 2017-09-26 | 湖北航天技术研究院总体设计所 | A kind of total system and software design approach based on VPX platforms |
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Granted publication date: 20130605 |