CN116680220B - Signal transceiver and signal receiving and transmitting system - Google Patents
Signal transceiver and signal receiving and transmitting system Download PDFInfo
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- CN116680220B CN116680220B CN202310662181.3A CN202310662181A CN116680220B CN 116680220 B CN116680220 B CN 116680220B CN 202310662181 A CN202310662181 A CN 202310662181A CN 116680220 B CN116680220 B CN 116680220B
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- 230000006870 function Effects 0.000 claims abstract description 77
- 238000006243 chemical reaction Methods 0.000 claims abstract description 75
- 238000004891 communication Methods 0.000 claims abstract description 53
- 238000012545 processing Methods 0.000 claims abstract description 53
- 238000011144 upstream manufacturing Methods 0.000 claims description 31
- 230000017525 heat dissipation Effects 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 9
- 230000006978 adaptation Effects 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 47
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 15
- 238000011161 development Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000004806 packaging method and process Methods 0.000 description 8
- 230000006872 improvement Effects 0.000 description 5
- 230000003993 interaction Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000009131 signaling function Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a signal transceiver and a signal transceiver system, and relates to the technical field of signal transceiver. The signal transceiver comprises a high-speed interface conversion circuit and a signal transceiver function circuit, wherein the high-speed interface conversion circuit comprises an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, the uplink lightning interface is used for being connected with a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used for being connected with a cascaded next signal transceiver, the signal transceiver function circuit comprises a second bus connector, a communication interconnection module and a signal transceiver function front end module, and through the design of the connection relation of the second bus connector, the communication interconnection module and the signal transceiver function front end module, the centralized chassis back plate data transmission bus of a traditional bus type instrument system can be improved into the high-speed interface conversion circuit of each cascaded signal transceiver, so that the signal transceiver comprising the circuit can simultaneously meet the characteristics of ultra-portability, high performance, low cost, multiple functions, expandability and the like.
Description
Technical Field
The invention belongs to the technical field of signal transceiving, and particularly relates to a signal transceiver and a signal transceiving system.
Background
With the rapid development of analog circuits, digital circuits, and signal processing technologies, there is an increasing demand for broadband radio frequency signal measurement, analysis, processing, and generation. In many industries and applications, broadband radio frequency signal collection, analysis, processing and generation, such as wireless communication, satellite communication, navigation, electronic countermeasure, intelligent driving and weather prediction, etc., are involved, and a large amount of experiments or measurements are required to be carried out outdoor, and the amount of signal data required to be collected, analyzed, processed or generated by the applications is very large, so that users need high-performance signal receiving and processing capability, portability, functionality and expandability, and meanwhile, the requirement of cost reduction is also very strong because of large usage. The design of an ultra lightweight, high performance, low cost, multi-functional and scalable signal transceiver would thus be a great aid to such applications.
Currently on the market, signal transceivers with high performance, multifunction and expandable characteristics are mainly bus-type instrumentation systems, their main bus architecture being PXIE (PeripheralComponentInterconnectionextensionsfor InstrumentationExpress, optimized version of the peripheral component interconnect expansion towards the instrumentation system), AXIE (Advanced eXtensibleInterfaceExpress, optimized version of a bus protocol), VPX (new generation high-speed serial bus standard proposed by VME international trade association, VITA, 2007 on the basis of its VME bus) and LXI (LAN-based eXtensionsforInstrumentation, instrumentation expansion of a local area network), etc.
The three types of instrument bus architectures, namely PXIE, AXIE and VPX, are all based on PCIE (PeripheralComponent InterconnectExpress), which is a high-speed serial computer expansion bus standard, originally named "3GIO", proposed by intel in 2001, and are designed to replace the old PCI, PCI-X and AGP bus standards) buses to expand instrument functions, so that a special system chassis and system controller are required. The system case provides the functions of a bus backboard, a system power supply, system heat dissipation, structure fixation and the like; and the system controller provides functions of system control, man-machine interaction, signal processing, data storage, peripheral connection and the like. The system chassis and the system controller provide excellent performance for the system based on PCIE buses and advanced computer technology, but are also specially customized and designed, so that the cost is high, and the cost is often more than half of the cost of the whole system under the condition of less number of system functional modules.
The LXI instrument bus architecture is built based on ethernet-based extended instrument functions, and most products are evolved from the addition of ethernet and synchronous interfaces to conventional desktop instruments. Because of the limitations of ethernet characteristics, LXI systems have difficulty meeting the data transfer rates and bus delays required for broadband signal transceivers. In addition, the LXI equipment architecture adopts a built-in special signal analysis processing, storage and man-machine interaction functional module, so that the cost cannot be effectively reduced, and meanwhile, the signal analysis processing capacity of the system is fixed after leaving the factory, so that the continuous function and performance upgrading are difficult to realize.
In addition, the foregoing PXIE, AXIE, VPX and LXI instruments are generally similar to conventional commercial servers in volume and weight due to their complex composition and structure, i.e., generally weighing 10kg or more, making portability difficult.
In summary, the existing signal transceiver constructed based on the bus type instrument system has the characteristics of high performance, multifunction and expandability, but the problems of high cost and insufficient portability generally exist, so that the existing broadband signal transceiver capable of simultaneously meeting the characteristics of ultra portability, high performance, low cost, multifunction, expandability and the like is still lacking in the market.
Disclosure of Invention
The invention aims to provide a novel signal transceiver and a signal transceiver system, which are used for solving the problems of high cost and insufficient portability of the existing signal transceiver constructed based on a bus type instrument system, so as to provide a broadband signal transceiver capable of simultaneously meeting the characteristics of ultra portability, high performance, low cost, multiple functions, expandability and the like.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect, a signal transceiver is provided, including a high-speed interface conversion circuit and a signal transceiver function circuit, where the high-speed interface conversion circuit includes an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, where the uplink lightning interface is used to connect with a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used to connect with a cascaded next signal transceiver, and the signal transceiver function circuit includes a second bus connector, a communication interconnection module and a signal transceiver function front end module used to complete a local signal transceiver front end task;
The uplink lightning interface is connected with the uplink lightning channel of the lightning controller, and the downlink lightning interface is connected with the downlink lightning channel of the lightning controller, so that the uplink and downlink equipment is connected with the lightning controller in a cascade manner through the two lightning interfaces;
the downlink PCIE channel of the lightning controller is connected with the first bus type connector, the first bus type connector is connected with the second bus type connector, the lightning controller is used for realizing conversion adaptation of a lightning interface and a PCIE bus, and PCIE protocol-based data communication is performed between the high-speed interface conversion circuit and the signal receiving and transmitting functional circuit through the first bus type connector and the second bus type connector;
the communication interconnection module is respectively connected with the second bus type connector and the signal receiving and transmitting function front end module so as to realize data communication interconnection between the second bus type connector and the signal receiving and transmitting function front end module.
Based on the above summary, a new scheme of a signal transceiver circuit based on a lightning interface is provided, that is, the signal transceiver circuit includes a high-speed interface conversion circuit and a signal transceiver function circuit, where the high-speed interface conversion circuit includes an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, where the uplink lightning interface is used to connect a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used to connect a cascaded next signal transceiver, and the signal transceiver function circuit includes a second bus connector, a communication interconnection module and a signal transceiver function front end module for completing a front end task of the signal transceiver, and by designing a connection relationship between them, the centralized chassis back plate data transmission bus of a traditional bus instrument system can be improved to a high-speed interface conversion circuit of each cascaded signal transceiver, so that the signal transceiver including the high-speed interface conversion circuit can simultaneously meet the characteristics of super-performance, low-cost, light and multi-functional and expandable, and further can facilitate the realization of an improvement of a "system controller+signal transceiver+a commercial system of a traditional bus instrument system into a cascade architecture and a more than the practical transceiver.
In one possible design, the lightning protection device further comprises a first USB port controller, wherein the first USB port controller is respectively connected with the USB physical interface of the upstream lightning interface and the lightning controller, so as to realize power supply control and cable detection based on the USB physical interface.
In one possible design, the lightning protection device further comprises a second USB port controller, wherein the second USB port controller is respectively connected with the USB physical interface of the downlink lightning interface and the lightning controller, so that the USB physical interface of the downlink lightning interface and the second USB port controller cooperate to realize downlink lightning cascade connection.
In one possible design, the lightning protection device further comprises a USB port multiplexer, wherein the USB port multiplexer is respectively connected with the USB physical interface of the uplink lightning interface, the lightning controller and the USB physical interface of the downlink lightning interface, so as to realize the communication connection between the lightning controller and the lightning interfaces of the uplink and downlink devices.
In one possible design, the lightning controller further comprises a two-way PCIE clock generator, wherein the two-way PCIE clock generator is used to connect the first bus connector in cooperation with a downlink PCIE channel of the lightning controller.
In one possible design, the downlink USB channel of the lightning controller is also connected to the first bus connector, and the lightning controller is further configured to implement conversion adaptation between a lightning interface and a USB bus, so that local signal transceiving based on a USB protocol is further performed between the high-speed interface conversion circuit and the signal transceiving functional circuit through the first bus connector and the second bus connector.
In one possible design, the high-speed interface conversion circuit further comprises a power supply module and/or a storage module;
the power module is connected with the USB physical interface of the uplink lightning interface, and is used for taking electricity through the USB physical interface and supplying power to the high-speed interface conversion circuit;
the storage module is connected with the lightning controller and used for storing a function configuration program of the lightning controller.
In one possible design, the first bus connector and the second bus connector mutually employ a connector that is a golden finger terminal and a connector that is a socket terminal, so that a daughter board for arranging the high-speed interface conversion circuit can be plugged onto a motherboard on which the signal transceiving function circuit is arranged or a daughter board for arranging the signal transceiving function circuit can be plugged onto a motherboard on which the high-speed interface conversion circuit is arranged.
In one possible design, the signal transceiver function circuit further includes a clock and trigger signal interface, a clock crystal oscillator module and a clock generating and distributing module, wherein the clock and trigger signal interface is used for receiving an external clock signal and trigger signal, the clock signal includes a sampling clock signal, a reference clock signal or a GPS second pulse signal, and the clock crystal oscillator module is used for generating an internal time base signal;
the clock signal port of the clock and trigger signal interface and the time base signal port of the clock crystal oscillator module are respectively connected with the input port of the clock generating and distributing module, the trigger signal port of the clock and trigger signal interface and the output port of the clock generating and distributing module are respectively connected with the communication interconnection module, the clock generating and distributing module is based on a phase-locked loop and is used for providing working clock signals for the communication interconnection module and the whole signal receiving and transmitting functional circuit based on the clock signals or the time base signals, and the trigger signal port is used for providing trigger signals for the communication interconnection module, wherein the trigger signals are used for triggering internal processing logic based on external events, so that a plurality of signal transceivers synchronously work.
In one possible design, when the first bus connector is connected with the downlink USB channel of the lightning controller, the signal transceiver function circuit further includes a USB-JTAG debug module connected with the second bus connector, where the USB-JTAG debug module is connected with the communication interconnect module, so that the signal processing computer located on an uplink side develops and debugs the communication interconnect module via the uplink lightning interface, the first bus connector, the second bus connector and the USB-JTAG debug module, or so that the signal processing computer located on an uplink side develops and debugs the communication interconnect module via at least one of the high-speed interface conversion circuit, the uplink lightning interface, the first bus connector, the second bus connector and the USB-JTAG debug module, which are cascaded and located on an uplink side.
In one possible design, the device further comprises a separate packaging structure for providing a protective casing and an air cooling heat dissipation function for the high-speed interface conversion circuit and the signal receiving and transmitting function circuit.
In a second aspect, a signal transceiver system is provided, which comprises a signal processing computer and the signal transceiver according to the first aspect or any possible design of the first aspect, wherein a lightning interface of the signal processing computer is connected with an uplink lightning interface of the signal transceiver.
In a third aspect, there is provided another signal transceiver system comprising a signal processing computer and a signal transceiver as described in the first aspect or any of the possible designs of the first aspect, wherein the number of signal transceivers is at least two;
bringing all of the signal transceivers into a sequential cascade relationship as follows: the upstream lightning interface of the first signal transceiver is connected with the lightning interface of the signal processing computer, and the downstream lightning interface of the former signal transceiver is connected with the upstream lightning interface of the latter signal transceiver.
In a second aspect, another signal transceiver system is provided, which comprises a signal processing computer and a signal transceiver as in the first aspect or any possible design of the first aspect, wherein the signal processing computer is provided with K lightning interfaces, the number of the signal transceivers is at least K and is divided into K groups, K represents a positive integer greater than or equal to 2, and the K groups are in one-to-one correspondence with the K lightning interfaces;
for each group in the K groups, if only one signal transceiver exists in the corresponding group, the uplink lightning interface of the signal transceiver is connected with the corresponding lightning interface, otherwise, all the signal transceivers in the corresponding group are in the following cascade connection relationship: the upstream lightning interface of the first signal transceiver is connected with the corresponding lightning interface, and the downstream lightning interface of the former signal transceiver is connected with the upstream lightning interface of the latter signal transceiver.
The beneficial effect of above-mentioned scheme:
(1) The invention creatively provides a new scheme of a signal transceiving circuit based on a lightning interface, namely, the signal transceiving circuit comprises a high-speed interface conversion circuit and a signal transceiving functional circuit, wherein the high-speed interface conversion circuit comprises an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, the uplink lightning interface is used for being connected with a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used for being connected with the cascaded next signal transceiver, the signal transceiving functional circuit comprises a second bus connector, a communication interconnection module and a signal transceiving functional front-end module used for completing the front-end task of a signal transceiving of a computer, and through the design of the connection relation of the signal transceiving functional circuit and the signal transceiving functional circuit, the centralized chassis back-plate data transmission bus of a traditional bus instrument system can be improved into the high-speed interface conversion circuit of each signal transceiver of the cascade, so that the signal transceiver comprising the high-speed interface conversion circuit can simultaneously meet the characteristics of super-high performance, low cost, multiple functions, light and expandability, and the like, and the system controller+the chassis of the traditional bus system can be conveniently realized into a cascade architecture of a plurality of signal transceivers and a plurality of groups of practical instrument systems and a practical application and a practical popularization.
(2) In the aspect of light portability: the starting weight of the chassis and the controller of the traditional PXIE, AXIE, VPX and LXI bus system is above 10kg, and the traditional PXIE, AXIE, VPX and LXI bus system does not comprise the peripheral equipment required by man-machine interaction such as a display, a keyboard and a mouse; even the all-in-one machine which is specially designed for portability and comprises a display screen and a keyboard and mouse is difficult to reduce the weight of the system to below 10kg, so that the volume of the system is large, and almost at least one desktop computer host is large. In the scheme of the embodiment, the special PXIE, AXIE and VPX bus type instrument system backboard is replaced by a commercial lightning interface and a clock triggering interface which can be cascaded in a plurality of groups, the cage, the guide rail, the fixing and backboard connector structure of the complex case system is replaced by an independent packaging structure, and the heat dissipation and power supply system design of the complex case system is replaced by an independent heat dissipation structure and a power supply design, so that the signal receiving and transmitting system does not need a special case any more, the system volume is greatly reduced, and the system weight is reduced; in addition, the high-integration commercial portable computer is used for replacing a special controller, a display and a keyboard and a mouse, and the integrated JTAG debugging circuit is used for replacing a JTAG interface and an external JTAG debugger, so that the system size can be further reduced, and the system weight can be reduced. The resulting weight of the single signal transceiver is typically less than 1.5kg, plus the weight of the notebook and power adapter, and does not exceed 3kg, and in terms of volume, it is expected that a single piece of equipment will only have a 32-inch thick notebook size, i.e., the signal transceiver of this embodiment can be reduced by up to 70% in weight and volume.
(3) In terms of low cost: the embodiment adopts commercial products and technologies which are already shipped on a large scale in the market, including a lightning interface, an FPGA, a commercial computer, a power adapter and the like, and the cost of the commercial products and technologies is only a fraction of that of a custom-designed controller, a chassis backboard and a chassis power supply; meanwhile, the embodiment adopts a simpler packaging structure and a heat dissipation design, so that the design, process and production requirements are greatly reduced, and the construction cost of the whole system is further reduced. Especially in the case of a small number of channels, the design of this embodiment can reduce the construction cost by at most 50%.
(4) In terms of high performance: according to the embodiment, the lightning interface is adopted, so that a single lightning interface bus can provide the highest 4GB/s bus bandwidth, the half bandwidth of the latest bus products such as PXIE and VPX is actually achieved, and the bus speed is as high as 4 times higher than that of the USB3.2gen2 bus which is commonly used by the latest portable equipment in the market. Considering that a single host computer typically has a maximum of 2 lightning interfaces, if a signal transceiver system is constructed using dual lightning interfaces, a total of 8GB/s of system bandwidth can be provided. Furthermore, the combination of lightning interfaces and PCIE buses also provides very low bus latency, which can meet the demands of most high performance applications.
(5) In terms of flexibility: considering that a single host computer is usually provided with at most 2 lightning interfaces, each lightning interface can cascade 6 signal transceivers, so that a signal transceiver system consisting of 1 to 12 modules can be constructed. Because the signal transceiver adopts an independent working design, a complex signal transceiver system can be gradually built from one device, and a chassis and a controller for primary building which are necessary for systems such as PXIE, AXIE, VPX and the like are not purchased, so that the system building threshold is greatly reduced, and the later expansibility is reserved.
(6) In terms of short development cycle: in the embodiment, the high-speed interface conversion circuit is used as a design of a sub-board of the signal receiving and transmitting function circuit, the signal receiving and transmitting function circuit is designed in a standardized manner by an FPGA, and a standardized design of a module structure, power supply and heat dissipation is realized, so that a developer can reuse standard hardware designs such as a bus interface, timing synchronization, power supply and heat dissipation for new module research and development; with PCIE technology ecological resources of commercial computer systems and reuse of standardized FPGAIP and driver software of the present invention, developers can mainly focus on design and development of signal transceiver circuits of modules. Design and development reuse of the standardized hardware and software can play a role in greatly shortening the development period.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a specific structure of a signal transceiver according to an embodiment of the present application.
Fig. 2 is a circuit diagram of an uplink lightning interface in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 3 is a circuit diagram of a first bus connector in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 4 is a circuit diagram of a first USB port controller in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 5 is a circuit diagram of a second USB port controller in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 6 is a circuit diagram of a USB port multiplexer in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 7 is a circuit example diagram of a two-way PCIE clock generator in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 8 is a circuit diagram of a power module in a high-speed interface conversion circuit according to an embodiment of the present application.
Fig. 9 is a circuit diagram of a second bus connector in a signal transceiver circuit according to an embodiment of the present application.
Fig. 10 is a circuit diagram of clock and trigger signal interfaces in a signal transceiver circuit according to an embodiment of the present application.
Fig. 11 is a circuit diagram of a clock generating and distributing module in a signal transceiving functional circuit according to an embodiment of the present application.
Fig. 12 is a circuit diagram of a USB-JTAG debug module in a signaling function circuit according to an embodiment of the present application.
Fig. 13 is a schematic structural diagram of a first signal transceiver system according to an embodiment of the present application.
Fig. 14 is a schematic structural diagram of a second signal transceiver system according to an embodiment of the present application.
Fig. 15 is a schematic structural diagram of a third signal transceiver system according to an embodiment of the present application.
Detailed Description
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the present application will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present application, but is not intended to limit the present application.
It should be understood that although the terms first and second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, a first object may be referred to as a second object, and similarly a second object may be referred to as a first object, without departing from the scope of example embodiments of the invention.
It should be understood that for the term "and/or" that may appear herein, it is merely one association relationship that describes an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: three cases of A alone, B alone or both A and B exist; as another example, A, B and/or C, can represent the presence of any one of A, B and C or any combination thereof; for the term "/and" that may appear herein, which is descriptive of another associative object relationship, it means that there may be two relationships, e.g., a/and B, it may be expressed that: the two cases of A and B exist independently or simultaneously; in addition, for the character "/" that may appear herein, it is generally indicated that the context associated object is an "or" relationship.
Embodiment one:
as shown in fig. 1, the signal transceiver provided in this embodiment includes, but is not limited to, a high-speed interface conversion circuit and a signal transceiver function circuit, where the high-speed interface conversion circuit includes, but is not limited to, an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, where the uplink lightning interface is used to connect to a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used to connect to a cascaded next signal transceiver, and the signal transceiver function circuit includes, but is not limited to, a second bus connector, a communication interconnection module and a signal transceiver function front end module for completing tasks of a local signal transceiver front end.
The high-speed interface conversion circuit is used for providing a standard high-speed serial interface, namely the uplink lightning interface, for the signal transceiver and connecting to the signal processing computer or the tandem former signal transceiver, and also providing a tandem high-speed serial interface, namely the downlink lightning interface, for the tandem latter signal transceiver, so as to realize the expandability of the signal transceiver. And the signal receiving and transmitting function circuit is used for realizing the specific signal receiving and transmitting function of the local machine. The uplink lightning interface and the downlink lightning interface are both existing lightning interfaces (also called as a Thunderbolt interface or a Lei Li interface, and are interface standards integrating two communication protocols, namely PCIES and DisplayPort, issued by Intel corporation, wherein PCIES is used for data transmission, and can be very conveniently used for expanding any type of equipment, while DisplayPort is used for displaying, and can synchronously transmit 1080p even ultra-high definition video and at most eight channels of audio). Since the latest lightning 3 and lightning 4 standards have physically adopted a USB type-C physical interface implementing a USB2.0 (universal serial bus) connection, so as to have a hot plug characteristic and provide a data transmission bandwidth of 40Gbps in both directions, the uplink lightning interface and the downlink lightning interface preferably adopt the lightning 3 standard or the lightning 4 standard, that is, the uplink lightning interface may preferably but not exclusively adopt the USB type-C physical interface to connect to the signal processing computer or the previous signal transceiver of the cascade, and the downlink lightning interface may preferably but not exclusively adopt the USB type-C physical interface to connect to the next signal transceiver of the cascade. In addition, the signal processing computer is used for providing functions such as system control, man-machine interaction, signal processing, data storage, peripheral connection and the like, so that a commercial notebook computer with lightning interfaces, which has the characteristics of low cost and high integration, can be preferably adopted instead of an expensive special system controller, a heavy display, a heavy mouse and the like.
The uplink lightning interface is connected with the uplink lightning channel of the lightning controller, and the downlink lightning interface is connected with the downlink lightning channel of the lightning controller, so that uplink and downlink equipment (wherein the uplink equipment is the signal processing computer or the cascaded previous signal transceiver, and the downlink equipment is the cascaded latter signal transceiver) are in cascade connection with the lightning controller through two lightning interfaces; the downlink PCIE channel of the lightning controller is connected with the first bus type connector, the first bus type connector is connected with the second bus type connector, the lightning controller is used for realizing conversion adaptation of a lightning interface and a PCIE bus, and PCIE protocol-based data communication is performed between the high-speed interface conversion circuit and the signal receiving and transmitting functional circuit through the first bus type connector and the second bus type connector; the communication interconnection module is respectively connected with the second bus type connector and the signal receiving and transmitting function front end module so as to realize data communication interconnection between the second bus type connector and the signal receiving and transmitting function front end module.
The foregoing lightning controller may be implemented in a hardware design by using existing devices, where the downlink PCIE channel of the lightning controller may, but is not limited to, use PCIE en3×1 or×4 channels to perform local signaling of 1Gbps or 4Gbps between the high-speed interface conversion circuit and the signaling function circuit (i.e., as PCIE bus specifications have been developed to 6.0 standards since release, the first generation to the fourth generation are currently mainly commercially used, each generation is commonly represented by Gen, the connection between two PCIE devices is called "connection" or "Link", each connection may have multiple channels Lane, the number of common channels is×1, ×4, ×8, and×16, if a PCIE connection is Gen2×4, one PCIE bus connection of one PCIE en3X1 has a transmission rate of 1GB/s, and one PCIE n3×4 Link has a transmission rate of 4 GB/s. Thus, by the circuit structure, the host can communicate with the upstream signal processing computer in a high-speed lightning protocol (the communication rate can reach 40Gbps at the highest). In addition, because the uplink lightning interface and the downlink lightning interface can realize the characteristic of hot plug, the characteristic of hot plug of the whole equipment of the machine can be realized, namely, the access and the starting of the signal transceiver equipment can be completed under the state that the signal processing computer is started, and meanwhile, because of the cascade characteristic of the high-speed interface conversion circuit, the topology expansion of the whole signal transceiver system under the starting state can be realized, and the multifunctional or multi-channel signal transceiver system capable of hot plug is formed.
The communication interconnection module may be, but is not limited to, implemented based on an FPGA (field programmable gate array), i.e. the communication interconnection module may be specifically configured with an FPGA chip and surrounding circuits, and may specifically use an IP core of a PCIE protocol (soft core and hard core of PCIE protocol are provided by mainstream FPGA manufacturers) to connect to the second bus connector. Because the FPGA device belongs to a semi-custom circuit in the application-specific integrated circuit, and is a programmable logic array, it has high-speed data throughput capability and high-speed logic and timing control capability, so the communication interconnection module can be suitable for implementing functions such as PCIE bus, timing logic and trigger timing. In order to match the downlink PCIE channels of the lightning controller using PCIE en3 x 1 or x 4 channels, the PCIE protocol preferably uses PCIE en3 x 1 or x 4 standards. In addition, the circuit structure of the front-end module of the signal receiving and transmitting function varies according to specific tasks, which is not an innovation point of the present embodiment, and the number of the front-end modules of the signal receiving and transmitting function may be one or more, so as to achieve the purpose of performing distributed setting on the front-end module of the signal receiving and transmitting function, as shown in fig. 1, the number of the front-end modules of the signal receiving and transmitting function is two by way of example.
The signal transceiver circuit based on the lightning interface comprises a high-speed interface conversion circuit and a signal transceiver function circuit, wherein the high-speed interface conversion circuit comprises an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, the uplink lightning interface is used for being connected with a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used for being connected with a cascaded next signal transceiver, the signal transceiver function circuit comprises a second bus connector, a communication interconnection module and a signal transceiver function front end module used for completing the task of a front end of a signal transceiver, and through the connection relation design of the signal transceiver function front end module and the signal transceiver function front end module, the centralized chassis backboard data transmission bus of a traditional bus instrument system can be improved into the high-speed interface conversion circuit of each cascaded signal transceiver, so that the signal transceiver comprising the high-speed interface conversion circuit can simultaneously meet the characteristics of ultra-portability, high performance, low cost, multiple functions, expandability and the like, and further the realization of the improvement of the architecture of the signal transceiver of the traditional bus instrument system and the signal transceiver system and the more than the practical instrument system and the more can be realized.
Preferably, the system further comprises a first USB port controller, wherein the first USB port controller is respectively connected to a USB physical interface (for example, but not limited to, a USB type-C physical interface) of the upstream lightning interface and the lightning controller, so as to realize power supply control and cable detection based on the USB physical interface, and further enable the host to communicate with and supply power to the upstream signal processing computer in a high-speed lightning protocol. In particular, the first USB port controller may be, but is not limited to, an existing USB3.1 port controller.
Preferably, the lightning protection device further comprises a second USB port controller, wherein the second USB port controller is respectively connected to a USB physical interface (for example, but not limited to, a USB type-C physical interface) of the downstream lightning interface and the lightning controller, so that the USB physical interface of the downstream lightning interface and the second USB port controller cooperate to realize downstream lightning cascade connection. Specifically, the second USB port controller may also, but not limited to, use an existing USB3.1 port controller.
Preferably, the lightning control device further comprises a USB port multiplexer, wherein the USB port multiplexer is respectively connected with a USB physical interface of the upstream lightning interface (for example and without limitation, a USB type-C physical interface), a USB physical interface of the lightning control device and a USB physical interface of the downstream lightning interface (for example and without limitation, a USB type-C physical interface), so as to realize communication connection between the lightning control device and the lightning interfaces of the upstream and downstream devices. In particular, the USB port multiplexer may be, but is not limited to, an existing USB2.0 port multiplexer.
Preferably, the lightning controller further comprises a two-way PCIE clock generator, wherein the two-way PCIE clock generator is used for connecting the first bus connector with a downlink PCIE channel of the lightning controller. The two-way PCIE clock generator may also use existing devices to implement hardware design.
Preferably, the downlink USB channel of the lightning controller is also connected to the first bus connector, and the lightning controller is further configured to implement conversion adaptation between a lightning interface and a USB bus, so that local signal transceiving based on a USB protocol is further performed between the high-speed interface conversion circuit and the signal transceiving functional circuit through the first bus connector and the second bus connector. Specifically, the downlink USB channel of the lightning controller may, but is not limited to, use a downlink USB3.1gen2 channel, so as to provide a USB bus communication function with a highest speed of 10Gbps, further enable local signal transceiving with a highest speed of 14Gbps to be implemented between the high-speed interface conversion circuit and the signal transceiving functional circuit, and further facilitate the purposes of providing integrated debugging for a communication interconnection module in the signal transceiving functional circuit and performing rapid integration for other possible USB devices.
Preferably, the high-speed interface conversion circuit further includes a power module, where the power module is connected to a USB physical interface (for example, but not limited to, a USB type-C physical interface) of the upstream lightning interface, and is configured to take power through the USB physical interface and supply power to the high-speed interface conversion circuit. Therefore, other power interfaces are not required to be additionally arranged, the neatness of the whole appearance can be improved, and the cost can be further reduced.
Preferably, the high-speed interface conversion circuit further comprises a storage module, wherein the storage module is connected with the lightning controller and is used for storing a function configuration program of the lightning controller. Specifically, the memory module may specifically employ an on-board BIOSFLASH (nonvolatile memory), so that the loader may start the high-speed interface conversion circuit when power is applied.
Preferably, the first bus connector and the second bus connector are used as a golden finger end connector and a slot end connector (for example, the first bus connector is used as a golden finger end M.2 connector, the second bus connector is used as a slot end M.2 connector, or the first bus connector is used as a slot end M.2 connector, and the second bus connector is used as a golden finger end M.2 connector), so that a daughter board for arranging the high-speed interface conversion circuit can be plugged onto a mother board for arranging the signal receiving and transmitting function circuit or a daughter board for arranging the signal receiving and transmitting function circuit can be plugged onto a mother board for arranging the high-speed interface conversion circuit. The first bus connector and the second bus connector are each preferably, but not limited to, an m.2 connector. Because the conventional PCIE interface uses a double-sided golden finger on a PCB (printed circuit board) circuit board and a corresponding PCIE slot form (there are other derivative forms, including an m.2 interface form of Intel special for extremely portable super-local design, of course), the specific design of the two-bus connector is beneficial to design the high-speed interface conversion circuit into a general, compact and quickly detachable high-integration daughter board form, thereby facilitating the whole machine production and facilitating the replacement of whole machine accessories (i.e. including a daughter board for arranging the high-speed interface conversion circuit and/or a motherboard for arranging the signal transceiver function circuit), and improving the flexibility of the product.
Preferably, the signal transceiver function circuit further includes, but is not limited to, a clock and trigger signal interface, a clock crystal oscillator module, and a clock generation and distribution module, wherein the clock and trigger signal interface is used for receiving external clock signals and trigger signals, the clock signals include, but are not limited to, sampling clock signals, reference clock signals, or GPS (GlobalPositioning System ) second pulse signals, and the clock crystal oscillator module is used for generating internal time base signals; the clock signal port of the clock and trigger signal interface and the time base signal port of the clock crystal oscillator module are respectively connected with the input port of the clock generating and distributing module, the trigger signal port of the clock and trigger signal interface and the output port of the clock generating and distributing module are respectively connected with the communication interconnection module, the clock generating and distributing module is based on a phase-locked loop and is used for providing working clock signals for the communication interconnection module and the whole signal receiving and transmitting functional circuit based on the clock signals or the time base signals, and the trigger signal port is used for providing trigger signals for the communication interconnection module, wherein the trigger signals are used for triggering internal processing logic based on external events, so that a plurality of signal transceivers synchronously work. Through the specific design of the signal receiving and transmitting functional circuit, the bus interface of the communication interconnection module and the clock triggering interface design can be standardized, the clock triggering bus circuit of the traditional bus type instrument system can be improved to be the clock triggering circuit of each signal transceiver, and the aim of improving the architecture of a system controller, a system case and a signal receiving and transmitting module of the traditional bus type instrument system to the architecture of a commercial computer and a signal transceiver capable of being cascaded in multiple groups can be further fulfilled. In addition, the signal receiving and transmitting functional circuit can also comprise an on-board FLASH chip, so that the firmware program of the communication interconnection module can be stored by using the on-board FLASH chip.
Preferably, when the first bus connector is connected to a downstream USB channel (specifically, a downstream USB3.1gen2 channel) of the lightning controller, the signal transceiver function circuit further includes a USB-JTAG debug module connected to the second bus connector, where the USB-JTAG debug module is connected to the communication interconnect module, so that the signal processing computer located on an upstream side develops and debugs the communication interconnect module via the upstream lightning interface, the first bus connector, the second bus connector, and the USB-JTAG debug module, or so that the signal processing computer located on an upstream side develops and debugs the communication interconnect module via at least one high-speed interface conversion circuit, the upstream lightning interface, the first bus connector, the second bus connector, and the USB-JTAG debug module, which are cascaded and located on an upstream side. Therefore, an additional independent JTAG (JointTestActionGroup, an international standard test protocol is not required to be set, and is mainly used for testing the inside of a chip) debugging interface is not required to be connected with an external JTAG debugger, so that the capability of debugging a communication interconnection module (such as an FPGA) of each signal transceiver is integrated, the number of equipment interfaces is reduced, portability is greatly improved, the neatness of the whole appearance is improved, and the cost is further reduced; for example, when the communication interconnection module realizes the data communication interconnection based on the FPGA, because the FPGA is programmed and debugged through the JTAG interface and the JTAG debugger, the development and debugging work can be greatly facilitated by integrating the JTAG debugger into each signal transceiver in the cascade. In addition, the downlink USB channel of the lightning controller can be used for facilitating the rapid and convenient integration of other USB devices into the signal receiving and transmitting functional circuit, and is not only used for JTAG debugging.
Preferably, the high-speed interface conversion circuit and the signal receiving and transmitting function circuit further comprise independent packaging structures for providing a protective shell and an air cooling and heat dissipation function for the high-speed interface conversion circuit and the signal receiving and transmitting function circuit. Therefore, the high-speed interface conversion circuit and the signal receiving and transmitting functional circuit can be ensured to work normally through the independent packaging structure. In addition, in order to facilitate combining a plurality of signal transceivers in cascade connection during cascade connection, the outer surface of the independent packaging structure can be specifically designed into structures which are beneficial to building block type stacking, such as a mortise-tenon structure.
In summary, the signal transceiver provided by the embodiment has the following technical effects:
(1) The embodiment provides a new scheme of a signal transceiver circuit based on a lightning interface, namely, the signal transceiver circuit comprises a high-speed interface conversion circuit and a signal transceiver function circuit, wherein the high-speed interface conversion circuit comprises an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, the uplink lightning interface is used for being connected with a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used for being connected with a cascaded next signal transceiver, the signal transceiver function circuit comprises a second bus connector, a communication interconnection module and a signal transceiver function front end module used for completing tasks of a front end of a signal transceiver of a local computer, and through the design of connection relation of the high-speed interface conversion circuit, the centralized chassis backboard data transmission bus of a traditional bus instrument system can be improved into the high-speed interface conversion circuit of each cascaded signal transceiver, so that the signal transceiver comprising the high-speed interface conversion circuit can simultaneously meet the characteristics of ultra-portability, high performance, low cost, multiple functions, expandability and the like, and further can be beneficial to realizing the improvement of a system controller and a signal transceiver of a traditional bus instrument system and the purpose of the improvement of a signal transceiver and the system and the signal transceiver as a multi-group of the cascaded transceiver and practical application of the system and the architecture of the computer.
(2) In the aspect of light portability: the starting weight of the chassis and the controller of the traditional PXIE, AXIE, VPX and LXI bus system is above 10kg, and the traditional PXIE, AXIE, VPX and LXI bus system does not comprise the peripheral equipment required by man-machine interaction such as a display, a keyboard and a mouse; even the all-in-one machine which is specially designed for portability and comprises a display screen and a keyboard and mouse is difficult to reduce the weight of the system to below 10kg, so that the volume of the system is large, and almost at least one desktop computer host is large. In the scheme of the embodiment, the special PXIE, AXIE and VPX bus type instrument system backboard is replaced by a commercial lightning interface and a clock triggering interface which can be cascaded in a plurality of groups, the cage, the guide rail, the fixing and backboard connector structure of the complex case system is replaced by an independent packaging structure, and the heat dissipation and power supply system design of the complex case system is replaced by an independent heat dissipation structure and a power supply design, so that the signal receiving and transmitting system does not need a special case any more, the system volume is greatly reduced, and the system weight is reduced; in addition, the high-integration commercial portable computer is used for replacing a special controller, a display and a keyboard and a mouse, and the integrated JTAG debugging circuit is used for replacing a JTAG interface and an external JTAG debugger, so that the system size can be further reduced, and the system weight can be reduced. The resulting weight of the single signal transceiver is typically less than 1.5kg, plus the weight of the notebook and power adapter, and does not exceed 3kg, and in terms of volume, it is expected that a single piece of equipment will only have a 32-inch thick notebook size, i.e., the signal transceiver of this embodiment can be reduced by up to 70% in weight and volume.
(3) In terms of low cost: the embodiment adopts commercial products and technologies which are already shipped on a large scale in the market, including a lightning interface, an FPGA, a commercial computer, a power adapter and the like, and the cost of the commercial products and technologies is only a fraction of that of a custom-designed controller, a chassis backboard and a chassis power supply; meanwhile, the embodiment adopts a simpler packaging structure and a heat dissipation design, so that the design, process and production requirements are greatly reduced, and the construction cost of the whole system is further reduced. Especially in the case of a small number of channels, the design of this embodiment can reduce the construction cost by at most 50%.
(4) In terms of high performance: according to the embodiment, the lightning interface is adopted, so that a single lightning interface bus can provide the highest 4GB/s bus bandwidth, the half bandwidth of the latest bus products such as PXIE and VPX is actually achieved, and the bus speed is as high as 4 times higher than that of the USB3.2gen2 bus which is commonly used by the latest portable equipment in the market. Considering that a single host computer typically has a maximum of 2 lightning interfaces, if a signal transceiver system is constructed using dual lightning interfaces, a total of 8GB/s of system bandwidth can be provided. Furthermore, the combination of lightning interfaces and PCIE buses also provides very low bus latency, which can meet the demands of most high performance applications.
(5) In terms of flexibility: considering that a single host computer is usually provided with at most 2 lightning interfaces, each lightning interface can cascade 6 signal transceivers, so that a signal transceiver system consisting of 1 to 12 modules can be constructed. Because the signal transceiver adopts an independent working design, a complex signal transceiver system can be gradually built from one device, and a chassis and a controller for primary building which are necessary for systems such as PXIE, AXIE, VPX and the like are not purchased, so that the system building threshold is greatly reduced, and the later expansibility is reserved.
(6) In terms of short development cycle: in the embodiment, the high-speed interface conversion circuit is used as a design of a sub-board of the signal receiving and transmitting function circuit, the signal receiving and transmitting function circuit is designed in a standardized manner by an FPGA, and a standardized design of a module structure, power supply and heat dissipation is realized, so that a developer can reuse standard hardware designs such as a bus interface, timing synchronization, power supply and heat dissipation for new module research and development; with PCIE technology ecological resources of commercial computer systems and reuse of standardized FPGAIP and driver software of the present invention, developers can mainly focus on design and development of signal transceiver circuits of modules. Design and development reuse of the standardized hardware and software can play a role in greatly shortening the development period.
Example two
The first novel signal transceiver system based on the signal transceiver of the first embodiment is provided on the basis of the technical scheme of the first embodiment, that is, the novel signal transceiver system comprises a signal processing computer and the signal transceiver of the first embodiment, wherein a lightning interface of the signal processing computer is connected with an uplink lightning interface of the signal transceiver. As shown in fig. 13, a portable signal transceiver system is formed by connecting a lightning interface and an active lightning cable between a signal transceiver and a signal processing computer, wherein the signal processing computer is selected as a commercial notebook computer with a lightning interface. Thus, the system structure is suitable for constructing a highly portable signal receiving and transmitting system because the signal transceiver and the commercial notebook computer have the characteristics of small size and light weight.
The technical details and technical effects of the foregoing system provided in this embodiment may be referred to the signal transceiver in the first embodiment, and are not described herein.
Example III
The first embodiment provides a second novel signal transceiver system based on the signal transceiver of the first embodiment, that is, the signal transceiver system includes a signal processing computer and the signal transceivers of the first embodiment, wherein the number of the signal transceivers is at least two; bringing all of the signal transceivers into a sequential cascade relationship as follows: the upstream lightning interface of the first signal transceiver is connected with the lightning interface of the signal processing computer, and the downstream lightning interface of the former signal transceiver is connected with the upstream lightning interface of the latter signal transceiver. As shown in fig. 14, the number of the signal transceivers is three, and is different from the second embodiment, in this embodiment, each signal transceiver (except the last signal transceiver) may be connected to the next signal transceiver through its cascaded lightning interface, and the cascaded expansion supports a hot plug operation. In order to enable the signal timing and synchronous transceiving between any two signal transceivers through the external clock signal and the trigger signal, the clock and trigger signal interfaces of all the signal transceivers are preferably connected together. The structure is suitable for quickly constructing a multi-channel or multi-functional signal receiving and transmitting system.
The technical details and technical effects of the foregoing system provided in this embodiment may be referred to the signal transceiver in the first embodiment, and are not described herein.
Example IV
The third novel signal transceiver system based on the signal transceiver of the first embodiment is provided on the basis of the technical solution of the first embodiment, that is, the novel signal transceiver system includes a signal processing computer and the signal transceiver of the first embodiment, wherein the signal processing computer has K lightning interfaces, the number of the signal transceivers is at least K and is divided into K groups, K represents a positive integer greater than or equal to 2, and the K groups are in one-to-one correspondence with the K lightning interfaces; for each group in the K groups, if only one signal transceiver exists in the corresponding group, the uplink lightning interface of the signal transceiver is connected with the corresponding lightning interface, otherwise, all the signal transceivers in the corresponding group are in the following cascade connection relationship: the upstream lightning interface of the first signal transceiver is connected with the corresponding lightning interface, and the downstream lightning interface of the former signal transceiver is connected with the upstream lightning interface of the latter signal transceiver. As shown in fig. 15, the number of the signal transceivers is 4 and is divided into two groups (i.e. two signal transceivers in each group), so that each group is cascaded with two signal transceivers, thus, when the number of signal transceivers required by the system is more and the data transmission capability is more required, compared with the third embodiment, multiple groups of cascaded signal transceivers can be connected by selecting a signal processing computer supporting multiple lightning interfaces. Also, in order to enable signal timing and synchronous transceiving between any two signal transceivers via external clock signals and trigger signals, the clock and trigger signal interfaces of all the signal transceivers are preferably connected together. The structure is suitable for constructing a signal receiving and transmitting system with more channels or more module function requirements and larger data throughput.
The technical details and technical effects of the foregoing system provided in this embodiment may be referred to the signal transceiver in the first embodiment, and are not described herein.
Finally, it should be noted that: the foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The signal transceiver is characterized by comprising a high-speed interface conversion circuit and a signal transceiver function circuit, wherein the high-speed interface conversion circuit comprises an uplink lightning interface, a downlink lightning interface, a lightning controller and a first bus connector, the uplink lightning interface is used for being connected with a signal processing computer or a cascaded previous signal transceiver, the downlink lightning interface is used for being connected with a cascaded next signal transceiver, and the signal transceiver function circuit comprises a second bus connector, a communication interconnection module and a signal transceiver function front-end module used for completing a local signal transceiver front-end task;
the uplink lightning interface is connected with the uplink lightning channel of the lightning controller, and the downlink lightning interface is connected with the downlink lightning channel of the lightning controller, so that the uplink and downlink equipment is connected with the lightning controller in a cascade manner through the two lightning interfaces;
The downlink PCIE channel of the lightning controller is connected with the first bus type connector, the first bus type connector is connected with the second bus type connector, the lightning controller is used for realizing conversion adaptation of a lightning interface and a PCIE bus, and PCIE protocol-based data communication is performed between the high-speed interface conversion circuit and the signal receiving and transmitting functional circuit through the first bus type connector and the second bus type connector;
the communication interconnection module is respectively connected with the second bus type connector and the signal receiving and transmitting function front end module so as to realize data communication interconnection between the second bus type connector and the signal receiving and transmitting function front end module.
2. The signal transceiver of claim 1, further comprising a first USB port controller, wherein the first USB port controller is respectively connected to the USB physical interface of the upstream lightning interface and the lightning controller, so as to implement power supply control and cable detection based on the USB physical interface;
and/or, the lightning protection device further comprises a second USB port controller, wherein the second USB port controller is respectively connected with the USB physical interface of the downlink lightning interface and the lightning controller, so that the USB physical interface of the downlink lightning interface and the second USB port controller are matched to realize downlink lightning cascade connection;
And/or, the lightning protection device further comprises a USB port multiplexer, wherein the USB port multiplexer is respectively connected with the USB physical interface of the uplink lightning interface, the USB physical interfaces of the lightning controller and the downlink lightning interface so as to realize the communication connection between the lightning controller and the lightning interfaces of the uplink and downlink devices;
and/or, the lightning controller further comprises a two-way PCIE clock generator, wherein the two-way PCIE clock generator is used for being matched with a downlink PCIE channel of the lightning controller to be connected with the first bus connector;
and/or, the downlink USB channel of the lightning controller is also connected with the first bus connector, and the lightning controller is further used for realizing conversion adaptation of a lightning interface and a USB bus so as to further perform local signal transceiving based on a USB protocol between the high-speed interface conversion circuit and the signal transceiving functional circuit through the first bus connector and the second bus connector.
3. The signal transceiver of claim 1, wherein the high-speed interface conversion circuit further comprises a power module and/or a memory module;
the power module is connected with the USB physical interface of the uplink lightning interface, and is used for taking electricity through the USB physical interface and supplying power to the high-speed interface conversion circuit;
The storage module is connected with the lightning controller and used for storing a function configuration program of the lightning controller.
4. The signal transceiver of claim 1, wherein the first bus connector and the second bus connector mutually employ a connector that is a golden finger terminal and a connector that is a slot terminal so that a daughter board for disposing the high-speed interface conversion circuit can be plugged onto a motherboard disposed with the signal transceiver function circuit or a daughter board for disposing the signal transceiver function circuit can be plugged onto a motherboard disposed with the high-speed interface conversion circuit.
5. The signal transceiver of claim 1, wherein the signal transceiver function circuit further comprises a clock and trigger signal interface, a clock crystal oscillator module and a clock generation and distribution module, wherein the clock and trigger signal interface is used for receiving an external clock signal and trigger signal, the clock signal comprises a sampling clock signal, a reference clock signal or a GPS second pulse signal, and the clock crystal oscillator module is used for generating an internal time base signal;
the clock signal port of the clock and trigger signal interface and the time base signal port of the clock crystal oscillator module are respectively connected with the input port of the clock generating and distributing module, the trigger signal port of the clock and trigger signal interface and the output port of the clock generating and distributing module are respectively connected with the communication interconnection module, the clock generating and distributing module is based on a phase-locked loop and is used for providing working clock signals for the communication interconnection module and the whole signal receiving and transmitting functional circuit based on the clock signals or the time base signals, and the trigger signal port is used for providing trigger signals for the communication interconnection module, wherein the trigger signals are used for triggering internal processing logic based on external events, so that a plurality of signal transceivers synchronously work.
6. The signal transceiver of claim 5, wherein when the first bus connector is connected to a downstream USB channel of the lightning controller, the signal transceiver function circuit further comprises a USB-JTAG debug module connected to the second bus connector, wherein the USB-JTAG debug module is connected to the communication interconnect module such that a signal processing computer located on an upstream side develops and debugs the communication interconnect module via the upstream lightning interface, the first bus connector, the second bus connector, and the USB-JTAG debug module, or such that a signal processing computer located on an upstream side develops and debugs the communication interconnect module via at least one of the high speed interface conversion circuit, the upstream lightning interface, the first bus connector, the second bus connector, and the USB-JTAG debug module that are cascaded and located on an upstream side.
7. The signal transceiver of claim 1, further comprising a separate package structure for providing a protective enclosure and an air-cooled heat dissipation function for the high speed interface conversion circuit and the signal transceiver function circuit.
8. A signal transceiving system comprising a signal processing computer and a signal transceiver according to any of claims 1 to 7, wherein a lightning interface of said signal processing computer is connected to an upstream lightning interface of said signal transceiver.
9. A signal transceiving system comprising a signal processing computer and a signal transceiver as claimed in any of claims 1 to 7, wherein the number of signal transceivers is at least two;
bringing all of the signal transceivers into a sequential cascade relationship as follows: the upstream lightning interface of the first signal transceiver is connected with the lightning interface of the signal processing computer, and the downstream lightning interface of the former signal transceiver is connected with the upstream lightning interface of the latter signal transceiver.
10. A signal receiving and transmitting system, characterized by comprising a signal processing computer and the signal transceiver according to any one of claims 1-7, wherein the signal processing computer is provided with K lightning interfaces, the number of the signal transceivers is at least K and is divided into K groups, K represents a positive integer greater than or equal to 2, and the K groups are in one-to-one correspondence with the K lightning interfaces;
For each group in the K groups, if only one signal transceiver exists in the corresponding group, the uplink lightning interface of the signal transceiver is connected with the corresponding lightning interface, otherwise, all the signal transceivers in the corresponding group are in the following cascade connection relationship: the upstream lightning interface of the first signal transceiver is connected with the corresponding lightning interface, and the downstream lightning interface of the former signal transceiver is connected with the upstream lightning interface of the latter signal transceiver.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2022113754961 | 2022-11-04 | ||
| CN202211375496.1A CN115481063A (en) | 2022-11-04 | 2022-11-04 | Distributed high-speed signal receiving and transmitting processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116680220A CN116680220A (en) | 2023-09-01 |
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Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211375496.1A Withdrawn CN115481063A (en) | 2022-11-04 | 2022-11-04 | Distributed high-speed signal receiving and transmitting processing system |
| CN202310663750.6A Active CN116647247B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
| CN202310666458.XA Active CN116841932B (en) | 2022-11-04 | 2023-06-06 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
| CN202310666462.6A Active CN116680221B (en) | 2022-11-04 | 2023-06-06 | Distributed high-speed signal receiving and transmitting processing system |
| CN202310662181.3A Active CN116680220B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system |
Family Applications Before (4)
| Application Number | Title | Priority Date | Filing Date |
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| CN202211375496.1A Withdrawn CN115481063A (en) | 2022-11-04 | 2022-11-04 | Distributed high-speed signal receiving and transmitting processing system |
| CN202310663750.6A Active CN116647247B (en) | 2022-11-04 | 2023-06-06 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
| CN202310666458.XA Active CN116841932B (en) | 2022-11-04 | 2023-06-06 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
| CN202310666462.6A Active CN116680221B (en) | 2022-11-04 | 2023-06-06 | Distributed high-speed signal receiving and transmitting processing system |
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| Country | Link |
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| CN (5) | CN115481063A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116383107B (en) * | 2023-06-06 | 2023-08-22 | 成都立思方信息技术有限公司 | Flexibly-expandable signal receiving and transmitting system |
| CN116955258B (en) * | 2023-09-19 | 2023-11-28 | 成都立思方信息技术有限公司 | Flexibly-connectable trigger connector, signal acquisition control equipment and system |
| CN117289236B (en) * | 2023-11-27 | 2024-02-09 | 成都立思方信息技术有限公司 | Short-time radar signal intra-pulse modulation type identification method, device, equipment and medium |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN116680220A (en) | 2023-09-01 |
| CN116841932B (en) | 2024-03-26 |
| CN116647247A (en) | 2023-08-25 |
| CN116680221A (en) | 2023-09-01 |
| CN115481063A (en) | 2022-12-16 |
| CN116841932A (en) | 2023-10-03 |
| CN116647247B (en) | 2024-01-26 |
| CN116680221B (en) | 2024-03-26 |
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