CN214176363U

CN214176363U - PCIE equipment board card expansion connecting device for system level simulation accelerator verification environment

Info

Publication number: CN214176363U
Application number: CN202022825378.9U
Authority: CN
Inventors: 吴沙; 王忠弈; 马鑫; 夏永乐; 杨庆娜; 王红灵; 柏颖; 高金培; 胡恩; 李晨; 宋欲佳; 吴轲
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2021-09-10
Anticipated expiration: 2030-11-30

Abstract

The utility model discloses a system level emulation accelerator verifies that PCIE equipment integrated circuit board extension connecting device for environment, which comprises a mainboard, have the first PCIE slot that is used for connecting the golden finger interface of PCIE equipment integrated circuit board on the mainboard respectively and be used for connecting the golden finger interface of the design that awaits measuring, control signal pin between first PCIE slot and the first PCIE slot is parallelly connected each other, complementary connection between the data signal pin between first PCIE slot and the first PCIE slot. The utility model discloses can realize that the golden finger interface of PCIE equipment integrated circuit board in the system level emulation accelerator verification environment, the one-to-one connection between the golden finger interface of the design of awaiting measuring, the reinforcing has simple structure, convenient to use's advantage to the verification ability of PCIE equipment.

Description

PCIE equipment board card expansion connecting device for system level simulation accelerator verification environment

Technical Field

The utility model relates to an integrated circuit verifies the field, concretely relates to system level emulation accelerator is PCIE (peripheral component interconnect express) equipment integrated circuit board extension connecting device for verification environment for realize the design that awaits measuring in the system level emulation accelerator verification environment and be connected of PCIE peripheral hardware integrated circuit board.

Background

PCIE is a high-speed serial computer expansion bus standard proposed by intel in 2001, and aims to replace old bus standards such as PCI, PCI-X, and the like, and PCIE belongs to a high-speed serial point-to-point dual-channel high-bandwidth transmission technical standard. Nowadays, the design size of the integrated circuit is large and the structure is complex, and the requirement for the verification of the PCIE peripheral is increased. The integrated circuit needs to be connected with a plurality of PCIE external devices in system level verification, and the hardware simulation accelerator or other verification environments do not have the capability of being directly connected with the PCIE external daughter card, so that an expansion connection device is needed to complete the connection between the design to be tested and the external PCIE device board card in the system level simulation accelerator verification environment.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem who solves: to the above-mentioned problem of prior art, a system level emulation accelerator is verified PCIE equipment integrated circuit board extension connecting device for environment is provided, the utility model discloses can realize that the golden finger interface of PCIE equipment integrated circuit board in the system level emulation accelerator verification environment, the one-to-one connection between the golden finger interface of the design of awaiting measuring, the reinforcing has simple structure, convenient to use's advantage to the verification ability of PCIE equipment.

In order to solve the technical problem, the utility model discloses a technical scheme be:

the system-level simulation accelerator verification environment peripheral PCIE equipment board card expansion connecting device comprises a mainboard, wherein a first PCIE slot used for connecting a golden finger interface of a PCIE equipment board card and a second PCIE slot used for connecting the golden finger interface of a design to be tested are respectively arranged on the mainboard, control signal pins between the first PCIE slot and the second PCIE slot are mutually connected in parallel, and data signal pins between the first PCIE slot and the second PCIE slot are complementarily connected.

Optionally, a reset key is arranged on the motherboard, and a pin of the reset key is connected with a reset signal pin in control signal pins of the first PCIE slot and the second PCIE slot.

Optionally, an independent power interface is arranged on the motherboard, and the independent power interface is connected to power terminals of the first PCIE slot and the second PCIE slot through power lines.

Optionally, a power switch is arranged on the motherboard, and the power switch is arranged in series on a power line connecting the independent power interface and the power terminals of the first PCIE slot and the second PCIE slot.

Optionally, an on-board clock source is disposed on the motherboard, and pins of the on-board clock source are connected to clock signal pins in control signal pins of the first PCIE slot and the second PCIE slot.

Optionally, the first PCIE slot is directly soldered and fixed on the motherboard or connected to the motherboard through a PCIE extension cable.

Optionally, the second PCIE slot is directly soldered and fixed to the motherboard or connected to the motherboard through a PCIE extension cable.

Optionally, a plurality of first fixing through holes for fixing the PCIE device board card are disposed around the motherboard, and a second fixing through hole for fixing the power plug is disposed on one side of the independent power interface.

Optionally, the first fixing through hole simultaneously serves as a ground terminal of the main board.

Optionally, an avoiding hole for placing the PCIE device board and the metal patch on the test-receiving design is formed in one end of the motherboard located in the first PCIE slot and the second PCIE slot.

Compared with the prior art, the utility model has the advantages of as follows: the utility model discloses system level emulation accelerator verifies that first PCIE slot that the golden finger interface of environment used for PCIE equipment integrated circuit board extension connecting device has the golden finger interface that is used for connecting the PCIE equipment integrated circuit board on the mainboard respectively and is used for connecting the first PCIE slot of the golden finger interface of design that awaits measuring, control signal pin between first PCIE slot and the first PCIE slot is parallelly connected each other, complementary connection between the data signal pin between first PCIE slot and the first PCIE slot, through the structure, can realize the golden finger interface of PCIE equipment integrated circuit board in the system level emulation accelerator verification environment, the one-to-one connection between the golden finger interface of design that awaits measuring, the reinforcing is to the verification ability of PCIE equipment, and the circuit board extension connecting device has the advantages of simple structure and convenient use.

Drawings

Fig. 1 is a schematic front structural diagram of an embodiment of the present invention.

Fig. 2 is a schematic diagram of a back structure according to an embodiment of the present invention.

Fig. 3 is a schematic view of a usage status of the embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a PCIE extension cable in the embodiment of the present invention.

Detailed Description

In order to understand the technical features of the invention more clearly. The following detailed description will be made of a specific embodiment of a PCIE expansion connection apparatus according to the present invention with reference to the accompanying drawings.

As shown in fig. 1, fig. 2, and fig. 3, the PCIE device board expansion connection apparatus for verification environment of the system-level emulation accelerator in this embodiment includes a motherboard 1, where the motherboard 1 has a first PCIE slot 2 for connecting a gold finger interface of a PCIE device board and a second PCIE slot 3 for connecting a gold finger interface of a design to be tested, respectively, control signal pins between the first PCIE slot 2 and the second PCIE slot 3 are connected in parallel, and data signal pins between the first PCIE slot 2 and the second PCIE slot 3 are complementarily connected. In this embodiment, the PCIE device board expansion connection apparatus for the system-level simulation accelerator verification environment can realize expansion connection between the golden finger interface of the PCIE device board and the golden finger interface of the design to be tested through the first PCIE slot 2 and the second PCIE slot 3 on the motherboard 1. The data signal pins are complementarily connected, that is, the data transmission signal pin TX in the second PCIE slot 3 is connected to the data reception signal pin RX in the first PCIE slot 2, and the data reception signal pin RX in the second PCIE slot 3 is connected to the data transmission signal pin TX in the first PCIE slot 2. In the using process, the PCIE equipment board card and the design to be tested form a master device and a slave device, the master device is the design to be tested in the system level simulation accelerator verification environment, and the slave device is the PCIE equipment board card. It should be noted that, in the figure, the order or the position of the first PCIE slot 2 and the second PCIE slot 3 may be interchanged, the first PCIE slot 2 and the second PCIE slot 3 are located on the front side of the motherboard 1, and in addition, may be all disposed on the back side of the motherboard 1 as needed, or one may be placed on the front side of the motherboard 1 and the other may be placed on the back side of the motherboard 1, which does not affect the implementation of the one-to-one connection between the golden finger interface of the PCIE device board card and the golden finger interface of the design to be tested in the system-level simulation accelerator verification environment in this embodiment.

As shown in fig. 1, the main board 1 of this embodiment is provided with a reset key 4, and a pin of the reset key 4 is connected to a reset signal pin in control signal pins of both the first PCIE slot 2 and the second PCIE slot 3, so as to provide a synchronous reset signal for both a PCIE device board and a design to be tested.

In order to simplify the power supply of the PCIE device board and the design to be tested, as shown in fig. 2, an independent power interface 5 is disposed on the motherboard 1 in this embodiment, and the independent power interface 5 is respectively connected to the power terminals of the first PCIE slot 2 and the second PCIE slot 3 through power lines, so that the integrated power supply of the PCIE device board and the design to be tested by using an external power source is realized.

In order to facilitate integrated power supply control of the PCIE device board and the design to be tested, as shown in fig. 1, a power switch 6 is disposed on the main board 1 in this embodiment, the power switch 6 is serially arranged on a power line where the independent power interface 5 is connected to the power terminals of the first PCIE slot 2 and the second PCIE slot 3, and when the PCIE device board and the design to be tested are plugged, the power supply can be turned off through the power switch 6, so that the safety of the PCIE device board and the design to be tested is ensured.

As shown in fig. 1, an on-board clock source 7 is disposed on the motherboard 1 in this embodiment, and pins of the on-board clock source 7 are connected to clock signal pins in control signal pins of both the first PCIE slot 2 and the second PCIE slot 3, so as to provide reference clock signals required by the PCIE device board card.

The first PCIE slot 2 may be directly soldered and fixed on the motherboard 1 or connected to the motherboard 1 through a PCIE extension cable 8 as needed; the second PCIE slot 3 may be directly soldered and fixed on the motherboard 1 or connected to the motherboard 1 through a PCIE extension cable 8 as required (as shown in fig. 4).

As shown in fig. 1, fig. 2 and fig. 3, a plurality of (specifically, 6 in this embodiment) first fixing through holes 11 for fixing a PCIE device board card are provided around the motherboard 1 in this embodiment, so that the PCIE device board card can be conveniently fixed; one side of the main board 1, which is located at the independent power interface 5, is provided with a second fixing through hole 12 for fixing a power plug, so that the reliability and stability of an external power supply can be ensured.

In this embodiment, the first fixing through hole 11 serves as a ground terminal of the motherboard 1, so that the motherboard 1 and the PCIE device board can be grounded stably and reliably.

As shown in fig. 1, fig. 2, fig. 3, and fig. 4, one end of the main board 1 located in the first PCIE slot 2 and the second PCIE slot 3 is provided with a avoiding hole 13 for placing a PCIE device board and a metal patch on the device under test, and through the design of the avoiding hole 13, the embodiment can support the metal patch (used for heat dissipation) with an over size on the PCIE device board and the device under test, so as to improve the compatibility of the PCIE device board and the device under test.

It is above only the utility model discloses a preferred embodiment, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. The system-level simulation accelerator board card expansion connecting device for the verification environment is characterized by comprising a mainboard (1), wherein a first PCIE slot (2) used for connecting a golden finger interface of a PCIE equipment board card and a second PCIE slot (3) used for connecting the golden finger interface of a design to be tested are respectively arranged on the mainboard (1), control signal pins between the first PCIE slot (2) and the second PCIE slot (3) are connected in parallel, and data signal pins between the first PCIE slot (2) and the second PCIE slot (3) are complementarily connected.

2. The PCIE device board expansion connection apparatus according to claim 1, wherein a reset key (4) is disposed on the motherboard (1), and a pin of the reset key (4) is connected to a reset signal pin in control signal pins of the first PCIE slot (2) and the second PCIE slot (3).

3. The PCIE device board expansion connection apparatus according to claim 1, wherein an independent power interface (5) is disposed on the motherboard (1), and the independent power interface (5) is connected to power terminals of the first PCIE slot (2) and the second PCIE slot (3) through power lines, respectively.

4. The PCIE device board expansion connecting device used in the verification environment of the system level simulation accelerator as claimed in claim 3, wherein a power switch (6) is arranged on the motherboard (1), and the power switch (6) is serially arranged on a power line connecting the independent power interface (5) and the power terminals of the first PCIE slot (2) and the second PCIE slot (3).

5. The PCIE device board expansion connecting device for verification environment of system level simulation accelerator as claimed in claim 1, wherein an on-board clock source (7) is arranged on the motherboard (1), and pins of the on-board clock source (7) are connected with clock signal pins in control signal pins of the first PCIE slot (2) and the second PCIE slot (3).

6. The PCIE device board expansion connection apparatus according to claim 1, where the first PCIE slot (2) is directly soldered and fixed to the motherboard (1) or connected to the motherboard (1) through a PCIE extension cable (8).

7. The PCIE device board expansion connection apparatus according to claim 1, where the second PCIE slot (3) is directly soldered and fixed to the motherboard (1) or connected to the motherboard (1) through a PCIE extension cable (8).

8. The PCIE equipment board expansion connecting device used in the verification environment of the system level simulation accelerator as claimed in claim 3, wherein a plurality of first fixing through holes (11) for fixing the PCIE equipment board are arranged around the main board (1), and a second fixing through hole (12) for fixing a power plug is arranged at one side of the independent power interface (5).

9. The PCIE device board expansion connection apparatus according to claim 8, wherein the first fixed through hole (11) is simultaneously used as a ground terminal of the motherboard (1).

10. The PCIE device board expansion connection apparatus according to claim 1, wherein an avoiding hole (13) for placing a PCIE device board and a metal patch on a device under test is formed in one end of the motherboard (1) located in the first PCIE slot (2) and the second PCIE slot (3).