CN214591389U - Extensible cognitive radio system - Google Patents
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Abstract
The application discloses an extensible cognitive radio system, and relates to the technical field of electronic information. The extensible cognitive radio system comprises a heterogeneous computing platform, a radio front end and a serial adapter, wherein the heterogeneous computing platform comprises a central processing unit and a first processor used for processing parallel computing tasks, and the central processing unit is connected with the first processor; the radio front end comprises an analog-digital/digital-analog converter, a radio frequency signal input/output channel and a second processor for preprocessing data, and the analog-digital/digital-analog converter is respectively connected with the second processor and the radio frequency signal input/output channel; the serial adapter comprises an FPGA chip which is in communication connection with the central processing unit and the second processing unit through high-speed serial ports. The extensible cognitive radio system disclosed by the application has high data throughput capacity, signal processing capacity and flexible channel expansion capacity.
Description
Technical Field
The application relates to the technical field of electronic information, in particular to an extensible cognitive radio system.
Background
Cognitive Radio (CR) is an intelligent Software Radio (SDR) with spectrum sensing capability, and its physical platform is based on a Software Radio platform, and has additional functions of sensing, learning, etc. on the basis of the Software Radio platform to realize its unique Cognitive capability.
At present, a traditional software radio platform is limited by an architecture of an embedded computer, which mainly includes an arm (advanced RISC machines) processor, a Field Programmable Gate Array (FPGA), and a Digital Signal Processor (DSP), and system data throughput, data processing capability, and a limited number of channels of the architecture all become bottlenecks, so that complexity and difficulty of program development are greatly improved, and expandability and application scenarios of the system are greatly limited.
Therefore, how to provide a cognitive radio system with high data throughput, strong signal processing capability, flexible channel expansion capability and convenient construction has become an urgent problem in the prior art.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application adopts the following technical scheme:
a scalable cognitive radio system, comprising:
the heterogeneous computing platform comprises a central processing unit and a first processor for processing parallel computing tasks, and the central processing unit is connected with the first processor;
the radio front end comprises an analog-digital/digital-analog converter, a radio frequency signal input/output channel and a second processor for preprocessing data, wherein the analog-digital/digital-analog converter is respectively connected with the second processor and the radio frequency signal input/output channel;
the serial adapter comprises a first FPGA chip, and the first FPGA chip is in communication connection with the central processing unit and the second processing unit through high-speed serial ports respectively.
In one possible design, the first processor is a neural network processor or a graphics acceleration processor.
In one possible design, the second processor is a field programmable gate array.
In one possible design, the second processor includes a field programmable gate array and an ARM processor, the field programmable gate array and the ARM processor being integrated to form the second processor.
In one possible design, the radio front ends and the serial adapters are multiple and equal in number, the multiple radio front ends correspond to the multiple serial adapters one by one, and first FPGA chips of the multiple serial adapters are respectively in communication connection with the central processor and the corresponding second processors through high-speed serial ports.
In one possible design, signal acquisition and generation synchronization between multiple radio front ends.
In one possible design, the number of the radio front ends is multiple, and the first FPGA chip of the serial adapter is in communication connection with the central processor and the second processors of the multiple radio front ends respectively through high-speed serial ports.
In one possible design, the heterogeneous computing platform further includes a second FPGA chip, and the second FPGA chip is connected between the central processing unit and the first FPGA chip.
In one possible design, the radio front end further includes a first memory, and the first memory is connected to the second processor.
In one possible design, the heterogeneous computing platform further includes a hard disk, a second memory and a video memory, the hard disk and the second memory are both connected with the central processing unit, and the video memory is connected with the first processor.
The embodiment of the application adopts at least one technical scheme which can achieve the following beneficial effects:
the extensible cognitive radio system provided by the embodiment of the application has the advantages of high data throughput capacity, artificial intelligence algorithm computing capacity, flexible channel expansion capacity, convenience in system construction and the like.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of a scalable cognitive radio system according to a first embodiment of the present application.
Fig. 2 is a schematic structural diagram of another scalable cognitive radio system according to the first embodiment of the present application.
Fig. 3 is a schematic structural diagram of a scalable cognitive radio system according to a second embodiment of the present application.
Fig. 4 is a schematic structural diagram of another scalable cognitive radio system according to a second embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
First embodiment
Referring to fig. 1, embodiments of the present application provide a scalable cognitive radio system that includes a heterogeneous computing platform, a radio front end, and a serial adapter. The heterogeneous computing platform comprises a Central Processing Unit (CPU) and a first processor for processing parallel computing tasks, and the CPU is connected with the first processor. The radio front end comprises an analog-digital/digital-analog converter, a radio frequency signal input/output channel and a second processor used for preprocessing data, wherein the analog-digital/digital-analog converter is respectively connected with the second processor and the radio frequency signal input/output channel. The serial adapter comprises a first FPGA chip which is in communication connection with the central processing unit and the second processing unit through the high-speed serial port.
Specifically, the radio frequency signal input/output channel of the radio front end comprises a radio frequency signal input channel and a radio frequency signal output channel, an analog-to-digital converter is arranged between the radio frequency signal input channel and the second processor, a digital-to-analog converter is arranged between the radio frequency signal output channel and the second processor, an analog quantity signal input by the radio frequency signal input channel can be converted into a digital signal by arranging the analog-to-digital converter between the radio frequency signal input channel and the second processor so that the second processor and the heterogeneous computing platform can carry out operation, and the digital signal sent by the heterogeneous computing platform can be converted into the analog signal to be output by arranging the digital-to-analog converter between the radio frequency signal output channel and the second processor. Meanwhile, the radio front end also comprises a first memory, and the first memory is connected with the second processor.
In the embodiment of the application, the second processor is used for preprocessing data to preprocess high-speed stream data from the analog-to-digital converter, and the preprocessing includes but is not limited to signal interception, signal compression, digital frequency conversion, filtering, extraction and the like to greatly reduce the data volume, and then the data volume is sent to a heterogeneous computing platform for centralized processing, so that the computing capacity can be distributed to the front end, the data transmission efficiency is improved, the expandable capacity and the channel number of the system are increased, and finally the cognitive function of the system is improved.
The second processor can be a Field Programmable Gate Array (FPGA) or can be formed by integrating the FPGA with an ARM processor. In the embodiment of the application, the second processor is formed by integrating a field programmable gate array and an ARM processor.
The heterogeneous computing platform includes a central Processing Unit and a first processor for Processing a parallel computing task, where the first processor may be, but is not limited to, a Graphics Processing Unit (GPU), a Neural-Network Processing Unit (NPU), and the first processor may be a stand-alone chip or may be integrated in the central Processing Unit. With the development of semiconductor technology, integrated central processing units have become increasingly popular, and the performance has completely exceeded the processing capability of conventional DSPs, the first processor can be integrated in the central processing unit, while providing high performance computing capability and low power consumption level, creating the possibility for the construction of high performance portable and embedded applications. In addition, a stand-alone graphics acceleration processor or a neural network processor, such chips may be connected to the central processor with PCIe Gen3, Gen4, or higher speed buses, ensuring high bandwidth data throughput capability. In addition, to meet radio development requirements, the central processor may be configured as a high frequency processor with more than 4 cores, and the graphics acceleration processor or the neural network processor may employ single precision floating point computing power with more than 1 TFLOPS.
The heterogeneous computing platform has one or more high-speed serial ports for connecting the radio front-end through a serial adapter, which may employ, but is not limited to, Thunderbolt 3, Thunderbolt 4, or PCIe bus standards with very high data transfer rates.
The heterogeneous computing platform may run, but is not limited to, a Windows or Linux operating system, and therefore in the embodiment of the present application, the heterogeneous computing platform is further configured with a hard disk, a second memory, and a video memory according to an actual application requirement, where the hard disk and the second memory are both connected to the central processing unit, and the video memory is connected to the first processor. In addition, the heterogeneous computing platform can be also configured with a network card or a wireless network card so as to facilitate remote control and data transmission of users.
In the embodiment of the application, the first processor of the heterogeneous computing platform is a computing architecture with high parallelism, and can be used for, but not limited to, high-performance computing tasks such as deep learning, artificial intelligence and the like. The central processing unit has complex scheduling, management and logic processing capabilities, can be used for managing the whole system, and can complete a human-to-human interface and various functional tasks, such as processing task strategies, task management, a knowledge base, communication control, user interface management and the like.
The serial adapter comprises a first FPGA chip and a high-speed serial port, and is mainly used for carrying out data recombination, forwarding and protocol adaptation, and also carrying out additional work such as data preprocessing, verification and communication medium conversion under partial conditions. A high-speed communication link between the heterogeneous computing platform and the radio front-end itself may be established through the serial adapter. In addition, the serial adapter can also convert bus communication media, for example, the serial adapter is connected with a heterogeneous computing platform in a short distance through a copper cable, and is connected with a radio front end through an optical cable, and the length of an optical fiber can be as long as hundreds of meters, so that the construction mode of the cognitive radio system is expanded to a long-distance distributed architecture.
In addition, because the physical size of the high-speed serial port is usually smaller, the size and the power consumption of the system can be effectively reduced. A distributed, combined, portable and modular cognitive radio system can also be conveniently built in a manner of extending the radio front end through a serial cable.
The radio front end and the serial adapter in the extensible cognitive radio system provided by the embodiment of the application can be multiple and equal in quantity, when the radio front end and the serial adapter are multiple, the radio front ends correspond to the serial adapters one by one, and a first FPGA chip of the serial adapter is in communication connection with the central processing unit and the corresponding second processor through the high-speed serial port. Fig. 2 is a schematic structural diagram of a cognitive radio system in a case where 2 radio front ends and 2 serial adapters are provided according to the embodiment of the present application.
Further, a synchronous signal transmission mechanism can be adopted among the plurality of radio front ends, and synchronous signals include, but are not limited to, GPS signals, beidou positioning signals, pulse per second signals, external trigger signals, local oscillator signal output/input, reference clock signals and the like. The synchronous type transmission mechanism is applied to multi-channel coherent, such as an MIMO system, a digital array system and the like, and can provide channel expansion support.
In the embodiment of the application, the digital-to-analog converters and the radio frequency signal output channels are multiple and same in number, the digital-to-analog converters are connected with the radio frequency signal output channels in a one-to-one correspondence manner, the analog-to-digital converters and the radio frequency signal input channels are multiple and same in number, and the analog-to-digital converters are connected with the radio frequency signal input channels in a one-to-one correspondence manner.
The data processing process of the scalable cognitive radio system is as follows:
firstly, synchronous sampling records of input and output channels of the radio front end are established through synchronous signals, all analog-to-digital converters of the radio front end synchronously acquire signals, and the digitized signals are transmitted to a second processor of the radio front end to be preprocessed (such as signal interception, signal compression, digital frequency conversion, filtering, extraction and the like). The preprocessed data are synchronously gathered to the heterogeneous computing platform through the serial adapter, after the heterogeneous computing platform obtains signals of all radio front ends through computing, the signals are uniformly scheduled by the central processing unit, the central processing unit and the first processor complete high-speed data computing, results are fed back and output, the fed back and output results are distributed to all the radio front ends through the serial adapter to be sent out, exist on hard disks of the heterogeneous computing platform, are further transmitted to other systems through a network, and the like.
In summary, the extensible cognitive radio system provided in the embodiment of the present application can preprocess high-speed stream data from the analog-to-digital converter by arranging the second processor at the radio front end, so as to greatly reduce the data volume and improve the throughput and signal processing capability of the data. Secondly, since a plurality of radio front ends can be expanded according to specific application requirements by providing the serial adapter, flexible channel expansion capability is provided. In addition, the size and the power consumption of the system can be effectively reduced by arranging the serial adapter, and a distributed, combined, portable and modularized cognitive radio system can be conveniently built, so that theories and algorithms can be quickly verified, and the project research and development period is shortened.
Second embodiment
Referring to fig. 3, an embodiment of the present application is a further improvement of the scalable cognitive radio system shown in fig. 2, and unlike the embodiment shown in fig. 2, the scalable cognitive radio system provided in the embodiment of the present application includes only one serial adapter, where the serial adapter is provided with 3 high-speed serial ports, and is communicatively connected to the first processor and the second processor of the 2 radio front ends through the 3 high-speed serial ports, respectively.
It will be appreciated that in the case where a serial adapter is provided, as the number of radio front ends increases, so does the high speed serial ports of the serial adapter.
Referring to fig. 4, an embodiment of the present application further provides another scalable cognitive radio system, and different from the scalable cognitive radio system shown in fig. 3, the heterogeneous computing platform further includes a second FPGA chip, and the second FPGA chip is connected between the central processing unit and the first FPGA chip of the serial adapter. The second FPGA chip is used for collecting data and preprocessing part of collected data so as to solve the problem that the first FPGA chip in the serial adapter cannot collect data and preprocess the collected data.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A scalable cognitive radio system, comprising:
the heterogeneous computing platform comprises a central processing unit and a first processor for processing parallel computing tasks, and the central processing unit is connected with the first processor;
the radio front end comprises an analog-digital/digital-analog converter, a radio frequency signal input/output channel and a second processor for preprocessing data, wherein the analog-digital/digital-analog converter is respectively connected with the second processor and the radio frequency signal input/output channel;
the serial adapter comprises a first FPGA chip, and the first FPGA chip is in communication connection with the central processing unit and the second processing unit through high-speed serial ports respectively.
2. The scalable cognitive radio system of claim 1, wherein the first processor is a neural network processor or a graphics acceleration processor.
3. The scalable cognitive radio system of claim 1, wherein the second processor is a field programmable gate array.
4. The scalable cognitive radio system of claim 1, wherein the second processor comprises a field programmable gate array and an ARM processor, the field programmable gate array and the ARM processor integrated to form the second processor.
5. The scalable cognitive radio system according to claim 1, wherein the number of the radio front ends and the number of the serial adapters are equal, the number of the radio front ends corresponds to the number of the serial adapters one by one, and the first FPGA chips of the serial adapters are respectively in communication connection with the central processor and the corresponding second processors through high-speed serial ports.
6. The scalable cognitive radio system of claim 5, wherein signal acquisition and generation are synchronized between a plurality of said radio front ends.
7. The scalable cognitive radio system according to claim 1, wherein the number of the radio front ends is multiple, and the first FPGA chip of the serial adapter is communicatively connected to the central processor and the second processors of the plurality of radio front ends respectively via high-speed serial ports.
8. The scalable cognitive radio system of claim 1, wherein the heterogeneous computing platform further comprises a second FPGA chip, the second FPGA chip connected between the central processor and the first FPGA chip.
9. The scalable cognitive radio system of claim 1, wherein the radio front end further comprises a first memory, the first memory coupled to the second processor.
10. The scalable cognitive radio system of claim 1, wherein the heterogeneous computing platform further comprises a hard disk, a second memory and a video memory, the hard disk and the second memory are both connected to the central processing unit, and the video memory is connected to the first processor.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116680221A (en) * | 2022-11-04 | 2023-09-01 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116680221A (en) * | 2022-11-04 | 2023-09-01 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
| CN116680221B (en) * | 2022-11-04 | 2024-03-26 | 成都立思方信息技术有限公司 | Distributed high-speed signal receiving and transmitting processing system |
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