CN115509970A - FPGA multichannel high-speed signal acquisition and processing module - Google Patents

FPGA multichannel high-speed signal acquisition and processing module Download PDF

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Publication number
CN115509970A
CN115509970A CN202211252657.8A CN202211252657A CN115509970A CN 115509970 A CN115509970 A CN 115509970A CN 202211252657 A CN202211252657 A CN 202211252657A CN 115509970 A CN115509970 A CN 115509970A
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unit
communication
units
fpga
communication unit
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CN202211252657.8A
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李怀良
干超迪
何昕
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Chengdu Univeristy of Technology
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Chengdu Univeristy of Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

The invention discloses an FPGA multichannel high-speed signal acquisition processing module, which comprises an ARM main control unit, an FPGA unit, a multichannel high-speed communication unit, a register unit and a plurality of communication units, wherein the ARM main control unit comprises an FSMC controller; the communication units comprise a plurality of RS232 communication units, a plurality of RS422 communication units and a plurality of RS485 communication units, wherein the RS232 communication units are in a group, the RS422 communication units are in a group, and the RS485 communication units are in a group; the FPGA unit comprises an FIFO buffer unit and a register unit; the multichannel high-speed communication unit includes: the device comprises a plurality of transmission processing units and a plurality of acquisition control units, wherein each acquisition control unit comprises a plurality of ADC acquisition channels, a plurality of conditioning circuits, a corresponding FPGA unit and a plurality of sensor modules. The data transmission rate of the multifunctional communication module is improved, and the transmission quality is further improved while high-speed transmission is guaranteed.

Description

FPGA multichannel high-speed signal acquisition and processing module
Technical Field
The invention relates to the technical field of signal processing, in particular to an FPGA (field programmable gate array) multi-channel high-speed signal acquisition and processing module.
Background
At present, the environment of the communication equipment is complex, and communication interfaces among different equipment and each equipment comprise RS485, RS422, RS232 and the like. With the continuous development and application of ARM and FPGA field editable logic gate arrays and DSP digital signal processing technologies, signal data acquisition and processing technologies are developed rapidly. In recent years, with the continuous development of industries, the requirements on communication safety and reliability are higher and higher, and meanwhile, the communication interfaces of various monitoring instruments need to be matched with the communication interfaces of components to be tested or communication buses. At present, the multichannel high-speed signal acquisition and processing modules capable of meeting the requirements are rare.
The multi-channel high-speed signal acquisition and processing module can meet the requirement of high-speed signals on multi-channel expansion while ensuring that various communication devices can normally transmit data, and effectively forms a larger signal acquisition system, but the signal acquisition and processing system has the functions of signal acquisition, real-time processing, digital filter bandwidth selection, user interaction parameter setting and the like, and also has the functions of supporting synchronous acquisition among multiple systems or multiple channels, stable data communication transmission and the like.
Disclosure of Invention
The invention aims to provide an FPGA multi-channel high-speed signal acquisition and processing module, which solves the existing problems.
In order to achieve the purpose, the invention provides the following technical scheme: an FPGA multichannel high-speed signal acquisition processing module comprises an ARM main control unit, an FPGA unit, a multichannel high-speed communication unit, a register unit and a plurality of communication units, wherein the ARM main control unit comprises an FSMC controller;
the communication units comprise a plurality of RS232 communication units, a plurality of RS422 communication units and a plurality of RS485 communication units, wherein the RS232 communication units are in one group, the RS422 communication units are in one group, and the RS485 communication units are in one group;
the FPGA unit comprises an FIFO buffer unit and a register unit;
the multichannel high-speed communication unit includes: the device comprises a plurality of transmission processing units and a plurality of acquisition control units, wherein each acquisition control unit comprises a plurality of ADC acquisition channels, a plurality of conditioning circuits, a corresponding FPGA unit and a plurality of sensor modules.
Preferably, the RS232 communication unit is further connected with an ARM single chip microcomputer, the RS422 communication unit is further connected with the ARM single chip microcomputer, the RS485 communication unit is further connected with the ARM single chip microcomputer, and the RS232 communication unit, the RS422 communication unit and the RS485 communication unit are in serial port communication with the ARM single chip microcomputer;
the RS232 communication unit is used for being connected with an external RS232 interface, the RS422 communication unit is used for being connected with an external RS422 interface, and the RS485 communication unit is used for being connected with an external RS485 interface.
Preferably, the FIFO buffer units correspond to 3 groups, the memory size of each group of FIFO buffer units is 2K, the register units comprise a plurality of 16-bit registers which can be expanded, a functional memory segment space management technology is adopted inside the register units to carry out multi-channel high-speed communication unit communication, and the registers are segmented to carry out data communication control on different channel units.
Preferably, the register unit is respectively connected with the FIFO buffer unit and the FSMC controller, the register unit and the FIFO buffer unit are connected with the multi-channel high-speed communication unit, and the FIFO buffer unit is configured to buffer data transmitted from an external interface to the communication unit and to buffer data transmitted from an external interface to the communication unit.
Preferably, the plurality of ADC acquisition channels are in communication connection with the FPGA unit, and the FPGA unit is electrically connected with the transmission processing unit through a multi-channel SPI bus;
the sensor modules are respectively connected with the conditioning circuit, and the corresponding FPGA units are in communication connection with the sensor modules.
Compared with the prior art, the invention has the following beneficial effects:
the invention reduces the circuit volume, reduces the hardware cost, ensures the stable and reliable communication of the serial port, and fully utilizes the characteristics of high running speed of FPGA parallel processing, an on-chip oscillator and rich on-chip resources.
The multi-channel high-speed signal acquisition processing module connects the register unit with the multi-channel high-speed communication module through an asynchronous FIFO cache function, coordinates to work, and realizes the functions together, and distributes and integrates data through instructions in the FPGA under the control of the instruction receiving and control module through the SPI bus control, so as to realize the multi-channel acquisition processing of high-speed signals; in addition, as the data volume is large, the problem of unmatched transmission rate between the ARM main control unit and the FPGA unit can exist, and the problem of unmatched transmission rate is solved by establishing an FIFO cache unit in the FPGA unit;
compared with the traditional parallel or serial communication mode, the data transmission speed of the multifunctional communication module is improved, and the transmission quality is further improved while high-speed transmission is guaranteed.
Drawings
FIG. 1 is a system connection diagram provided by the present invention;
FIG. 2 is a block diagram of a multi-channel high-speed communication unit provided by the present invention;
FIG. 3 is a diagram of a transmission processing unit according to the present invention;
FIG. 4 is an internal structure diagram of the FPGA provided by the present invention;
fig. 5 is a flowchart of a multi-channel high-speed signal processing and collecting method provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
As shown in fig. 1, fig. 2, fig. 3 and fig. 4, an FPGA multi-channel high-speed signal acquisition and processing module includes an ARM main control unit, an FPGA unit, a multi-channel high-speed communication unit, a register unit, and a plurality of communication units, wherein the ARM main control unit includes an FSMC controller;
the communication units comprise a plurality of RS232 communication units, a plurality of RS422 communication units and a plurality of RS485 communication units, wherein the RS232 communication units are in one group, the RS422 communication units are in one group, and the RS485 communication units are in one group;
the RS232 communication unit is also connected with the ARM singlechip, the RS422 communication unit is also connected with the ARM singlechip, the RS485 communication unit is also connected with the ARM singlechip, and the RS232 communication unit, the RS422 communication unit and the RS485 communication unit are communicated with the ARM singlechip through serial ports;
the RS232 communication unit is used for being connected with an external RS232 interface, the RS422 communication unit is used for being connected with an external RS422 interface, and the RS485 communication unit is used for being connected with an external RS485 interface;
the FPGA unit comprises an FIFO buffer unit and a register unit, the register unit is respectively connected with an FIFO cache unit and an FSMC controller, the register unit and the FIFO buffer unit are connected with a multi-channel high-speed communication unit, the FIFO cache unit is used for caching data transmitted to the communication unit from an external interface and caching data transmitted to the communication unit from the external interface, the FIFO cache units correspond to 3 groups, the memory size of each group of FIFO buffer units is 2K, the register unit comprises a plurality of expandable 16-bit registers, a function memory segment space management technology is adopted in the register unit to realize multi-channel high-speed communication unit communication, and the registers are segmented to realize data communication control of different channel units;
the multichannel high-speed communication unit includes: the multifunctional communication module comprises a plurality of transmission processing units and a plurality of acquisition control units, wherein each acquisition control unit comprises a plurality of ADC acquisition channels, a plurality of conditioning circuits, a corresponding FPGA unit and a plurality of sensor modules, and can realize data communication of each device and a communication bus.
As shown in fig. 2, fig. 3 and fig. 4, further, a plurality of ADC acquisition channels are connected to the communication unit, the FPGA unit is electrically connected to the transmission processing unit through a multi-channel SPI bus, the multi-channel SPI bus can transmit signal data of the plurality of ADC acquisition channels respectively, and mutual interference between signal acquisition and transmission between super-channels can be realized, so that signal acquisition and delay acquisition of the super-channels are realized, data communication between a plurality of acquisition control units in parallel and based on the multi-channel SPI bus and the transmission processing unit can be realized, so that data transmission efficiency is improved, and a large data volume of a high-speed signal acquisition system can be realized, so that a real-time processing technical problem of a large data volume can be solved;
the sensor module is connected with the conditioning circuit respectively, corresponds FPGA unit and sensor module communication connection, every transmission processing unit can support a plurality of collection control units to carry out data communication, and transmission processing unit packs the data that obtain simultaneously, and collection control unit adopts FPGA + ADC's framework, and multichannel analog signal is after ADC acquisition channel high-speed sampling, and it is average to add up parallelly in the input FPGA unit, and the FPGA unit is with the data after handling through multichannel SPI bus transmission to transmission processing unit and handle.
As shown in fig. 5, the multi-channel high-speed signal processing and collecting method specifically includes the following steps:
step 1, after the FPGA multi-channel high-speed signal acquisition and processing module is powered on, a data processing and ARM central control unit is initialized;
step 2, receiving a system control instruction sent by the system to prepare for data acquisition;
step 3, transmitting a system control instruction to an internal logic processing unit of the FPGA;
step 4, controlling the operation of the sensor module and the ADC acquisition channel according to the control instruction;
step 5, sending the received signal to a conditioning circuit for processing;
step 6, sending the conditioned signal data to an ADC acquisition channel for analog-to-digital conversion to obtain corresponding digital signal data;
step 7, sending the digital signal data to a register through the FPGA, a multi-channel SPI bus, a processing unit, a switch and an asynchronous FIFO;
and 8, the ARM main control unit sends the data in the register through corresponding RS232, RS422 and RS485 communication units respectively according to needs to finish the acquisition and transmission of the data.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (5)

1. An FPGA multichannel high-speed signal acquisition processing module is characterized by comprising an ARM main control unit, an FPGA unit, a multichannel high-speed communication unit, a register unit and a plurality of communication units, wherein the ARM main control unit comprises an FSMC controller;
the communication units comprise a plurality of RS232 communication units, a plurality of RS422 communication units and a plurality of RS485 communication units, wherein the RS232 communication units are in a group, the RS422 communication units are in a group, and the RS485 communication units are in a group;
the FPGA unit comprises an FIFO buffer unit and a register unit;
the multichannel high-speed communication unit includes: the device comprises a plurality of transmission processing units and a plurality of acquisition control units, wherein each acquisition control unit comprises a plurality of ADC acquisition channels, a plurality of conditioning circuits, a corresponding FPGA unit and a plurality of sensor modules.
2. The FPGA multi-channel high-speed signal acquisition and processing module of claim 1, wherein the RS232 communication unit is further connected with an ARM single chip microcomputer, the RS422 communication unit is further connected with the ARM single chip microcomputer, the RS485 communication unit is further connected with the ARM single chip microcomputer, and serial port communication is adopted among the RS232 communication unit, the RS422 communication unit, the RS485 communication unit and the ARM single chip microcomputer;
the RS232 communication unit is used for being connected with an external RS232 interface, the RS422 communication unit is used for being connected with an external RS422 interface, and the RS485 communication unit is used for being connected with an external RS485 interface.
3. The FPGA multi-channel high-speed signal acquisition processing module according to claim 1, wherein the FIFO buffer units are corresponding to 3 groups, each group of FIFO buffer units has a memory size of 2K, the register unit comprises a plurality of 16-bit registers which can be expanded, and adopts a functional memory segment space management technology internally to implement multi-channel high-speed communication unit communication, and the registers are segmented to implement data communication control of different channel units.
4. The FPGA multichannel high-speed signal acquisition and processing module according to claim 1, wherein the register unit is connected to the FIFO buffer unit and the FSMC controller, respectively, and the register unit and the FIFO buffer unit are connected to the multichannel high-speed communication unit, and the FIFO buffer unit is configured to buffer data transmitted from an external interface to the communication unit, and is configured to buffer data transmitted from an external interface to the communication unit.
5. The FPGA multichannel high-speed signal acquisition and processing module according to claim 1, wherein a plurality of the ADC acquisition channels are in communication connection with the transmission processing unit, and the FPGA unit is electrically connected with the transmission processing unit through a multichannel SPI bus;
the sensor modules are respectively connected with the conditioning circuit, and the corresponding FPGA units are in communication connection with the sensor modules.
CN202211252657.8A 2022-10-13 2022-10-13 FPGA multichannel high-speed signal acquisition and processing module Pending CN115509970A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116481599A (en) * 2023-06-25 2023-07-25 珠海矽敏科技有限公司 Multichannel signal acquisition device and sensor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116481599A (en) * 2023-06-25 2023-07-25 珠海矽敏科技有限公司 Multichannel signal acquisition device and sensor system

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