CN107367985A - A kind of Multichannel Real-time Data Acguisition System - Google Patents
A kind of Multichannel Real-time Data Acguisition System Download PDFInfo
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- CN107367985A CN107367985A CN201710626066.5A CN201710626066A CN107367985A CN 107367985 A CN107367985 A CN 107367985A CN 201710626066 A CN201710626066 A CN 201710626066A CN 107367985 A CN107367985 A CN 107367985A
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- fpga controller
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Abstract
The invention discloses a kind of Multichannel Real-time Data Acguisition System,Including FPGA controller and data transmission module,The bidirectional port of the FPGA controller is electrically connected with three A/D converters by control line,Wherein described two A/D converters receive the control signal after signal conditioning circuit is handled,Switching signal after another A/D converter reception signal conditioning processing of circuit,The control signal of passage is directly over after signal condition being gathered by two A/D change-over circuits parallel high-speeds respectively,And the multi-way control signals of other passages are selected by variable connector,Board area and hardware resource are saved,The output end of the FPGA controller is connected by LVDS high-speed serial communications circuit with data transfer FPGA control circuit,Feedback data directly realizes data interaction by the communications of RS 422 with multi-shaft motion control system itself,Realized at a high speed to main control computer by pci bus high-speed transfer,The Data Detection of Large Copacity,Improve the efficiency of data processing.
Description
Technical field
The present invention relates to data collecting system technical field, specially a kind of Multichannel Real-time Data Acguisition System.
Background technology
Modern Motion Control turns into Electrical Motor, Power Electronic Technique, microelectric technique, Computer Control Technology, control
The cross one another comprehensive branch of learning of multi-door subject such as theoretical, signal detection and treatment technology.Multiaxis fortune control technology is integrated with existing
It is the core of manufacturing industry digitlization, the modernization of industry and Automation of Manufacturing Process for numerous key technologies of motion control field.
Multi-shaft interlocked control system uses advanced Multi-axis motion control technology, adds in multi-shaft linkage numerical control machine, multi-axis linkage numerical control
Work center, multiple degrees of freedom industrial robot, complicated automatic industrial manufacturing line and aerospace field extensive application.State
It is various, self-contained more that inside and outside numerous enterprises, the needs of scientific research institutions' combination production and the demand of scientific research develops species
Axle coordinated control system.
Application and popularizations and performance boost along with multi-shaft interlocked control system, there is an urgent need to develop corresponding test to set
It is standby, the critical performance parameters of multi-shaft interlocked control system are detected, monitor its working condition.Traditional detection means relies on oscillography
The equipment such as device, logic analyser, there is the signal of detection is few, poor real, the short monitoring time the deficiencies of.As computer is imitated
The development of true technology, modeling and simulation technology, electronics technologies, the performance of kinetic control system test equipment improve constantly, work(
Can be increasingly perfect.But the deficiency of such test equipment is：The signalling channel number of collection is single, can not parallel acquisition it is more logical
Road signal, message transmission rate are relatively low, it is impossible to meet high speed, real-time, multi-channel parallel detection multi-shaft interlocked control system work
The demand of state.
The content of the invention
To achieve the above object, the present invention provides following technical scheme：A kind of Multichannel Real-time Data Acguisition System, including
FPGA controller and data transmission module, the bidirectional port of the FPGA controller are electrically connected with three A/D by control line and turned
Parallel operation, wherein described two A/D converters receive the control signal after signal conditioning circuit is handled, another A/D conversions
Switching signal after device reception signal conditioning processing of circuit, input and the multiplexer (MUX phase of the signal conditioning circuit
Connection, the output end of the FPGA controller are connected by LVDS high-speed serial communications circuit with data transfer FPGA control circuit
Connect, the storage end of the FPGA controller is also connected by control line with fifo memory circuit, the fifo memory circuit
Data terminal is connected with SDRAM memory, and the signal end of the FPGA controller passes through RS422 receivers and multi-shaft interlocked control
System is connected, and the data transfer FPGA control circuit is built-in with data transmission module, the output of the data transmission module
End is electrically connected with by control line and interface circuit, and the output end of the interface circuit passes through pci bus and main control computer phase
Connection.
As a kind of preferable technical scheme of the present invention, the multi-shaft interlocked control system is built-in with multiple Parallel Control lists
Member, the control signal that described control unit exports pass to data collecting card, the number after being handled by signal pre-processing circuit
It is connected according to the signal end of capture card with data processor, the signal processor is built-in with buffer unit, the signal transacting
The output end of device is connected by pci bus with main control computer.
As a kind of preferable technical scheme of the present invention, the output end of the signal processor passes through RS-422 communication modules
FPDP of the feedback link to control unit.
As a kind of preferable technical scheme of the present invention, the input of the FPGA controller is additionally provided with Ethernet mould
Block, the ethernet module are connected by RJ45 interfaces with host computer.
As a kind of preferable technical scheme of the present invention, the signal end of the SDRAM memory also passes through control line and number
It is electrically connected with according to transmission FPGA control circuit.
As a kind of preferable technical scheme of the present invention, two are offered on the A/D converter for receiving control signal
Signal conditioning circuit control port.
As a kind of preferable technical scheme of the present invention, the output end of the FPGA controller is also electrically connected with LCD liquid crystal
Display screen.
Compared with prior art, the beneficial effects of the invention are as follows：The Multichannel Real-time Data Acguisition System, is adjusted by signal
Reason circuit and multi-way switch circuit receive control signal jointly, for different passage demands, are provided with three A/D converters,
The condition of 16 passages and the average 4 road working signal concurrent workings of each passage can at most be met.The control signal of passage
It is directly over after signal condition being gathered by two A/D change-over circuits parallel high-speeds respectively, saves switch conversion time and delay,
It is adapted to high-speed signal acquisition；And the multi-way control signals of other passages are selected by variable connector, then carry out signal condition and A/D
Conversion, has saved board area and hardware resource, has reduced cost, the collection of low speed signal in being adapted to.The letter of A/D change-over circuits
Number sample frequency is not less than 1MHz, and can pass through master control FPGA programmings and set.Therefore, signal sampling channel number, every passage
Working signal number and signal sampling frequencies all meet system performance index requirement, and also control multiaxis to join by FPGA controller
Autocontrol system, the driving power by the use of multi-shaft interlocked control system as multi-way contral signal, and signal is located in advance
The characteristic such as reason, the amplitude of conditioned signal, bandwidth, is then exported at data by data acquisition circuit high speed acquisition, collection result
Circuit is managed, carries out the analyzing and processing of signal, detection data are extracted in the result after processing and feedback data, feedback data are direct
Data interaction is realized with multi-shaft motion control system itself by RS-422 communications, the caching list inside by data processor
Member is cached to data, and high speed, the Data Detection of Large Copacity are being realized to main control computer by pci bus high-speed transfer,
Improve the efficiency of data processing.
Brief description of the drawings
Fig. 1 is schematic structural view of the invention.
Fig. 2 is multi-shaft interlocked control system structure diagram of the present invention.
Fig. 3 is signal conditioning circuit figure of the present invention.
Fig. 4 is signal pre-processing circuit figure of the present invention.
In figure：1-FPGA controllers；2- data transmission modules；3-A/D converters；4- signal conditioning circuits；5- multichannels are opened
Close selector；6- multi-shaft interlocked control systems；7-RS422 receivers；8- LCDs；9-FIFO storage circuits；10-
SDRAM memory；11- interface circuits；12- main control computers；13- ethernet modules；14- host computers；15- control units；16-
Signal pre-processing circuit；17- data collecting cards；18- signal processors.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The explanation of following embodiment is refer to the attached drawing, can be to the specific embodiment implemented to the example present invention.
The direction and position term that the present invention is previously mentioned, for example, " on ", " in ", " under ", "front", "rear", "left", "right", " interior ", "
Outside ", " side " etc., only it is direction and position with reference to annexed drawings.Therefore, the direction and position term used is to illustrate
And understand the present invention, and it is not used to the limitation present invention.
Embodiment：
Fig. 1 to Fig. 4 is referred to, the present invention provides a kind of technical scheme：A kind of Multichannel Real-time Data Acguisition System, including
FPGA controller 1 and data transmission module 2, the FPGA controller 1 is using the FPGA of Spartan-3 series as pci data
Transmission control FPG, for realizing PCI9054 Interface Controllers, the control of SDRAM read-write operations and LVDS interface control, the FPGA
The bidirectional port of controller 1 is electrically connected with three A/D converters 3 by control line, wherein described two A/D converters 3 receive
Control signal after the processing of signal conditioning circuit 4, another A/D converter reception signal nurse one's health the switch after processing of circuit
Signal, the A/D converter select acp chip of the Max1308 chips as signal acquisition circuit, support the same of up to 8 passages
When sample, high using precision, the input of the signal conditioning circuit is connected with multiplexer (MUX 5, and the multichannel is opened
Variable connector of the selector 5 using ADG508 models is closed, its dynamic characteristic is preferable, switch conversion time 100ns or so, opens electricity
Hinder 150 Ω or so.In multi-channel signal acquiring processing system, when the port number of work is more than 4, passage 1-4 4 passages 16
Road signal is directly output to signal sample circuit after pretreatment；And other up to 48 road signals by 68 select 1 it is more
Way switch ADG508, then export to signal sample circuit.
The A/D converter is controlled to three A/D conversion chips MAX1308, and sending signal in main control computer adopts
After collecting sign on, A/D conversions are started by master control FPGA execute instructions, transformation result exports to be carried out to Data Analysis Services module
Follow-up analyzing and processing.A/D converter is divided into control signal, output data pin two parts, wherein, control signal includes sampling
Clock A/D change over clocks, conversion start, conversion end, last passage conversion end, data reading and data writing etc.；Output
Data pins include the output result of each passage.
The output end of the FPGA controller 1 is connected by LVDS high-speed serial communications circuit with data transmission module 2,
Pass through LVDS communication high-speed transfer main control computers descending control instruction and up detection data, the FPGA controller 1
Storage end be also connected by control line with fifo memory circuit 9, the data terminal of the fifo memory circuit 9 is deposited with SDRAM
Reservoir 10 is connected, and the signal end of the FPGA controller 1 is connected by RS422 receivers 7 with multi-shaft interlocked control system 6
Connect, be controlled instruction using RS-422 serial communications interacts with feedback data, and the mechanism controlled is：First, controlled by outside
System processed is by the descending control instruction of RS-422 serial ports, including sets the type of feedback, the passage of closed-loop control；Then, once
The instruction of the descending open signal collection of main control computer, master control FPGA in time can send the feedback data of generation to outside and control
System processed, realizes closed-loop control；If feedback kind is arranged to " feedback-less ", external system uses opened loop control, it is not necessary to
Feedback data is serially sent by RS-422, the output end of the data transmission module 2 passes through control line and the electricity of interface circuit 11
Property connection, the output end of the interface circuit 11 is connected by pci bus with main control computer 12, and the interface circuit 11 is adopted
By the use of PCI9054 as interface chip come realize pci bus communication unit the characteristics of and implementation method.
As shown in Figure 1 and Figure 4：The multi-shaft interlocked control system 6 is built-in with multiple control units 15 being connected in parallel, institute
The control signal of the output of control unit 15 is stated by passing to data collecting card 17, the number after the processing of signal pre-processing circuit 16
It is connected according to the signal end of capture card 17 with data processor 18, the signal processor 18 is built-in with buffer unit, the letter
The output end of number processor 18 is connected by pci bus with main control computer 12；The operating voltage of the A/D converter 3 for-
10V~+10V, and the usual voltage of drive signal of multichannel coordinated control system is 0-32V, therefore modelled signal pretreatment electricity
Road 16 pre-processes to control signal, and amplitude, the bandwidth of conditioned signal meet the needs of subsequent conditioning circuit, pass through Signal Pretreatment
Circuit 16 realizes the partial pressure of signal, clamper protection, amplifier, active low-pass filter and variable connector selection function, amplifier and
Low-pass filter circuit.
Data of the output end of the signal processor 18 by RS-422 communication modules feedback link to control unit 15
Port；The input of the FPGA controller 1 is additionally provided with ethernet module 13, and the ethernet module 13 passes through RJ45 interfaces
It is connected with host computer 14；The signal end of the SDRAM memory 10 is also electrically connected by control line and data transmission module 2
Connect；Two signal conditioning circuit control ports are offered on the A/D converter 3 for receiving control signal；The FPGA controls
The output end of device 1 is also electrically connected with LCDs 8.
The fifo memory circuit 9 of the present invention is directed to, because the sampled result parallel output of signal acquisition circuit is to master control
FPGA, data analysis and processing are carried out after FPGA is cached, sequentially generate the data of feedback data and 32Byte detection data
Bag.During multi-channel parallel acquisition process, each control signal pulses generation of each passage detect packet accordingly, it is necessary to
High speed, the data storage of Large Copacity are realized, therefore FIFO, high speed storing data, with this are used in master control FPGA control circuit
Meanwhile pci data transmit FPGA control circuit in using Large Copacity SDRAM store, realize design in buffer memory capacity with
And the demand of read or write speed.
Specifically used mode and advantage：The Multichannel Real-time Data Acguisition System, is opened by signal conditioning circuit and multichannel
Powered-down road receives control signal jointly, for different passage demands, is provided with three A/D converters, can at most meet 16
Individual passage and the condition of the average 4 road working signal concurrent workings of each passage.The control signal of passage is directly over signal tune
Gathered respectively by two A/D change-over circuits parallel high-speeds after reason, save switch conversion time and delay, suitable high speed signal are adopted
Collection；And the multi-way control signals of other passages are selected by variable connector, then signal condition and A/D conversions are carried out, saved plate
Card area and hardware resource, reduce cost, the collection of low speed signal in being adapted to.The signal sampling frequencies of A/D change-over circuits are not
Less than 1MHz, and it can be programmed and set by master control FPGA.Therefore, signal sampling channel number, per channels operation signal number with
Signal sampling frequencies all meet system performance index requirement, and also control multi-shaft interlocked control system by FPGA controller,
Driving power by the use of multi-shaft interlocked control system as multi-way contral signal, and signal is pre-processed, conditioned signal
Amplitude, the characteristic such as bandwidth, then by data acquisition circuit high speed acquisition, collection result is exported to data processing circuit, is carried out
The analyzing and processing of signal, detection data are extracted in the result after processing and feedback data, feedback data directly pass through RS-422
Communication realizes data interaction with multi-shaft motion control system itself, and the buffer unit inside by data processor enters to data
Row caching, high speed, the Data Detection of Large Copacity are being realized to main control computer by pci bus high-speed transfer, improving data
The efficiency of processing.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires rather than described above limits, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as to the involved claim of limitation.
Claims (7)
- A kind of 1. Multichannel Real-time Data Acguisition System, it is characterised in that：Including FPGA controller (1) and data transmission module (2), the bidirectional port of the FPGA controller (1) is electrically connected with three A/D converters (3) by control line, wherein described two Individual A/D converter (3) receives the control signal after signal conditioning circuit (4) processing, another A/D converter reception signal Switching signal after modulate circuit processing, the input of the signal conditioning circuit are connected with multiplexer (MUX (5), institute The output end for stating FPGA controller (1) is connected by LVDS high-speed serial communications circuit with data transmission module (2), described The storage end of FPGA controller (1) is also connected by control line with fifo memory circuit (9), the fifo memory circuit (9) Data terminal be connected with SDRAM memory (10), the signal end of the FPGA controller (1) by RS422 receivers (7) with Multi-shaft interlocked control system (6) is connected, and the output end of the data transmission module (2) passes through control line and interface circuit (11) It is electrically connected with, the output end of the interface circuit (11) is connected by pci bus with main control computer (12).
- A kind of 2. Multichannel Real-time Data Acguisition System according to claim 1, it is characterised in that：The multi-shaft interlocked control System (6) processed is built-in with multiple control units (15) being connected in parallel, and the control signal of described control unit (15) output passes through Data collecting card (17), the signal end and data of the data collecting card (17) are passed to after signal pre-processing circuit (16) processing Processor (18) is connected, and the signal processor (18) is built-in with buffer unit, the output end of the signal processor (18) It is connected by pci bus with main control computer (12).
- A kind of 3. Multichannel Real-time Data Acguisition System according to claim 2, it is characterised in that：The signal processor (18) FPDP that output end passes through RS-422 communication modules feedback link to control unit (15).
- A kind of 4. Multichannel Real-time Data Acguisition System according to claim 1, it is characterised in that：The FPGA controller (1) input is additionally provided with ethernet module (13), and the ethernet module (13) passes through RJ45 interfaces and host computer (14) It is connected.
- A kind of 5. Multichannel Real-time Data Acguisition System according to claim 1, it is characterised in that：The SDRAM storages The signal end of device (10) is also electrically connected with by control line and data transmission module (2).
- A kind of 6. Multichannel Real-time Data Acguisition System according to claim 1, it is characterised in that：It is described to receive control letter Number A/D converter (3) on offer two signal conditioning circuit control ports.
- A kind of 7. Multichannel Real-time Data Acguisition System according to claim 1, it is characterised in that：The FPGA controller (1) output end is also electrically connected with LCDs (8).
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| CN201710626066.5A CN107367985A (en) | 2017-07-27 | 2017-07-27 | A kind of Multichannel Real-time Data Acguisition System |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107911176A (en) * | 2017-12-27 | 2018-04-13 | 长沙深之瞳信息科技有限公司 | A kind of mini signals solution tuned plate and its operating method |
| CN108345253A (en) * | 2018-05-18 | 2018-07-31 | 北京钢铁侠科技有限公司 | Brain communication system controller, control method and robot for robot |
| CN109932940A (en) * | 2017-12-15 | 2019-06-25 | 成都熠辉科技有限公司 | Multi channel signals synchronous acquisition storage system |
| CN112947170A (en) * | 2021-02-02 | 2021-06-11 | 珠海拓芯科技有限公司 | Double-fan control circuit and air conditioner |
| CN113092104A (en) * | 2021-04-09 | 2021-07-09 | 重庆大学 | System and method for detecting performance of electronic transmission chain of worm gear master machine |
| CN113607288A (en) * | 2021-06-25 | 2021-11-05 | 上海航天控制技术研究所 | High-speed large-area-array infrared imaging circuit |
| CN113703370A (en) * | 2021-09-01 | 2021-11-26 | 天津工业大学 | Multichannel high-resolution data acquisition system |
| CN113721486A (en) * | 2021-07-30 | 2021-11-30 | 中国航空工业集团公司沈阳飞机设计研究所 | Multichannel variable frequency signal acquisition system and method thereof |
| CN116734929A (en) * | 2023-08-16 | 2023-09-12 | 中北大学 | Distributed multi-parameter test system suitable for aircraft |
| CN113721486B (en) * | 2021-07-30 | 2024-04-19 | 中国航空工业集团公司沈阳飞机设计研究所 | Multichannel variable frequency signal acquisition system and method thereof |
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| CN113092104A (en) * | 2021-04-09 | 2021-07-09 | 重庆大学 | System and method for detecting performance of electronic transmission chain of worm gear master machine |
| CN113607288A (en) * | 2021-06-25 | 2021-11-05 | 上海航天控制技术研究所 | High-speed large-area-array infrared imaging circuit |
| CN113721486A (en) * | 2021-07-30 | 2021-11-30 | 中国航空工业集团公司沈阳飞机设计研究所 | Multichannel variable frequency signal acquisition system and method thereof |
| CN113721486B (en) * | 2021-07-30 | 2024-04-19 | 中国航空工业集团公司沈阳飞机设计研究所 | Multichannel variable frequency signal acquisition system and method thereof |
| CN113703370A (en) * | 2021-09-01 | 2021-11-26 | 天津工业大学 | Multichannel high-resolution data acquisition system |
| CN116734929A (en) * | 2023-08-16 | 2023-09-12 | 中北大学 | Distributed multi-parameter test system suitable for aircraft |
| CN116734929B (en) * | 2023-08-16 | 2023-11-07 | 中北大学 | Distributed multi-parameter test system suitable for aircraft |
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