CN113703370A - Multichannel high-resolution data acquisition system - Google Patents
Multichannel high-resolution data acquisition system Download PDFInfo
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- CN113703370A CN113703370A CN202111018655.8A CN202111018655A CN113703370A CN 113703370 A CN113703370 A CN 113703370A CN 202111018655 A CN202111018655 A CN 202111018655A CN 113703370 A CN113703370 A CN 113703370A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Abstract
The invention provides a multi-channel high-resolution data acquisition system. The whole system comprises a receiving board array, a main board and upper computer software, wherein the receiving board array is connected with the main board in a star structure and can be detached and recombined. The hardware circuit of the receiving board comprises a voltage lifting circuit, an ADC acquisition circuit, an FPGA core circuit and an LVDS sending circuit. The mainboard hardware circuit comprises an FPGA core circuit, an LVDS receiving circuit, a PCIE interface circuit and a receiving board slot. The acquisition system adopts the design of pre-triggering, window sampling and level jump, reduces useless signals and realizes the quick response of control signals. And the main board and the receiving board adopt an LVDS protocol for data transmission. After the main board and the receiving board FPGA controller receive data, the data are respectively stored in the SDRAM and the DDR 3. After the data is collected, the data in the DDR3 is read out, the data is uploaded to the upper computer software through the PCIE to be corrected and processed by a system, and finally, the display and storage of the data are achieved.
Description
Technical Field
The invention belongs to the field of data acquisition, and can be applied to various projects related to multichannel data acquisition to realize synchronous, real-time and high-resolution multichannel data acquisition.
Background
Data Acquisition (DAQ) refers to automatically acquiring non-electric quantity or electric quantity signals from analog and digital units to be tested, such as sensors and other devices to be tested, and sending the signals to an upper computer for analysis and processing. The data acquisition device is widely applied to the fields of communication, medical treatment, industrial automation and the like, and is a device for automatically acquiring and measuring data information from a measured target. Modern science and technology and industrial production are continuously developed, data acquisition is more widely applied to various detection fields, and a good data acquisition system is a key factor for determining excellent performance of a detection system. With the complexity of a detection target, the expansion of a detection space range and the improvement of a detection precision requirement, a high-performance multi-channel data acquisition system has an increasing demand in scientific research work and engineering application. However, due to the design difficulty and high cost of the multi-channel data acquisition system, products on the market are still rare at present, and the performance is not outstanding yet.
Disclosure of Invention
The invention provides a design scheme of a multi-channel high-resolution data acquisition system aiming at the defects of the prior data acquisition system such as few channels, low sampling rate, poor synchronism and high cost, and can realize the synchronous acquisition of multi-channel differential signals.
The invention adopts the following technical scheme:
a multichannel high-resolution data acquisition system comprises a receiving board array, a main board and upper computer software, wherein the receiving board array is composed of 5 receiving boards, the receiving board array and the main board are connected in a star-shaped structure, and disassembly and recombination can be carried out according to the actual channel number requirement.
Furthermore, the receiving board hardware circuit of the multichannel high-resolution data acquisition system comprises a voltage lifting circuit, a multichannel ADC acquisition circuit, an FPGA controller, an SDRAM module and an LVDS transmitting circuit, wherein the voltage lifting circuit is connected with a multichannel AD converter, the AD converter is connected with the FPGA controller, and the FPGA controller is connected with the SDRAM module and the LVDS transmitting circuit.
Furthermore, the main board hardware circuit of the multichannel high-resolution data acquisition system comprises an LVDS receiving circuit, an FPGA controller, a DDR3 module, a PCIE interface circuit, a power interface circuit and a receiving board slot, wherein the LVDA receiving circuit is connected with the FPGA controller, and the FPGA controller is connected with a DDR3 module and the PCIE interface circuit and is connected with upper computer software through a PCIE interface.
Furthermore, the receiving board of the multichannel high-resolution data acquisition system raises the differential input voltage to the input range of the AD converter through the voltage raising circuit, the model of the AD converter is LTC2320, the AD converter converts the input analog signal into a digital signal, and then inputs the converted digital signal into the FPGA controller of the receiving board, and the FPGA controller chip of the receiving board is Altera EP4CE22F17C 8.
Furthermore, the multichannel ADC chip of the multichannel high-resolution data acquisition system acquires multichannel differential signals, and simultaneously, by utilizing the design of pre-triggering and window sampling, the mixing of useless signals is reduced, and the data volume is reduced.
Furthermore, the receiving board stores the acquired data in an SDRAM with the model of W9825G6KH through the receiving board FPGA controller, and then uploads the data to the main board through the LVDS sending circuit, each receiving board is connected with the main board through a control signal line, and a fast response of a control signal between the main board and the receiving board is realized in a level jump manner.
Furthermore, the main board of the multichannel high-resolution data acquisition system adopts an FPGA as a main controller to control the receiving board and process data returned by the receiving board, and a chip of the FPGA controller of the main board is Xilinx-XC7A 35T.
Further, the mainboard FPGA controller of the multi-channel high-resolution data acquisition system receives the data of the receiving board and stores the data into the DDR 3.
Further, after the data are continuously collected, the data in the DDR3 are read out and uploaded to the upper computer software through the PCIE, the upper computer software receives the data returned by the PCIE bus, channel separation, waveform filtering, database backup and the like are carried out, and finally display and storage of the data are achieved.
Due to the adoption of the technical scheme, the invention has the following beneficial effects:
the invention carries out optimization design aiming at the defects of large design difficulty, high cost and unobvious performance of a multi-channel data acquisition system, each receiving board is provided with 8 ADC chips, and each ADC chip can realize the acquisition of 8-channel signals, thereby realizing the synchronous acquisition of up to 320 channel data.
The receiving board and the main board are connected by adopting a star structure, free recombination and design can be carried out according to the number of channels to be acquired, and the application places are wider.
The invention adopts various triggering modes for sampling, can realize the requirements of various measurement occasions, and can adjust the sampling window according to the factors of the pulse width and the duty ratio of the acquired signal, thereby realizing the measurement of various signals.
The invention adopts a sine histogram method to calibrate the data signals of the multi-channel data acquisition system, accurately calculates the output characteristic curve of each ADC, calculates a corresponding correction function for each ADC, and finally utilizes upper computer software to perform channel separation, waveform filtering, database backup and the like, thereby finally realizing the display and storage of waveforms.
Drawings
FIG. 1 is a general block diagram of a multi-channel high resolution data acquisition system of the present invention;
FIG. 2 is a schematic representation of a system data flow for a multi-channel high resolution data acquisition system in accordance with the present invention;
FIG. 3 is a data calibration sine histogram for a multi-channel high resolution data acquisition system according to the present invention;
FIG. 4 is a diagram of an upper computer display interface of the multi-channel high resolution data acquisition system according to the present invention.
Detailed Description
In order to make the working process and technical scheme of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the present invention has a wide application range, and the specific embodiment is only a typical application case of the present invention and is used for explaining the present invention.
As shown in fig. 1 to 4, a multichannel high-resolution data acquisition system includes a receiving board array, a main board and upper computer software, wherein the receiving board array is composed of 5 receiving boards, the receiving board array and the main board are connected by a star structure, and can be disassembled and reassembled according to the actual channel number requirement. The hardware circuit of the receiving board comprises a voltage lifting circuit, a multi-channel ADC acquisition circuit, an FPGA controller, an SDRAM module and an LVDS transmitting circuit. The mainboard hardware circuit comprises an LVDS receiving circuit, an FPGA controller, a DDR3 module, a PCIE interface circuit, a power interface circuit and a receiving board slot.
Specifically, the embodiment collects differential voltage data, a differential voltage signal is lifted to an input range of an ADC through a voltage lifting circuit, the ADC is of the LTC2320 type, 16-bit code-loss-free sampling can be achieved, 8-channel differential input and a wide common-mode range are provided, the maximum sampling rate of each channel is 1.5MSps/Ch, the differential input range can reach 8Vp _ p, and 8-channel synchronous sampling can be achieved under the condition of the maximum sampling rate by a built-in signal selector of the ADC.
Furthermore, each receiving board has 8 ADCs, each ADC can realize synchronous acquisition of 8 channels of data, and the multi-channel high-resolution data acquisition system can realize synchronous acquisition of up to 320 differential channels of data.
Further, when a channel is triggered, the main board controls the receiving board to start sampling of signals at the same time, the main control chip of the receiving board is Altera EP4CE22F17C8, the receiving board has the advantages of low power consumption, high speed and parallel execution, and then the main control chip buffers the acquired data through a write FIFO (first-in first-out memory) and stores the data into SDRAM.
Further, the triggering mode of the DAQ card may be switched as needed, including edge triggering, level triggering, conditional triggering, and the like. The DAQ card is added with the design of pre-triggering and window sampling, so that the pre-storage of signals before a trigger point is realized, the mixing of useless signals is reduced, and the data volume is reduced.
Furthermore, the receiving board reads data in the SDRAM after buffering through a read FIFO (first-in first-out memory), LVDS is used as a high-speed data transmission mode between the receiving board and the main board, an LVDS serialization factor is 8, each LVDS clock can transmit 8-bit data, and a mode of level jump is used to realize a fast response of a control signal between the main board and the receiving board. And sending a synchronous LVDS clock to the receiving board by utilizing the main board for synchronizing data streams.
Further, after the mainboard receives the data, the mainboard FPGA controller is used for buffering the data through writing in FIFO (first-in first-out memory) and then storing the data into the DDR 3. And then the data in the DDR3 is read out after the data is buffered through a read FIFO (first in first out memory). The chip of the FPGA controller of the mainboard is Xilinx-XC7A35T, and the chip has the advantages of richer logic resources, higher speed, lower power consumption and lower cost.
Furthermore, the mainboard of the multichannel high-resolution data acquisition system uploads data to the upper computer software through the PCIE bus interface.
Further, referring to fig. 3, the data calibration sine histogram of the present invention is calibrated by a sine histogram method, and the output characteristic curve of each ADC is accurately calculated, and a corresponding correction function is calculated for each ADC, and the nonlinear error of the ADC is calibrated by a cubic polynomial method. And the upper computer receives the data transmitted back by the PCIE bus, and performs channel separation, waveform filtering, database backup and the like, so that the display and storage of the data are finally realized.
The above are only specific examples of the present invention, which is used for explaining the present invention, and do not represent the application range of the present invention, and the practical application is wider. Any simple change, equivalent replacement or modification made based on the present invention to solve the substantially same technical problems and achieve the substantially same technical effects are all covered in the protection scope of the present invention.
Claims (9)
1. A multichannel high-resolution data acquisition system comprises a receiving board array, a main board and upper computer software, wherein the receiving board array is composed of 5 receiving boards, the receiving board array and the main board are connected in a star-shaped structure, and disassembly and recombination can be carried out according to the actual channel number requirement.
2. The multi-channel high-resolution data acquisition system according to claim 1, wherein the hardware circuit of the receiving board of the multi-channel high-resolution data acquisition system comprises a voltage boost circuit, a multi-channel ADC acquisition circuit, an FPGA controller, an SDRAM module, and an LVDS transmission circuit, the voltage boost circuit is connected with a multi-channel AD converter, the AD converter is connected with the FPGA controller, and the FPGA controller is connected with the SDRAM module and the LVDS transmission circuit.
3. The multi-channel high-resolution data acquisition system according to claim 1, wherein a motherboard hardware circuit of the multi-channel high-resolution data acquisition system comprises an LVDS receiving circuit, an FPGA controller, a DDR3 module, a PCIE interface circuit, a power interface circuit and a receiving board slot, the LVDA receiving circuit is connected with the FPGA controller, and the FPGA controller is connected with a DDR3 module and the PCIE interface circuit and is connected with upper computer software through a PCIE interface.
4. The multi-channel high resolution data acquisition system as claimed in claim 2, wherein the receiving board of the multi-channel high resolution data acquisition system boosts the differential input voltage to the input range of the ADC through the voltage boosting circuit.
5. The multi-channel high-resolution data acquisition system as claimed in claim 4, wherein the multi-channel ADC chip acquires multi-channel differential signals, and the design of pre-triggering and window sampling is adopted, so that the incorporation of useless signals is reduced, and the data volume is reduced.
6. The multi-channel high-resolution data acquisition system according to claim 2, wherein the receiving board stores the acquired data in SDRAM by using the FPGA controller of the receiving board, and uploads the data to the main board through the LVDS transmitting circuit, and the receiving board and the main board control the fast response of signals in a level jump manner.
7. The multi-channel high-resolution data acquisition system as claimed in claim 1, wherein the main board of the multi-channel high-resolution data acquisition system uses the FPGA as a main controller to control the receiver board and process the data transmitted back from the receiver board.
8. The multi-channel high-resolution data acquisition system as claimed in claim 1, wherein a motherboard LVDS receiver of the multi-channel high-resolution data acquisition system receives data of the receiving board and then stores the data into DDR3 through the motherboard FPGA controller.
9. The multi-channel high-resolution data acquisition system as claimed in claim 1, wherein after the data is continuously acquired, the data in the DDR3 is read and uploaded to the upper computer software via the PCIE, and the upper computer software receives the data returned by the PCIE bus, performs channel separation, waveform filtering, database backup, and the like, and finally realizes display and storage of the data.
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| CN202111018655.8A CN113703370A (en) | 2021-09-01 | 2021-09-01 | Multichannel high-resolution data acquisition system |
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| KR102563459B1 (en) * | 2022-09-07 | 2023-08-04 | 주식회사 아인스페이스 | Voltage Mathcing Board |
| KR102604219B1 (en) * | 2022-09-07 | 2023-11-20 | 주식회사 아인스페이스 | Method and System for Detecting Faults on High Resolution Data |
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