CN201130369Y - Multichannel synchronous data capturing card based on VXI bus - Google Patents

Multichannel synchronous data capturing card based on VXI bus Download PDF

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Publication number
CN201130369Y
CN201130369Y CNU2007203113261U CN200720311326U CN201130369Y CN 201130369 Y CN201130369 Y CN 201130369Y CN U2007203113261 U CNU2007203113261 U CN U2007203113261U CN 200720311326 U CN200720311326 U CN 200720311326U CN 201130369 Y CN201130369 Y CN 201130369Y
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CN
China
Prior art keywords
sampling
channel
signal
vxi
synchronous data
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CNU2007203113261U
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Chinese (zh)
Inventor
郭恩全
严昭莹
李小杰
赵涛
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陕西海泰电子有限责任公司
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Application filed by 陕西海泰电子有限责任公司 filed Critical 陕西海泰电子有限责任公司
Priority to CNU2007203113261U priority Critical patent/CN201130369Y/en
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Publication of CN201130369Y publication Critical patent/CN201130369Y/en

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Abstract

The utility model discloses a multi-channel synchronous data acquisition card based on VXI bus, which comprises four fully independent daughter boards for adjusting analog signal and one motherboard, wherein, an FPGA chip, an SDRAM chip and a VXI interface chip are integrated on the mother board; a conditioning circuit for analog signal and an A/D converter are integrated on the daughter board; each daughter board has independent signal acquisition channel; each channel has one independent 16 bit A/D converter and signal conditioning circuit and independently collaterally samples; highest sampling for each channel is 2M; frequency division can be downward made for sampling rate. The multi-channel synchronous data acquisition card has the advantages of high sampling rate, high sampling precision of more excellent than per mill one thousandth per mill, big volume and fast speed of data memory, high peak value of the handling capacity up to 320MB/S, and ability to lower influence of signal burr upon sequential logic, improve the stability of the card, guarantee the sampling synchronism of a plurality of channels, and adapt to application place with higher requirement of phase.

Description

A kind of multi-channel synchronous data acquisition card based on vxi bus
Technical field
The utility model relates to the virtual instrument technique field, refers to a kind of synchronous data collection card based on vxi bus.
Background technology
Both at home and abroad the high sampling rate of existing 16 VXI data collecting cards all is lower than 1MSa/s, and is all smaller at the plate buffer memory.Along with quick development of modern science and technology, especially in Aero-Space, military field, the frequency analog signal that gather progressively rises, and the user is also more and more higher for the signal sampling accuracy requirement of gathering, for also requiring bigger at the plate buffer memory.In this case, existing VXI synchronous collecting card does not all satisfy this demand.
Summary of the invention
The purpose of this utility model is to overcome the shortcoming of above-mentioned prior art, and a kind of high sampling rate,, multi-channel synchronous data acquisition card based on vxi bus that sampling precision high big at the plate buffer memory are provided.
The technical solution of the utility model is a kind of multi-channel synchronous data acquisition card based on vxi bus, fully independently analog signal conditioner daughter board and 1 motherboard are formed by 4 for every integrated circuit board, be integrated with fpga chip, SDRAM chip, VXI interface chip on motherboard, this plate is 8 layers of printed board; Be integrated with analog signal conditioner circuit, A/D converter on daughter board, this plate is 4 layers of printed board; Each daughter board has independently signal sampling channel, and each passage has 1 independently 16 A/D converters and signal conditioning circuit, each passage independent parallel sampling, and the highest 2M that is sampled as of every passage, sampling rate is frequency division downwards.
All A/D sampling clocks of this capture card are final all from the same clock of VXI backboard, and the A/D sampling clock is isometric.
The notebook data capture card detects and user's rig-site utilization through the laboratory, reaches following main effect:
1. sampling rate height.Adopting the high sampling rate of 16 A/D converters is 2M, and sampling rate is frequency division downwards.
2. sampling precision height.Adopt noiselike signal conditioning technology, programme-controlled gain, program control filtering and multiple spot collimation technique, the sampling precision of this capture card is better than 1 ‰.
3. data storage capacity is big, speed is fast.Every passage adopts the SDRAM of 128MB as data-carrier store, and frequency of operation is 80MHz, and the peak-data handling capacity can reach 320MB/S.
4.FPGA global clock, synchronous design method are all adopted in inside, use synchronous design method can reduce the influence of signal burr to sequential logic greatly, improve the stability of integrated circuit board.
5. all A/D sampling clocks of this capture card are final all from the same clock of VXI backboard, and the A/D sampling clock is isometric in printed board, has guaranteed the synchronism of a plurality of channel sample, is very suitable for the demanding application places of phase place.
Description of drawings
Fig. 1 VXI synchronous collecting card general structure block diagram.
Fig. 2 capture card single channel structural drawing.
Fig. 3 FPGA inner body structural drawing.
Fig. 4 simulating signal receiving element schematic diagram.
Fig. 5 programme-controlled gain unit schematic diagram.
Fig. 6 program control filtering unit schematic diagram.
Fig. 7 A/D converter unit schematic diagram.
Fig. 8 trigger element schematic diagram.
Fig. 9 clock generator unit schematic diagram.
Embodiment
Below in conjunction with Figure of description, be example with 4 passage capture cards, describe embodiment of the present utility model in detail, but embodiment of the present utility model is not limited thereto.
Hardware architecture as shown in Figure 1, fully independently analog signal conditioner daughter board and 1 motherboard are formed by 4 for every integrated circuit board.Motherboard mainly finish digital signal control, transmission and with the vxi bus interface.Motherboard is made of fpga chip EP20K100QC, SDRAM chip K4S511632B, VXI interface chip IT9010 etc., and this plate is 8 layers of printed board.On daughter board, be integrated with analog signal conditioner circuit, A/D converter.
The simulation daughter board is finished reception, signal selection, program control amplification and the filter function of simulating signal, finally simulating signal is sent in the A/D converter and changes.This simulation daughter board is 4 layers of printed board, and mimic channel and digital circuit are isolated fully, to reduce the interference of high-speed digital circuit to low frequency analog circuit.
FPGA finishes the operation control of whole acquisition channel.Digital signal after the A/D conversion is temporarily stored in the K4S511632B data-carrier store under the control of EP20K100QC.When the storage data among the K4S511632B reach the memory length that upper layer software (applications) sets, just be sent in the host computer and go by vxi bus interface IT9010.
As shown in Figure 2, synchronous collecting card has the input of 4 tunnel simulating signals, veneer of the common composition of this 4 road acquisition channel.4 data acquisition channels in each veneer are separate, use resource alone, can reach the isolation fully of each passage like this.4 acquisition channels are shared same vxi bus interface resource in the veneer, so just can guarantee for computing machine the corresponding functional module of veneer, rather than 4 functional modules.
As shown in Figure 9, the clock generator unit produces the required clock of this passage work, and this clock is by the 10MHz reference clock on the vxi bus backboard is carried out getting after 8 frequencys multiplication.
As shown in Figure 8, trigger pip takes place and the trigger pip transmission unit is judged the trigger pip of outside input or produced the trigger pip that this passage outputs to other passage, guarantees the synchronous data collection between each passage.
Reference voltage is a precision voltage source, is used for the gain size of calibrated analog passage, and the precision of compensation A/D transformation result makes the accurate size of reflected input signal of data after the compensation, and the distortion of analog channel is kept to minimum, satisfies the distortion requirement of system signal; The calibration of analog channel need be carried out the A/D conversion of reference voltage under all gain situations, compares with notional result with the actual converted result, draws the yield value of analog channel reality this moment, the channel gain value during as real work.
Single-ended operational amplifier receives single-ended signal, and differential operational amplifier receives differential signal, and as shown in Figure 4, single-ended, differential signal is received by the OP37 of different connections respectively, and direct current and AC coupling mode realize by signal selecting switch MAX311.Calibration voltage is connected to the reference voltage input of signal selecting switch, FPGA discerns the signal type that current needs are chosen according to the control signal on upper strata, thereby export different control signals to signal selecting switch, guarantee the actual signal type of signal that is input to the capture card analog channel for needing.
In order to make the A/D transformation result have best signal to noise ratio (S/N ratio), gain-programmed amplifier need be to amplifying through the simulating signal behind the signal selecting switch gating, guarantee the maximum switching signal value of the amplitude of signal near A/D converter, concrete gain size can be decided according to the range of current input signal.As shown in Figure 5, the simulating signal after the reception is sent to prime amplifier OP37 and carries out first order amplification, according to the range of signal, also needs to carry out the second level and amplifies.Amplify by D/A converter TLC7528 and OP37 realization programme-controlled gain the second level.
As shown in Figure 6, for effective filtering interference signals, therefore, the low-pass filter of different gears will be selected according to the frequency of input signal.The gear of wave filter is divided into 200KHz, 100KHz, and 50KHz, 10KHz selects for use the wave filter LTC1069-7 of LINEAR company to realize.This wave filter is 8 rank linear phase low-pass filters, can be by the simple cutoff frequency that changes input clock frequency adjusting wave filter.
As shown in Figure 7, the filtered simulating signal of process is delivered among 16 A/D converter ADS8411 and is changed, and this A/D converter inside provides the reference of 4.096V, parallel data output.
A/D converter is finished the conversion of simulating signal, and the digital signal after the conversion is received by FPGA, and is stored among the SDRAM.
SDRAM storage of collected data, when the sampled data of storing among the SDRAM reaches the memory length that upper layer software (applications) sets, the FPGA central control unit just reads sampled data to the vxi bus application and interrupts, vxi bus just reads sampled data among the SDRAM by vxi bus after receiving look-at-me.
FPGA finishes the operation control of whole acquisition channel, and whole veneer performance is had conclusive effect.FPGA finishes the interface of A/D translation data; The refreshing of SDRAM, reading and writing control; The control of passage duty (acquisition controlling, trigger mode, the control of A/D sampling rate, interchannel synchro control, gain control, gain calibration control); The SDRAM data are to the control of vxi bus interface; The request vxi bus is read the control of SDRAM data interruption; Vxi bus is write the controlled variable interface unit, comes the duty of control channel; Vxi bus read channel FPGA state parameter interface unit etc.Fig. 3 is the structural drawing in the FPGA.Global clock, synchronous design method are all adopted in FPGA inside, use synchronous design method can reduce the influence of signal burr to sequential logic greatly.

Claims (2)

1, a kind of multi-channel synchronous data acquisition card based on vxi bus, it is characterized in that: fully independently analog signal conditioner daughter board and 1 motherboard are formed by 4 for every integrated circuit board, be integrated with fpga chip, SDRAM chip, VXI interface chip on motherboard, this plate is 8 layers of printed board; Be integrated with analog signal conditioner circuit, A/D converter on daughter board, this plate is 4 layers of printed board; Each daughter board has independently signal sampling channel, and each passage has 1 independently 16 A/D converters and signal conditioning circuit, each passage independent parallel sampling, and the highest 2M that is sampled as of every passage, sampling rate is frequency division downwards.
2, a kind of multi-channel synchronous data acquisition card based on vxi bus as claimed in claim 1 is characterized in that: all A/D sampling clocks of this capture card are final all from the same clock of VXI backboard, and the A/D sampling clock is isometric.
CNU2007203113261U 2007-12-20 2007-12-20 Multichannel synchronous data capturing card based on VXI bus CN201130369Y (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102521182A (en) * 2011-11-23 2012-06-27 华南师范大学 Extensible multichannel parallel real-time data acquisition device and method
CN102522959A (en) * 2011-12-06 2012-06-27 南京浩之德智能科技有限公司 Peripheral component interconnect extensions for instrument (PXI)-bus-based charge amplification device
CN103092100A (en) * 2013-01-10 2013-05-08 湘潭大学 Control and display device with synchronous acquisition of data and multi-picture display achievable
CN103218311A (en) * 2013-03-19 2013-07-24 中国科学院声学研究所 Virtual FIFO (First In, First Out) device realized by adopting SRAM (static random-access memory)
CN103246225A (en) * 2013-05-03 2013-08-14 奇瑞汽车股份有限公司 FPGA (Field Programmable Gata Array)-based multiway simultaneous sampling system realized by LVDS (Low Voltage Differential Signaling) interfaces
CN103336667A (en) * 2013-07-05 2013-10-02 中国科学院光电技术研究所 General multi-channel data collection system
CN104122851A (en) * 2013-04-26 2014-10-29 中国科学院声学研究所 Multichannel large-dynamic range data acquisition system
CN104378114A (en) * 2014-10-23 2015-02-25 西安电子科技大学 Method for achieving synchronization of multichannel analog-digital converter
US20150192480A1 (en) * 2012-07-24 2015-07-09 Commissariat à I'énergie atomique et aux énergies alternatives Self-calibrating calorimeter using electrical substitution
CN107966723A (en) * 2017-11-22 2018-04-27 中国人民解放军国防科技大学 A kind of multi tate multichannel time synchronization High-speed Data Recording System

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102521182A (en) * 2011-11-23 2012-06-27 华南师范大学 Extensible multichannel parallel real-time data acquisition device and method
CN102521182B (en) * 2011-11-23 2015-05-06 华南师范大学 Extensible multichannel parallel real-time data acquisition device and method
CN102522959A (en) * 2011-12-06 2012-06-27 南京浩之德智能科技有限公司 Peripheral component interconnect extensions for instrument (PXI)-bus-based charge amplification device
US10228295B2 (en) * 2012-07-24 2019-03-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Self-calibrating calorimeter using electrical substitution
US20150192480A1 (en) * 2012-07-24 2015-07-09 Commissariat à I'énergie atomique et aux énergies alternatives Self-calibrating calorimeter using electrical substitution
CN103092100A (en) * 2013-01-10 2013-05-08 湘潭大学 Control and display device with synchronous acquisition of data and multi-picture display achievable
CN103218311A (en) * 2013-03-19 2013-07-24 中国科学院声学研究所 Virtual FIFO (First In, First Out) device realized by adopting SRAM (static random-access memory)
CN104122851A (en) * 2013-04-26 2014-10-29 中国科学院声学研究所 Multichannel large-dynamic range data acquisition system
CN103246225A (en) * 2013-05-03 2013-08-14 奇瑞汽车股份有限公司 FPGA (Field Programmable Gata Array)-based multiway simultaneous sampling system realized by LVDS (Low Voltage Differential Signaling) interfaces
CN103246225B (en) * 2013-05-03 2016-06-08 奇瑞新能源汽车技术有限公司 The multichannel that a kind of LVDS interface based on FPGA realizes is sampled system simultaneously
CN103336667A (en) * 2013-07-05 2013-10-02 中国科学院光电技术研究所 General multi-channel data collection system
CN104378114A (en) * 2014-10-23 2015-02-25 西安电子科技大学 Method for achieving synchronization of multichannel analog-digital converter
CN104378114B (en) * 2014-10-23 2017-12-22 西安电子科技大学 A kind of method for realizing that multipath A/D converter is synchronous
CN107966723A (en) * 2017-11-22 2018-04-27 中国人民解放军国防科技大学 A kind of multi tate multichannel time synchronization High-speed Data Recording System
CN107966723B (en) * 2017-11-22 2019-10-08 中国人民解放军国防科技大学 A kind of multi tate multichannel time synchronization High-speed Data Recording System

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