CN219039380U

CN219039380U - Comprehensive electromagnetic receiver

Info

Publication number: CN219039380U
Application number: CN202222943032.8U
Authority: CN
Inventors: 杨艳军; 刘剑; 赵宗杰; 孙刚; 陈小剑; 杨晓明
Original assignee: China Institute of Radio Wave Propagation CETC 22 Research Institute
Current assignee: China Institute of Radio Wave Propagation CETC 22 Research Institute
Priority date: 2022-11-06
Filing date: 2022-11-06
Publication date: 2023-05-16
Anticipated expiration: 2032-11-06

Abstract

The utility model discloses a comprehensive electromagnetic receiver, which comprises an acquisition control circuit, a measurement channel, a GPS (global positioning system) and a clock module and a calibration module, wherein the measurement channel, the GPS and the clock module and the calibration module are electrically connected with the acquisition control circuit, a power supply supplies power to the electromagnetic receiver, the measurement channel comprises an input protection circuit, a first program-controlled gain amplification circuit group, a filter circuit, a second program-controlled gain amplification circuit group and an A/D (analog/digital) conversion circuit which are electrically connected together in sequence, wherein the input protection circuit receives an input signal, and the first program-controlled gain amplification circuit group, the second program-controlled gain amplification circuit group and the A/D conversion circuit are electrically connected with the acquisition control circuit. The integrated electromagnetic receiver disclosed by the utility model has the advantages that the acquisition control circuit adopts a system on a chip, the FPGA and the processor are integrated in a single chip, and the overall power consumption is reduced.

Description

Comprehensive electromagnetic receiver

Technical Field

The utility model relates to the field of geophysical prospecting and geomagnetic disturbance measurement by an magnetotelluric method, in particular to a comprehensive electromagnetic receiver in the field.

Background

The existing magnetotelluric measurement system mainly comprises an embedded computer, an acquisition control circuit, a measurement channel, a calibration circuit and the like. The acquisition control circuit generally adopts an FPGA device to control the acquisition of data, and an embedded computer is used as a man-machine interface and a data storage and management device. The main disadvantages are: 1) The communication bandwidth between the FPGA device and the embedded computer is limited, which is not beneficial to the collection of long-time high-speed signals; 2) Both devices require power consumption, which is not beneficial to the low-power-consumption miniaturized design of the electromagnetic measurement system. In order to improve the dynamic range of the existing magnetotelluric measuring system, the measuring channel adopts an integrated program-controlled gain amplifier to amplify signals, and the integrated program-controlled gain amplifier itself has larger noise, so that the integrated program-controlled gain amplifier also introduces larger noise while amplifying signals, thereby being unfavorable for the measurement of weak signals.

Disclosure of Invention

The utility model aims to solve the technical problem of providing a comprehensive electromagnetic receiver with high communication bandwidth and small circuit noise.

In order to solve the technical problems, the utility model adopts the following technical scheme:

in a comprehensive electromagnetic receiver, the improvement comprising: the electromagnetic receiver comprises an acquisition control circuit, a measurement channel, a GPS (global positioning system) and a clock module and a calibration module, wherein the measurement channel, the GPS and the clock module and the calibration module are electrically connected with the acquisition control circuit, a power supply supplies power to the electromagnetic receiver, the measurement channel comprises an input protection circuit, a first program-controlled gain amplification circuit group, a filter circuit, a second program-controlled gain amplification circuit group and an A/D (analog/digital) conversion circuit which are electrically connected together in sequence, wherein the input protection circuit receives an input signal, and the first program-controlled gain amplification circuit group, the second program-controlled gain amplification circuit group and the A/D conversion circuit are electrically connected with the acquisition control circuit.

Furthermore, the acquisition control circuit adopts a system on a chip, and an FPGA and a processor are integrated in a single chip.

Further, there are more than three measurement channels.

Further, the first program-controlled gain amplifying circuit group and the second program-controlled gain amplifying circuit group are formed by cascading more than one program-controlled gain amplifying circuit, the circuit structures of the program-controlled gain amplifying circuits are identical, the program-controlled gain amplifying circuits are built by two operational amplifiers, two analog switches and a plurality of resistors, differential signals are input to the positive input ends of the operational amplifiers, the negative input ends of the operational amplifiers are electrically connected with the output ends of the analog switches, the resistors are connected between the output ends of the two operational amplifiers in series, the input ends of the analog switches are electrically connected with the output ends of the operational amplifiers and leads between the resistors respectively, and control pins of the analog switches are electrically connected with the acquisition control circuit.

Further, the system also comprises a state display module, a storage circuit and a data buffer circuit which are electrically connected with the acquisition control circuit.

The beneficial effects of the utility model are as follows:

the integrated electromagnetic receiver disclosed by the utility model has the advantages that the acquisition control circuit adopts a system on a chip, the FPGA and the processor are integrated in a single chip, and the overall power consumption is reduced. The single chip realizes all functions of the original FPGA and the embedded computer, the communication bandwidth between the FPGA and the processor in the single chip is far higher than that between the FPGA and the embedded computer, the bandwidth between the acquisition system and the data management system is improved, the bottleneck problem of high-speed large data transmission is solved, long-time acquisition of high-speed data is possible, and the application range of the comprehensive electromagnetic receiver is widened. The program-controlled gain amplifying circuit built by the discrete components has smaller circuit noise, reduces the noise of a measuring channel while guaranteeing the dynamic range, and greatly improves the weak signal measuring capability of the comprehensive electromagnetic receiver.

Drawings

Fig. 1 is a block diagram showing the construction of an integrated electromagnetic receiver according to embodiment 1 of the present utility model;

FIG. 2 is a block diagram showing the constitution of a measurement channel in the integrated electromagnetic receiver disclosed in embodiment 1 of the present utility model;

fig. 3 is a schematic circuit diagram of a gain-controlled amplifying circuit in the integrated electromagnetic receiver according to embodiment 1 of the present utility model.

Reference numerals: the system comprises a 1-acquisition control circuit, a 2-measurement channel, a 21-input protection circuit, a 22-first program-controlled gain amplification circuit group, a 23-filter circuit, a 24-second program-controlled gain amplification circuit group, a 25-A/D conversion circuit, a 3-GPS and clock module, a 31-operational amplifier, a 32-analog switch, a 33-resistor, a 4-calibration module, a 5-power supply, a 6-state display module, a 7-storage circuit and an 8-data buffer circuit.

Detailed Description

The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

In embodiment 1, as shown in fig. 1, the embodiment discloses a comprehensive electromagnetic receiver, which comprises an acquisition control circuit 1, a six-way measurement channel 2 electrically connected with the acquisition control circuit, a GPS and clock module 3 and a calibration module 4, wherein a power supply 5 supplies power to the electromagnetic receiver.

The acquisition control circuit is the core of the comprehensive electromagnetic receiver, a main control chip of the acquisition control circuit adopts an SOC (system on a chip), and an FPGA and a processor are integrated in a single chip. The main functions include: setting parameters such as channel sampling rate, channel gain, filter, DC compensation voltage and the like; completing channel self-calibration, magnetic sensor self-calibration, electrode grounding resistance measurement and the like; according to the set time, controlling the measuring channel to acquire data on time, receiving and caching the AD converted digital signals; receiving GPS time information and a second pulse signal, and realizing synchronous data acquisition of a plurality of electromagnetic receivers; a user can log in the human-computer interface through a browser to control parameter setting of the comprehensive electromagnetic receiver; the collected data is stored on a storage device.

In the embodiment, a main control chip of the acquisition control circuit adopts a Zynq series SOC system of Xilinx company, an ARM processor and FPGA resources are built in the Zynq series SOC system, and the ARM processor and the FPGA can carry out high-speed communication through an AXI bus to realize long-time high-speed data acquisition. Meanwhile, the ARM processor and the FPGA are integrated into one chip, so that the space of a board card is saved, and the power consumption of the electromagnetic receiver is greatly reduced.

The function of the measuring channel is to amplify, filter and A/D convert the signal collected by the sensor. As shown in fig. 2, the measurement channel 2 includes an input protection circuit 21, a first programmable gain amplification circuit group 22, a filter circuit 23, a second programmable gain amplification circuit group 24 and an a/D conversion circuit 25 electrically connected together in this order, wherein the input protection circuit 21 receives an input signal, and the first programmable gain amplification circuit group 22, the second programmable gain amplification circuit group 24 and the a/D conversion circuit 25 are electrically connected with the acquisition control circuit 1. The number of the measuring channels is more than three.

The first program-controlled gain amplifying circuit group and the second program-controlled gain amplifying circuit group are formed by cascading more than one program-controlled gain amplifying circuit, as shown in fig. 3, the circuit structures of the program-controlled gain amplifying circuits are identical, and are built by two low-noise operational amplifiers 31, two analog switches 32 and a plurality of resistors 33, and the program-controlled gain amplifying circuits can amplify input differential signals and generate amplified differential signals. Differential signals (in+ and In-) are input to the positive input end of the operational amplifier, the negative input end of the operational amplifier is electrically connected with the output end of the analog switch, a plurality of resistors with different resistance values are connected In series between the output ends of the two operational amplifiers, the input ends of the analog switch are respectively electrically connected with the output ends of the operational amplifier and leads between the resistors, a control pin of the analog switch is electrically connected with the acquisition control circuit, CPU, MCU, DSP, FPGA In the acquisition control circuit sends out control signals, the amplification factors and the amplification gains of the program-controlled gain amplifying circuit are changed by controlling the working state of the analog switch to select different resistors, and the amplification gains corresponding to the resistance values of the marked resistors In fig. 3 are 1, 4, 16 and 64 times of gains, and the acquisition control circuit selects among the four gains through control signals. The resistor with the precision not lower than 0.1% is generally selected to realize higher gain precision. The analog switch can be, but not limited to, a high-performance analog switch such as ADG 659. The operational amplifier selects low noise operational amplifiers such as ADA4084, ADA4522 and the like.

The GPS and clock module is used for receiving the position information and performing time synchronization when a plurality of electromagnetic receivers work simultaneously. The calibration module generates a high-stability and high-precision reference signal for self-checking and calibration of the electromagnetic receiver. The system also comprises a state display module 6, a storage circuit 7 and a data buffer circuit 8 which are electrically connected with the acquisition control circuit.

Claims

1. An integrated electromagnetic receiver, characterized by: the electromagnetic receiver comprises an acquisition control circuit, a measurement channel, a GPS (global positioning system) and a clock module and a calibration module, wherein the measurement channel, the GPS and the clock module and the calibration module are electrically connected with the acquisition control circuit, a power supply supplies power to the electromagnetic receiver, the measurement channel comprises an input protection circuit, a first program-controlled gain amplification circuit group, a filter circuit, a second program-controlled gain amplification circuit group and an A/D (analog/digital) conversion circuit which are electrically connected together in sequence, wherein the input protection circuit receives an input signal, and the first program-controlled gain amplification circuit group, the second program-controlled gain amplification circuit group and the A/D conversion circuit are electrically connected with the acquisition control circuit.

2. The integrated electromagnetic receiver of claim 1, wherein: the acquisition control circuit adopts a system on a chip, and an FPGA and a processor are integrated in a single chip.

3. The integrated electromagnetic receiver of claim 1, wherein: there are more than three measuring channels.

4. The integrated electromagnetic receiver of claim 1, wherein: the first program-controlled gain amplifying circuit group and the second program-controlled gain amplifying circuit group are formed by cascading more than one program-controlled gain amplifying circuit, the circuit structures of the program-controlled gain amplifying circuits are identical, the program-controlled gain amplifying circuits are built by two operational amplifiers, two analog switches and a plurality of resistors, differential signals are input to the positive input end of each operational amplifier, the negative input end of each operational amplifier is electrically connected with the output end of each analog switch, the resistors are connected between the output ends of the two operational amplifiers in series, the input ends of each analog switch are electrically connected with the output ends of each operational amplifier and leads between the resistors respectively, and the control pins of each analog switch are electrically connected with the acquisition control circuit.

5. The integrated electromagnetic receiver of claim 1, wherein: the system also comprises a state display module, a storage circuit and a data buffer circuit which are electrically connected with the acquisition control circuit.