CN218240901U - PXIe interface-based voltage signal 16-channel parallel synchronous acquisition equipment - Google Patents

Abstract

The utility model relates to a signal processing technology field specifically is a parallel synchronous acquisition equipment of 16 passageways of voltage signal based on PXIe interface, include: the system comprises a signal isolator, a gain controller, an analog-to-digital converter, an FPGA chip and a PXIe interface; the FPGA chip communicates with an external computer through a PXIe interface; the signal input end of the signal isolator is used for receiving a differential analog signal to be detected, and the signal output end of the signal isolator is connected with the gain controller; the signal input end of the gain controller is used for receiving the differential analog signal and performing gain control on the differential analog signal, and the signal output end of the gain controller is connected with the analog-to-digital converter; the signal input end of the analog-to-digital converter is used for receiving the amplified or attenuated differential analog signal, and the signal output end of the analog-to-digital converter is connected with the FPGA chip for signal processing. The utility model discloses an improved the maximum sampling rate and the passageway figure that the single channel can support to and the sampling precision.

Description

PXIe interface-based voltage signal 16-channel parallel synchronous acquisition equipment

Technical Field

The utility model relates to a signal processing technology field specifically is a parallel synchronous acquisition equipment of 16 passageways of voltage signal based on PXIe interface.

Background

Fig. 1 is a block diagram showing a structural principle of a multi-channel parallel acquisition device in the prior art, the conventional multi-channel parallel acquisition device basically uses PCI, USB, a network and a computer to complete communication, and the basic principle is as follows: analog signals are amplified, filtered and the like through an analog conditioning circuit, then reach an ADC to complete analog-to-digital conversion, then digital signals are sent to an FPGA to be processed, and then are transmitted to an external computer through a circuit board interface.

However, the USB, PCI and network port transmission speed adopted in the prior art is limited, so that the number of channels and the maximum sampling rate which can be supported by the acquisition card are limited; due to the fact that a common reference clock source and a common synchronous signal are lacked among the plurality of board cards, high-precision synchronization among the plurality of acquisition cards cannot be completed, and the multichannel synchronization performance is limited; due to the fact that no on-board external memory exists, on-board FIFOs are generally small, and the number of points capable of being cached by the acquisition card is limited. In view of this, we propose a PXIe interface-based voltage signal 16-channel parallel synchronous acquisition device.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a parallel synchronous acquisition equipment of 16 passageways of voltage signal based on PXIe interface to solve the problem that proposes in the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a PXIe interface-based voltage signal 16-channel parallel synchronous acquisition device comprises: the device comprises a signal isolator, a gain controller, an analog-to-digital converter, an FPGA chip and a PXIe interface;

the FPGA chip communicates with an external computer through the PXIe interface;

the signal input end of the signal isolator is used for receiving a differential analog signal to be detected, and the signal output end of the signal isolator is connected with the gain controller;

the signal input end of the gain controller is used for receiving the differential analog signal and performing gain control on the differential analog signal, and the signal output end of the gain controller is connected with the analog-to-digital converter;

the signal input end of the analog-to-digital converter is used for receiving the amplified or attenuated differential analog signal and performing analog-to-digital conversion on the amplified or attenuated differential analog signal to generate a digital signal, and the signal output end of the analog-to-digital converter is connected with the FPGA chip to process the digital signal.

Preferably, a FLASH memory is further connected to the FPGA chip for storing a firmware program of the FPGA chip.

Preferably, the FPGA chip is further connected with a FIFO memory for serving as an onboard cache of the FPGA chip.

Preferably, the FPGA chip is further connected with an IIC chip for storing factory ID information of the FPGA chip and calibration information of the analog path.

Preferably, a DIO interface and a PFI interface are further connected to the FPGA chip.

Preferably, a DIO interface and a PFI interface are further connected to the FPGA chip.

Compared with the prior art, the beneficial effects of the utility model are that: according to the PXIe interface-based voltage signal 16-channel parallel synchronous acquisition equipment, the PXIe interface is adopted to greatly improve the maximum sampling rate and the number of channels which can be supported by a single channel, the maximum sampling rate of a single analog signal acquisition channel is improved to 5Msps, and the equipment can have the synchronous precision of less than 1ns absolute time measured under the 5Msps sampling rate by using the FPGA chip and the PXIe interface.

Drawings

FIG. 1 is a block diagram of the structure of a multi-channel parallel acquisition device in the prior art;

fig. 2 is a schematic block diagram of the structure of the present invention.

In the figure: 1. a signal isolator; 2. a gain controller; 3. an analog-to-digital converter; 4. an FPGA chip; 41. A FLASH memory; 42. a FIFO memory; 43. an IIC chip; 44. a DIO interface; 45. a PFI interface; 5. and PXIe interface.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.

In the description of this patent, it is noted that unless otherwise specifically stated or limited, the terms "mounted," "connected," and "disposed" are to be construed broadly and can include, for example, fixedly connected, disposed, detachably connected, disposed, or integrally connected and disposed. The specific meaning of the above terms in this patent may be understood by those of ordinary skill in the art as appropriate.

A PXIe interface-based voltage signal 16-channel parallel synchronous acquisition device, as shown in fig. 2, includes: the system comprises a signal isolator 1, a gain controller 2, an analog-to-digital converter 3, an FPGA chip 4 and a PXIe interface 5; the FPGA chip 4 communicates with an external computer through a PXIe interface 5; the signal input end of the signal isolator 1 is used for receiving a differential analog signal to be detected, and the signal output end is connected with the gain controller 2; the signal input end of the gain controller 2 is used for receiving the differential analog signal and performing gain control (signal amplification or reduction) on the differential analog signal, and the signal output end is connected with the analog-to-digital converter 3; the signal input end of the analog-to-digital converter 3 is used for receiving the amplified or attenuated differential analog signal and performing analog-to-digital conversion on the amplified or attenuated differential analog signal to generate a digital signal, and the signal output end of the analog-to-digital converter 3 is connected with the FPGA chip 4 to process the digital signal. The voltage signal 16-channel parallel synchronous acquisition equipment adopts a PXIe interface, the highest transmission rate can reach 2GB/s, the maximum sampling rate and the number of channels which can be supported by a single channel are greatly improved, AD7961 is adopted as an analog-to-digital converter, the maximum sampling rate of a single analog signal acquisition channel is improved to 5Msps, PXIe _ CLK100 and PXIe _ SYNC100 signals are used as a reference clock source and low-speed synchronous pulses between an FPGA chip 4 and the PXIe interface 5 respectively, and therefore the equipment has the synchronization accuracy of less than 1ns absolute time measured at the sampling rate of 5 Msps.

Further, the FPGA chip 4 is further connected to a FLASH memory 41 for storing a firmware program of the FPGA chip 4, and when the FPGA chip is powered on, the firmware is loaded into the FPGA chip 4 from the FLASH memory 41, so as to complete firmware program configuration of the FPGA chip.

Specifically, the FPGA chip 4 is further connected with an FIFO memory 42 for serving as an onboard cache of the FPGA chip 4, and a 512M DDR3 FIFO memory is used as a cache, so that the onboard cache is up to 256M samples, and thus, long-time, multi-channel continuous acquisition becomes possible.

It should be noted that the IIC chip 43 is further connected to the FPGA chip 4, and is configured to store factory ID information of the FPGA chip 4 and calibration information of the analog path, and provide calibration for the analog signal during analog acquisition.

In addition, a DIO interface 44 and a PFI interface 45 are connected to the FPGA chip 4. The PFI Interface 45 is a PFI (Programmable Function Interface) Programmable digital Function Interface, whose functions can be flexibly configured through software, and is generally used for input and output of trigger signals and custom digital signal input and output, and the Interface is used as a group of interfaces of an acquisition card, can be used as trigger input for AI acquisition, external clock input, and can also be used for simulating a low-speed serial bus Interface, etc.; the DIO interface 44 is a DIO (Digital Input Output) high-speed Digital Input/Output interface, and is generally used for high-speed Digital signal Input/Output, and is used as a supplement to a board card simple analog signal acquisition function, so that the functions of the board card are expanded, and the Digital Input/Output interface is suitable for a complex industrial control scene.

When the PXIe interface-based voltage signal 16-channel parallel synchronous acquisition equipment is used, the equipment is communicated with a computer through the PXIe interface 5; a GA [4 ] pin of the PXIe interface 5 is used for identifying the position of the current board card, a PXI _ Trigger [7 ] pin is used for routing a Trigger synchronization signal, and the PXIe _ CLK100 and the PXIe _ SYNC100 provide a high-precision synchronization clock and a low-frequency synchronization pulse for the board card, so that the board card completes high-precision synchronization;

the analog signal to be tested is in a differential mode, is accessed from the signal isolator 1 and enabled as required, so that better anti-interference performance is provided for multiple channels, the gain controller 2 is responsible for controlling the gain of the analog signal, so that multiple ranges are provided for the board card, and the analog-to-digital converter 3 is used as an analog-to-digital conversion device of an analog signal acquisition channel, is responsible for converting the analog signal into a digital signal and then sends the digital signal to the FPGA chip 4 for processing;

the driving program is divided into two parts of FPGA firmware and upper computer driving program, and the FPGA firmware receives the control of the upper computer driving program so as to complete the control of all hardware circuits and the transmission and storage of data; the upper computer driving program is responsible for providing a cross-platform and easy-to-use interface for interaction of a user;

therefore, the utility model discloses a PXIe interface has improved the maximum sampling rate and the passageway figure that the single channel can support greatly, and single analog signal gathers the maximum sampling rate of passageway and has improved 5msps, FPGA chip 4 can let equipment survey under 5Msps sampling rate and possess the synchronous precision less than 1ns absolute time with PXIe interface 5's use.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the description in the above embodiments and the description is only preferred examples of the present invention, and is not intended to limit the present invention, and that the present invention can have various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications all fall into the scope of the claimed invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (5)

1. A PXIe interface-based voltage signal 16-channel parallel synchronous acquisition device is characterized by comprising: the system comprises a signal isolator (1), a gain controller (2), an analog-to-digital converter (3), an FPGA chip (4) and a PXIe interface (5);

the FPGA chip (4) is communicated with an external computer through the PXIe interface (5);

the signal input end of the signal isolator (1) is used for receiving a differential analog signal to be tested, and the signal output end of the signal isolator is connected with the gain controller (2);

the signal input end of the gain controller (2) is used for receiving the differential analog signal and performing gain control on the differential analog signal, and the signal output end of the gain controller is connected with the analog-to-digital converter (3);

the signal input end of the analog-to-digital converter (3) is used for receiving the amplified or attenuated differential analog signal, and the signal output end of the analog-to-digital converter (3) is connected with the FPGA chip (4) to process the digital signal.

2. The PXIe interface-based voltage signal 16-channel parallel synchronous acquisition device according to claim 1, wherein: and the FPGA chip (4) is also connected with a FLASH memory (41) for storing a firmware program of the FPGA chip (4).

3. The PXIe-interface-based voltage signal 16-channel parallel synchronous acquisition device of claim 1, wherein: and the FPGA chip (4) is also connected with an FIFO memory (42) which is used as an onboard cache of the FPGA chip (4).

4. The PXIe interface-based voltage signal 16-channel parallel synchronous acquisition device according to claim 1, wherein: the FPGA chip (4) is also connected with an IIC chip (43) which is used for storing factory ID information of the FPGA chip (4) and calibration information of an analog path.

5. The PXIe-interface-based voltage signal 16-channel parallel synchronous acquisition device of claim 1, wherein: and the FPGA chip (4) is also connected with a DIO interface (44) and a PFI interface (45).

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